Preliminary ...the world's most energy friendly microcontrollers EFM32ZG222 DATASHEET F32/F16/F8/F4 Preliminary • ARM Cortex-M0+ CPU platform • High Performance 32-bit processor @ up to 24 MHz • Wake-up Interrupt Controller • Flexible Energy Management System • 20 nA @ 3 V Shutoff Mode • 0.5 μA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention • 0.9 μA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on Reset, Brown-out Detector, RAM and CPU retention • 46 μA/MHz @ 3 V Sleep Mode • 114 μA/MHz @ 3 V Run Mode, with code executed from flash • 32/16/8/4 KB Flash • 4/4/2/2 KB RAM • 37 General Purpose I/O pins • Configurable push-pull, open-drain, pull-up/down, input filter, drive strength • Configurable peripheral I/O locations • 16 asynchronous external interrupts • Output state retention and wake-up from Shutoff Mode • 4 Channel DMA Controller • 4 Channel Peripheral Reflex System (PRS) for autonomous in- ter-peripheral signaling • Hardware AES with 128-bit keys in 54 cycles • Timers/Counters • 2× 16-bit Timer/Counter • 2×3 Compare/Capture/PWM channels • 1× 24-bit Real-Time Counter • 1× 16-bit Pulse Counter • Watchdog Timer with dedicated RC oscillator @ 50 nA • Communication interfaces • 1× Universal Synchronous/Asynchronous Receiv- er/Transmitter • UART/SPI/SmartCard (ISO 7816)/IrDA/I2S • Triple buffered full/half-duplex operation • Low Energy UART • Autonomous operation with DMA in Deep Sleep Mode •I 2 C Interface with SMBus support • Address recognition in Stop Mode • Ultra low power precision analog peripherals • 12-bit 1 Msamples/s Analog to Digital Converter • 4 single ended channels/ differential channels • On-chip temperature sensor • Current Digital to Analog Converter • Selectable current range between 0.05 and 64 uA • 1× Analog Comparator • Capacitive sensing with up to 5 inputs • Supply Voltage Comparator • Ultra efficient Power-on Reset and Brown-Out Detec- tor • 2-pin Serial Wire Debug interface • Pre-Programmed UART Bootloader • Temperature range -40 to 85 ºC • Single power supply 1.85 to 3.8 V • TQFP48 package 32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for: • Energy, gas, water and smart metering • Health and fitness applications • Smart accessories • Alarm and security systems • Industrial and home automation
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Preliminary...the world's most energy friendly microcontrollers
• 1× 24-bit Real-Time Counter• 1× 16-bit Pulse Counter• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Communication interfaces• 1× Universal Synchronous/Asynchronous Receiv-
er/Transmitter• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S• Triple buffered full/half-duplex operation
• Low Energy UART• Autonomous operation with DMA in Deep Sleep
Mode• I2C Interface with SMBus support
• Address recognition in Stop Mode• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter• 4 single ended channels/ differential channels• On-chip temperature sensor
• Current Digital to Analog Converter• Selectable current range between 0.05 and 64 uA
• 1× Analog Comparator• Capacitive sensing with up to 5 inputs
• Supply Voltage Comparator• Ultra efficient Power-on Reset and Brown-Out Detec-
tor• 2-pin Serial Wire Debug interface• Pre-Programmed UART Bootloader• Temperature range -40 to 85 ºC• Single power supply 1.85 to 3.8 V• TQFP48 package
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for:
• Energy, gas, water and smart metering• Health and fitness applications• Smart accessories
• Alarm and security systems• Industrial and home automation
Preliminary...the world's most energy friendly microcontrollers
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combinationof the powerful 32-bit ARM Cortex-M0+, innovative low energy techniques, short wake-up time fromenergy saving modes, and a wide selection of peripherals, the EFM32ZG microcontroller is well suitedfor any battery operated application as well as other systems requiring high performance and low-energyconsumption. This section gives a short introduction to each of the modules in general terms and alsoshows a summary of the configuration for the EFM32ZG222 devices. For a complete feature set and in-depth information on the modules, the reader is referred to the EFM32ZG Reference Manual.
A block diagram of the EFM32ZG222 is shown in Figure 2.1 (p. 3) .
Figure 2.1. Block Diagram
Clock Management Energy Management
Serial Interfaces I/ O Ports
Core and Memory
Timers and Triggers
32- bit busPeripheral Reflex System
ARM Cortex™ M0+ processor
FlashProgramMemory
High Freq RCOscillator
High Freq Crystal Oscillator
Pulse Counter
Low Freq CrystalOscillator
Low Freq RCOscillator
WatchdogTimer
RAMMemory
GeneralPurposeI/ O
DebugInterface
ExternalInterrupts
PinReset
ZG222F32/ 16/ 8/ 4
USART I2C
Power- onReset
VoltageRegulator
VoltageComparator
Brown- outDetector
Timer/Counter
Real TimeCounter
Current DAC
Ultra Low Freq RCOscillator
LowEnergyUart™
PinWakeup
Analog Interfaces
ADC
Security
HardwareAES
DMAController
Analog Comparator
2.1.1 ARM Cortex-M0+ Core
The ARM Cortex-M0+ includes a 32-bit RISC processor which can achieve as much as 0.9 DhrystoneMIPS/MHz. A Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep is in-cluded as well. The EFM32 implementation of the Cortex-M0+ is described in detail in ARM Cortex-M0+Devices Generic User Guide.
2.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface.
2.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32ZG microcontroller.The flash memory is readable and writable from both the Cortex-M0+ and DMA. The flash memory isdivided into two blocks; the main block and the information block. Program code is normally written tothe main block. Additionally, the information block is available for special user data and flash lock bits.There is also a read-only page in the information block containing system and device calibration data.Read and write operations are supported in the energy modes EM0 and EM1.
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The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.This has the benefit of reducing the energy consumption and the workload of the CPU, and enablesthe system to stay in low energy modes when moving for instance data from the USART to RAM orfrom the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMAcontroller licensed from ARM.
2.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32ZG.
2.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32ZG microcon-trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMUcan also be used to turn off the power to unused SRAM blocks.
2.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-boardthe EFM32ZG. The CMU provides the capability to turn on and off the clock on an individual basis to allperipheral modules in addition to enable/disable and configure the available oscillators. The high degreeof flexibility enables software to minimize energy consumption in any specific application by not wastingpower on peripherals and oscillators that are inactive.
2.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli-cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by asoftware failure.
2.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral modulecommunicate directly with each other without involving the CPU. Peripheral modules which send outReflex signals are called producers. The PRS routes these reflex signals to consumer peripherals whichapply actions depending on the data received. The format for the Reflex signals is not given, but edgetriggers and other functionality can be applied by the PRS.
2.1.10 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting asboth a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.The interface provided to software by the I2C module, allows both fine-grained control of the transmissionprocess and close to automatic transfers. Automatic recognition of slave addresses is provided in allenergy modes.
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexibleserial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI,MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, IrDA and I2S devices.
Preliminary...the world's most energy friendly microcontrollers
The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Auto-baud and destructive write are supported. The autobaud feature, interface and commands are describedfurther in the application note.
2.1.13 Low Energy Universal Asynchronous Receiver/Transmitter(LEUART)
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication ona strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/s. The LEUART includes all necessary hardware support to make asynchronous serial communicationpossible with minimum of software intervention and energy consumption.
2.1.14 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-Width Modulation (PWM) output.
2.1.15 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystaloscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is alsoavailable in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 wheremost of the device is powered down.
2.1.16 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadratureencoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source.The module may operate in energy mode EM0 – EM3.
2.1.17 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indi-cating which input voltage is higher. Inputs can either be one of the selectable internal references or fromexternal pins. Response time and thereby also the current consumption can be configured by alteringthe current supply to the comparator.
2.1.18 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt canbe generated when the supply falls below or rises above a programmable threshold. Response time andthereby also the current consumption can be configured by altering the current supply to the comparator.
2.1.19 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bitsat up to one million samples per second. The integrated input mux can select inputs from 4 externalpins and 6 internal signals.
2.1.20 Current Digital to Analog Converter (IDAC)
The current digital to analog converter can source or sink a configurable constant current, which canbe output on, or sinked from pin or ADC. The current is configurable with several ranges of variousstep sizes.
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2.1.21 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit. Encrypting or decrypting one128-bit data block takes 52 HFCORECLK cycles with 128-bit keys. The AES module is an AHB slavewhich enables efficient access to the data and key registers. All write accesses to the AES module mustbe 32-bit operations, i.e. 8- or 16-bit operations are not supported.
2.1.22 General Purpose Input/Output (GPIO)
In the EFM32ZG222, there are 37 General Purpose Input/Output (GPIO) pins, which are divided intoports with up to 16 pins each. These pins can individually be configured as either an output or input. Moreadvanced configurations like open-drain, filtering and drive strength can also be configured individuallyfor the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWMoutputs or USART communication, which can be routed to several locations on the device. The GPIOsupports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on thedevice. Also, the input value of a pin can be routed through the Peripheral Reflex System to otherperipherals.
2.2 Configuration Summary
The features of the EFM32ZG222 is a subset of the feature set described in the EFM32ZG ReferenceManual. Table 2.1 (p. 6) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module Configuration Pin Connections
Cortex-M0+ Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO,
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA and I2S US0_TX, US0_RX. US0_CLK, US0_CS
LEUART0 Full configuration LEU0_TX, LEU0_RX
TIMER0 Full configuration TIM0_CC[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
RTC Full configuration NA
PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]
ACMP0 Full configuration ACMP0_CH[4:0], ACMP0_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[3:0]
IDAC0 Full configuration IDAC0_OUT
AES Full configuration NA
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The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in Table 3.2 (p. 8) , by simu-lation and/or technology characterisation unless otherwise specified.
3.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply volt-age and frequencies, as defined in Table 3.2 (p. 8) , by simulation and/or technology characterisa-tion unless otherwise specified.
3.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions arenot guaranteed. Stress beyond the limits specified in Table 3.1 (p. 8) may affect the device reliabilityor cause permanent damage to the device. Functional operating conditions are given in Table 3.2 (p.8) .
Table 3.1. Absolute Maximum Ratings
Symbol Parameter Condition Min Typ Max Unit
TSTG Storage tempera-ture range
-40 1501 °C
TS Maximum solderingtemperature
Latest IPC/JEDEC J-STD-020Standard
260 °C
VDDMAX External main sup-ply voltage
0 3.8 V
VIOPIN Voltage on any I/Opin
-0.3 VDD+0.3 V
1Based on programmed devices tested for 10000 hours at 150ºC. Storage temperature affects retention of preprogrammed cal-ibration values stored in flash. Please refer to the Flash section in the Electrical Characteristics for information on flash data re-tention for different temperatures.
3.3 General Operating Conditions
3.3.1 General Operating Conditions
Table 3.2. General Operating Conditions
Symbol Parameter Min Typ Max Unit
TAMB Ambient temperature range -40 85 °C
VDDOP Operating supply voltage 1.85 3.8 V
fAPB Internal APB clock frequency 24 MHz
fAHB Internal AHB clock frequency 24 MHz
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tEM10 Transition time from EM1 to EM0 01 HFcoreCLKcycles
tEM20 Transition time from EM2 to EM0 2 µs
tEM30 Transition time from EM3 to EM0 2 µs
tEM40 Transition time from EM4 to EM0 163 µs1Core wakeup time only.
3.6 Power Management
The EFM32ZG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (withoptional filter) at the PCB level. For practical schematic recommendations, please see the applicationnote, "AN0002 EFM32 Hardware Design Considerations".
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ESRLFXO Supported crystalequivalent series re-sistance (ESR)
30 120 kOhm
CLFXOL Supported crystalexternal load range
5 25 pF
DCLFXO Duty cycle 48 50 53.5 %
ILFXO Current consump-tion for core andbuffer after startup.
ESR=30 kOhm, CL=10 pF,LFXOBOOST in CMU_CTRL is1
190 nA
tLFXO Start- up time. ESR=30 kOhm, CL=10 pF,40% - 60% duty cycle hasbeen reached, LFXOBOOST inCMU_CTRL is 1
400 ms
For safe startup of a given crystal, the energyAware Designer in Simplicity Studio contains a tool to helpusers configure both load capacitance and software settings for using the LFXO. For details regardingthe crystal configuration, the reader is referred to application note "AN0016 EFM32 Oscillator DesignConsideration".
3.9.2 HFXO
Table 3.9. HFXO
Symbol Parameter Condition Min Typ Max Unit
fHFXO Supported nominalcrystal Frequency
4 24 MHz
Crystal frequency 24 MHz 30 60 OhmESRHFXO
Supported crystalequivalent series re-sistance (ESR) Crystal frequency 4 MHz 400 1500 Ohm
gmHFXO The transconduc-tance of the HFXOinput transistor atcrystal startup
After calibration, single ended 0.3 mVVADCOFFSET Offset voltage
After calibration, differential 0.3 mV
-1.92 mV/°C
TGRADADCTHThermometer out-put gradient
-6.3 ADCCodes/°C
DNLADC Differential non-lin-earity (DNL)
±0.7 LSB
INLADC Integral non-linear-ity (INL), End pointmethod
±1.2 LSB
MCADC No missing codes 11.9991 12 bits1On the average every ADC will have one missing code, most likely to appear around 2048 +/- n*512 where n can be a value inthe set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonicat all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that ismissing, the neighbour codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scaleinput for chips that have the missing code issue.
The integral non-linearity (INL) and differential non-linearity parameters are explained in Figure 3.24 (p.33) and Figure 3.25 (p. 33) , respectively.
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BIASPROG=0b0000, FULL-BIAS=0 and HALFBIAS=1 inACMPn_CTRL register
0.1 µA
BIASPROG=0b1111, FULL-BIAS=0 and HALFBIAS=0 inACMPn_CTRL register
2.87 µAIACMP Active current
BIASPROG=0b1111, FULL-BIAS=1 and HALFBIAS=0 inACMPn_CTRL register
195 µA
Internal voltage reference off.Using external voltage refer-ence
0 µA
IACMPREF
Current consump-tion of internal volt-age reference
Internal voltage reference 5 µA
Single ended 10 mVVACMPOFFSET Offset voltage
Differential 10 mV
VACMPHYST ACMP hysteresis Programmable 17 mV
CSRESSEL=0b00 inACMPn_INPUTSEL
39 kOhm
CSRESSEL=0b01 inACMPn_INPUTSEL
71 kOhm
CSRESSEL=0b10 inACMPn_INPUTSEL
104 kOhmRCSRES
Capacitive SenseInternal Resistance
CSRESSEL=0b11 inACMPn_INPUTSEL
136 kOhm
tACMPSTART Startup time 10 µs
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage referenceas given in Equation 3.1 (p. 43) . IACMPREF is zero if an external voltage reference is used.
Total ACMP Active Current
IACMPTOTAL = IACMP + IACMPREF (3.1)
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BIASPROG=0b0000 andHALFBIAS=1 in VCMPn_CTRLregister
0.1 µA
IVCMP Active currentBIASPROG=0b1111 andHALFBIAS=0 in VCMPn_CTRLregister. LPREF=0.
14.7 µA
tVCMPREF Startup time refer-ence generator
NORMAL 10 µs
Single ended 10 mVVVCMPOFFSET Offset voltage
Differential 10 mV
VVCMPHYST VCMP hysteresis 17 mV
tVCMPSTART Startup time 10 µs
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register inaccordance with the following equation:
VCMP Trigger Level as a Function of Level Setting
VDD Trigger Level=1.667V+0.034 ×TRIGLEVEL (3.2)
3.14 I2C
Table 3.25. I2C Standard-mode (Sm)
Symbol Parameter Min Typ Max Unit
fSCL SCL clock frequency 0 1001 kHz
tLOW SCL clock low time 4.7 µs
tHIGH SCL clock high time 4.0 µs
tSU,DAT SDA set-up time 250 ns
tHD,DAT SDA hold time 8 34502,3 ns
tSU,STA Repeated START condition set-up time 4.7 µs
tHD,STA (Repeated) START condition hold time 4.0 µs
tSU,STO STOP condition set-up time 4.0 µs
tBUF Bus free time between a STOP and START condition 4.7 µs1For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32ZG Reference Manual.2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10-9 [s] * fHFPERCLK [Hz]) - 5).
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tSU,STA Repeated START condition set-up time 0.6 µs
tHD,STA (Repeated) START condition hold time 0.6 µs
tSU,STO STOP condition set-up time 0.6 µs
tBUF Bus free time between a STOP and START condition 1.3 µs1For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32ZG Reference Manual.2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10-9 [s] * fHFPERCLK [Hz]) - 5).
Table 3.27. I2C Fast-mode Plus (Fm+)
Symbol Parameter Min Typ Max Unit
fSCL SCL clock frequency 0 10001 kHz
tLOW SCL clock low time 0.5 µs
tHIGH SCL clock high time 0.26 µs
tSU,DAT SDA set-up time 50 ns
tHD,DAT SDA hold time 8 ns
tSU,STA Repeated START condition set-up time 0.26 µs
tHD,STA (Repeated) START condition hold time 0.26 µs
tSU,STO STOP condition set-up time 0.26 µs
tBUF Bus free time between a STOP and START condition 0.5 µs1For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32ZG Reference Manual.
3.15 Digital Peripherals
Table 3.28. Digital Peripherals
Symbol Parameter Condition Min Typ Max Unit
IUSART USART current USART idle current, clock en-abled
7.5 µA/MHz
II2C I2C current I2C idle current, clock enabled 6.25 µA/MHz
ITIMER TIMER current TIMER_0 idle current, clockenabled
8.75 µA/MHz
IPCNT PCNT current PCNT idle current, clock en-abled
100 nA
IRTC RTC current RTC idle current, clock enabled 100 nA
IAES AES current AES idle current, clock enabled 2.5 µA/MHz
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Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" forguidelines on designing Printed Circuit Boards (PCB's) for the EFM32ZG222.
4.1 Pinout
The EFM32ZG222 pinout is shown in Figure 4.1 (p. 48) and Table 4.1 (p. 48) . Alternate locationsare denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/").Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the modulein question.
Figure 4.1. EFM32ZG222 Pinout (top view, not to scale)
16 RESETnReset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up en-sure that reset is released.
17 PB11 IDAC0_OUT TIM1_CC2 #3
18 VSS Ground
19 AVDD_1 Analog power supply 1.
20 PB13 HFXTAL_P LEU0_TX #1
21 PB14 HFXTAL_N LEU0_RX #1
22 IOVDD_3 Digital IO power supply 3.
23 AVDD_0 Analog power supply 0.
24 PD4 ADC0_CH4 LEU0_TX #0
25 PD5 ADC0_CH5 LEU0_RX #0
26 PD6 ADC0_CH6TIM1_CC0 #4
PCNT0_S0IN #3US1_RX #2/3I2C0_SDA #1
ACMP0_O #2
27 PD7 ADC0_CH7TIM1_CC1 #4
PCNT0_S1IN #3US1_TX #2/3I2C0_SCL #1
CMU_CLK0 #2
28 VDD_DREG Power supply for on-chip voltage regulator.
29 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
30 PC8
31 PC9 GPIO_EM4WU2
32 PC10
33 PC11
34 PC13 TIM1_CC0 #0TIM1_CC2 #4
PCNT0_S0IN #0
35 PC14 TIM1_CC1 #0
PCNT0_S1IN #0US1_CS #3 PRS_CH0 #2
36 PC15 TIM1_CC2 #0 US1_CLK #3 PRS_CH1 #2
37 PF0 TIM0_CC0 #5 US1_CLK #2 DBG_SWCLK #0
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A wide selection of alternate functionality is available for multiplexing to various pins. This is shown inTable 4.2 (p. 50) . The table shows the name of the alternate functionality in the first column, followedby columns showing the possible LOCATION bitfield settings.
NoteSome functionality, such as analog interfaces, do not have alternate settings or a LOCA-TION bitfield. In these cases, the pinout is shown in the column corresponding to LOCA-TION 0.
Table 4.2. Alternate functionality overview
Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.
ACMP0_O PE13 PD6 Analog comparator ACMP0, digital output.
ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4.
ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5.
ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6.
ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7.
BOOT_RX PF1 Bootloader RX
BOOT_TX PF0 Bootloader TX
CMU_CLK0 PA2 PD7 Clock Management Unit, clock output number 0.
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The specific GPIO pins available in EFM32ZG222 is shown in Table 4.3 (p. 52) . Each GPIO port isorganized as 16-bit ports indicated by letters A through F, and the individual pin on this port in indicatedby a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port Pin15
Pin14
Pin13
Pin12
Pin11
Pin10
Pin9
Pin8
Pin7
Pin6
Pin5
Pin4
Pin3
Pin2
Pin1
Pin0
Port A - - - - - PA10 PA9 PA8 - - - - - PA2 PA1 PA0
Port B - PB14 PB13 - PB11 - - PB8 PB7 - - - - - - -
Port C PC15 PC14 PC13 - PC11 PC10 PC9 PC8 - - - PC4 PC3 PC2 PC1 PC0
Port D - - - - - - - - PD7 PD6 PD5 PD4 - - - -
Port E - - PE13 PE12 PE11 PE10 - - - - - - - - - -
Port F - - - - - - - - - - PF5 PF4 PF3 PF2 PF1 PF0
4.4 TQFP48 Package
Figure 4.2. TQFP48
Note:
1. Dimensions and tolerance per ASME Y14.5M-19942. Control dimension: Millimeter.3. Datum plane AB is located at bottom of lead and is coincident with the lead where the lead exists
from the plastic body at the bottom of the parting line.4. Datums T, U and Z to be determined at datum plane AB.
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5. Dimensions S and V to be determined at seating plane AC.6. Dimensions A and B do not include mold protrusion. Allowable protrusion is 0.250 per side. Dimen-
sions A and B do include mold mismatch and are determined at datum AB.7. Dimension D does not include dambar protrusion. Dambar protrusion shall not cause the D dimension
to exceed 0.350.8. Minimum solder plate thickness shall be 0.0076.9. Exact shape of each corner is optional.
Table 4.4. QFP48 (Dimensions in mm)
DIM MIN NOM MAX DIM MIN NOM MAX
A - 7.000 BSC - M - 12DEG REF -
A1 - 3.500 BSC - N 0.090 - 0.160
B - 7.000 BSC - P - 0.250 BSC -
B1 - 3.500 BSC - R 0.150 - 0.250
C 1.000 - 1.200 S - 9.000 BSC -
D 0.170 - 0.270 S1 - 4.500 BSC -
E 0.950 - 1.050 V - 9.000 BSC -
F 0.170 - 0.230 V1 - 4.500 BSC -
G - 0.500 BSC - W - 0.200 BSC -
H 0.050 - 0.150 AA - 1.000 BSC -
J 0.090 - 0.200
K 0.500 - 0.700
L 0DEG - 7DEG
The TQFP48 Package is 7 by 7 mm in size and has a 0.5 mm pin pitch.
The TQFP48 Package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see:http://www.silabs.com/support/quality/pages/default.aspx
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Table 5.3. QFP48 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 1.50
b 0.20
c 0.50
d 8.50
e 8.50
1. The drawings are not to scale.2. All dimensions are in millimeters.3. All drawings are subject to change without notice.4. The PCB Land Pattern drawing is in compliance with IPC-7351B.5. Stencil thickness 0.125 mm.6. For detailed pin-positioning, see Figure 4.2 (p. 52) .
5.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
The packages have a Moisture Sensitivity Level rating of 3, please see the latest IPC/JEDEC J-STD-033standard for MSL description and level 3 bake conditions.
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In the illustration below package fields and position are shown.
Figure 6.1. Example Chip Marking
6.2 Revision
The revision of a chip can be determined from the "Revision" field in Figure 6.1 (p. 57) .
6.3 Errata
Please see the errata document for EFM32ZG222 for description and resolution of device erratas. Thisdocument is available in Simplicity Studio and online at:http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
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Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentationof all peripherals and modules available for system and software implementers using or intending to usethe Silicon Laboratories products. Characterization data, available modules and peripherals, memorysizes and memory addresses refer to each specific device, and "Typical" parameters provided can anddo vary in different applications. Application examples described herein are for illustrative purposes only.Silicon Laboratories reserves the right to make changes without further notice and limitation to productinformation, specifications, and descriptions herein, and does not give warranties as to the accuracyor completeness of the included information. Silicon Laboratories shall have no liability for the conse-quences of use of the information supplied herein. This document does not imply or express copyrightlicenses granted hereunder to design or fabricate any integrated circuits. The products must not beused within any Life Support System without the specific written consent of Silicon Laboratories. A "LifeSupport System" is any product or system intended to support or sustain life and/or health, which, if itfails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratoriesproducts are generally not intended for military applications. Silicon Laboratories products shall under nocircumstances be used in weapons of mass destruction including (but not limited to) nuclear, biologicalor chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®,EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most ener-gy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISO-modem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registeredtrademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or reg-istered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other productsor brand names mentioned herein are trademarks of their respective holders.
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B Contact InformationSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701
Please visit the Silicon Labs Technical Support web page:http://www.silabs.com/support/pages/contacttechnicalsupport.aspxand register to submit a technical support request.
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Table of Contents1. Ordering Information .................................................................................................................................. 22. System Summary ...................................................................................................................................... 3
3. Electrical Characteristics ............................................................................................................................. 83.1. Test Conditions .............................................................................................................................. 83.2. Absolute Maximum Ratings .............................................................................................................. 83.3. General Operating Conditions ........................................................................................................... 83.4. Current Consumption ....................................................................................................................... 93.5. Transition between Energy Modes .................................................................................................... 163.6. Power Management ....................................................................................................................... 163.7. Flash .......................................................................................................................................... 173.8. General Purpose Input Output ......................................................................................................... 183.9. Oscillators .................................................................................................................................... 253.10. Analog Digital Converter (ADC) ...................................................................................................... 283.11. Current Digital Analog Converter (IDAC) .......................................................................................... 383.12. Analog Comparator (ACMP) .......................................................................................................... 433.13. Voltage Comparator (VCMP) ......................................................................................................... 453.14. I2C ........................................................................................................................................... 453.15. Digital Peripherals ....................................................................................................................... 46
A. Disclaimer and Trademarks ....................................................................................................................... 60A.1. Disclaimer ................................................................................................................................... 60A.2. Trademark Information ................................................................................................................... 60
B. Contact Information ................................................................................................................................. 61B.1. ................................................................................................................................................. 61
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List of Figures2.1. Block Diagram ....................................................................................................................................... 32.2. EFM32ZG222 Memory Map with largest RAM and Flash sizes ........................................................................ 73.1. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at24MHz ..................................................................................................................................................... 103.2. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at21MHz ..................................................................................................................................................... 103.3. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at14MHz ..................................................................................................................................................... 113.4. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at11MHz ..................................................................................................................................................... 113.5. .......................................................................................................................................................... 123.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 24MHz ............................... 123.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 21MHz ............................... 133.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 14MHz ............................... 133.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 11MHz ............................... 143.10. ........................................................................................................................................................ 143.11. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO. ....................................................... 153.12. EM3 current consumption. ................................................................................................................... 153.13. EM4 current consumption. ................................................................................................................... 163.14. Typical Low-Level Output Current, 2V Supply Voltage ................................................................................ 193.15. Typical High-Level Output Current, 2V Supply Voltage ................................................................................ 203.16. Typical Low-Level Output Current, 3V Supply Voltage ................................................................................ 213.17. Typical High-Level Output Current, 3V Supply Voltage ................................................................................ 223.18. Typical Low-Level Output Current, 3.8V Supply Voltage .............................................................................. 233.19. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................. 243.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage .............................................................. 263.21. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 273.22. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 283.23. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 283.24. Integral Non-Linearity (INL) ................................................................................................................... 333.25. Differential Non-Linearity (DNL) .............................................................................................................. 333.26. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C ................................................................................. 343.27. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C ................................................................... 353.28. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C ............................................................... 363.29. ADC Absolute Offset, Common Mode = Vdd /2 ........................................................................................ 373.30. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V .............................................. 373.31. ADC Temperature sensor readout ......................................................................................................... 383.32. IDAC Source Current as a function of voltage on IDAC_OUT ....................................................................... 413.33. IDAC Sink Current as a function of voltage from IDAC_OUT ........................................................................ 423.34. IDAC linearity .................................................................................................................................... 423.35. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1 ............................................. 444.1. EFM32ZG222 Pinout (top view, not to scale) .............................................................................................. 484.2. TQFP48 .............................................................................................................................................. 525.1. TQFP48 PCB Land Pattern ..................................................................................................................... 545.2. TQFP48 PCB Solder Mask ..................................................................................................................... 555.3. TQFP48 PCB Stencil Design ................................................................................................................... 566.1. Example Chip Marking ........................................................................................................................... 57
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List of Equations3.1. Total ACMP Active Current ..................................................................................................................... 433.2. VCMP Trigger Level as a Function of Level Setting ..................................................................................... 45