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In sequential circuits the initial state(register’s values) is not by default known.Consequently, the sensitization of faults
InputsOutputsCombinational Combinational
LogicLogic
and the propagation of the correspondingerroneous responses may turn to be a hardtask.A solution is to use techniques for theproper initialization of the circuit state toknown values.
• Application of proper test vectorsequences and/or the use of Set/Reset
Scan Testing 3
RegistersRegisters
““StateState””Clock
sequences and/or the use of Set/Resetsignals to setup the required state.
• Development of efficient techniques toset the initial state and observe thesubsequent state after the response ofthe circuit.
General Scan Testing SchemeGeneral Scan Testing Scheme
Scan‐In
LogicLogicRegistersRegisters
Scan‐Out
Inputs Outputs
ClockScanScan
RegisterRegister
Scan Testing 4
The memory elements (latches or Flip‐Flops) in a design are properly connected to forma unified shift register (scan register or chain). This way the internal state of the circuit isdetermined (controlled) by shifting in (scan‐in) to the scan register the required test datato be applied to the combinational logic. Moreover, the existing internal state (previouslogic response) can be observed by shifting out (scan‐out) the data stored into the scanregister.
Scan‐in of alternating“0” and “1” from the SI input
2
3 Μ+1 clock cycles
Scan Testing 10
Response observationat the SO output
4
Μ = # of scan cells
6
Logic testing5
Scan ApplicationScan Application (Ι(ΙII))
g g
SE = “1”: Test data scan‐infrom the SI inputs
Μ clock cycles (scan‐in cycles)6
7 SE = “0”: Test patternapplication from the PI inputs
Scan Testing 11
Single clock pulse andresponse observation at the POs
single clock cycle (capture cycle)8
SE = “1”: New test data
Scan ApplicationScan Application (Ι(ΙIIII))
scan‐in from the SIsand simultaneous scan‐out of the test responses from the SOs
9
10
Μ clock cycles
Exists anothertest vector;
YES7
Scan Testing 12
11 End
No
7
D Q Out2D QIn2
D Q
CLK
In1D Q
CLKside path
Out11 1
1
Delay Fault TestingDelay Fault Testing
0
1
1 D Q
CLK
CLK
Out2D Q
CLK
In2
CLK
Logic
path under test
A path delay fault requires a pair of subsequent test vectors to be detected. The first test vector initializes the circuit while the second test vector activates the path under test.
V1 = <10>V2 = <11> ← Path ac va on test vector
← Ini alizing test vector
0 1
Scan Testing 13
The first test vector initializes the circuit while the second test vector activates the path under test.
tCLK
InitializingVector
Application
LaunchActivationVector
TestResponseCapture
How scan testing facilities can be exploited for delay fault testing ?
At speed clocking!
At Speed Scan Testing (I)At Speed Scan Testing (I)
. . . . . .
X1
X2
XK
Z1
Z2
ZN
(Skewed(Skewed‐‐load or Launchload or Launch‐‐onon‐‐shift Technique)shift Technique)
CombinationalCombinationalLogicLogic
XK ZN
. . .
CLK
SI0
1
0
1
0
1
0
1
SO
SE
D Q
CLK
D Q
CLK
D Q
CLK1 2 M
MUX
MUX
MUX
MUX
Scan Chain
unch
pture
Scan Testing 14
CLK
tSE
Shift Shift Lau
Cap Shift
Fast Transition
Delay fault oriented scan testing technique
Shift
8
At Speed Scan Testing (II)At Speed Scan Testing (II)
. . . . . .
X1
X2
XK
Z1
Z2
ZN
(Double Capture or Launch(Double Capture or Launch‐‐onon‐‐Capture Technique)Capture Technique)
CombinationalCombinationalLogicLogic
XK ZN
. . .
CLK
SI0
1
0
1
0
1
0
1
SO
SE
D Q
CLK
D Q
CLK
D Q
CLK1 2 M
MUX
MUX
MUX
MUX
Scan Chain
unch
pture
Scan Testing 15
CLK
tSE
Shift Shift
DeadTime
Lau
Cap Shift
Delay fault oriented scan testing technique
Fast Clock Pulses GenerationFast Clock Pulses Generation
D Q
Q1 Q2 Q3 Q4 Q5
SE
Scan_CLK1 2 3 4 5
00
11
0
1
CLK
PLL
PLL_CLK
Shift Register
Scan_CLK
Clock_Gating
Scan Testing 16
_
t
SE
PLL_CLK
CLK
Clock_Gating
9
The ClockedThe Clocked‐‐Scan TechniqueScan Technique
•Excess power consumption (usually outside circuit’sspecifications) during the scan‐in/out operations and thecapture of the test response in the scan chain.
Scan Testing 23
p p
Scan Chain
1 0 0 0 1 00 1 1 0 1 0
Test Vector Response
0
Scan Chain Shift Power Consumption (I)Scan Chain Shift Power Consumption (I)
CaptureCapture
0 1 0 0 0 10 1 1 0 1 0
1 0 1 0 0 00 1 1 0 1 0
0 1 0 1 0 00 1 1 0 1 0
1 0 1 0 1 00 1 0 0 1 0
Cycle 1Cycle 1
Cycle 2Cycle 2
Cycle 3Cycle 3
Cycle 4Cycle 4
Scan Testing 24
1 1 0 1 0 10 0 0 0 1 0
1 0 1 0 1 0
0 1 1 0 1 0 1 0 0 0 1 0
yy
Cycle 5Cycle 5
Cycle 6Cycle 6
13
Scan Chain
0 1 1 0 1 0
Test Vector Response
0
Scan Chain Shift Power Consumption (II)Scan Chain Shift Power Consumption (II)
1 0 0 0 1 0
# Transitions0 1 1 0 1 0
1 0 1 0 0 00 1 1 0 1 0
0 1 0 1 0 00 1 1 0 1 0
1 0 1 0 1 00 1 0 0 1 0
0 1 0 0 0 1 # Transitions = Distance from 1st scan‐out bit
Scan Testing 25
1 1 0 1 0 10 0 0 0 1 0
1 0 1 0 1 0
0 1 1 0 1 0 1 0 0 0 1 0
# Transitions = L – (Distance from 1st scan‐in bit)
L = scan chain length
h
Previous Test VectorPrevious Scan Chain State
New Response
Scan Chain Capture Power ConsumptionScan Chain Capture Power Consumption
0 1 1 1 0 1
1 0 1 0 0 0
Scan ChainPrevious Scan Chain State
Scan Chain
1 0 1 0 0 0 New Scan Chain State
Power consumption during scan testing procedures is a major concern since it can be severaltimes higher than this during the normal mode of operation. This can affect the reliability of
Scan Testing 26
g g p ythe circuit under test (CUT) due to overheat and electromigration phenomena.The excessive switching activity of the CUT during the scan operations may violate the powersupply IR and Ldi/dt drop limitations and increase the probability of noise induced testfailures. In addition, the elevated temperature can degrade the speed performance of theCUT and result to erroneous test responses that will invalidate the testing process and leadto yield loss.
14
XX‐‐bit Assignmentbit Assignment
•A large number of bits in a test cube that is generated byan ATPG tool are don’t care bits (X‐bits).
• In order to apply a test cube for circuit testing, specificvalues must be assigned to the X‐bits (test vectorformation). This task is called X‐filling.
•The X‐filling process can be oriented for shift and/orcapture power reduction.
Scan Testing 27
Low Power ScanLow Power Scan
0
from logic to logic
Scan FFDI
Original Topology
CLK
SI1
SE
D Q
CLK
MUX
to scan FFfrom scan FF
Use of Data Gating (φραγμός δεδομένων)t h i t th t t f th ll i
Original Topology
SE
from logic
to logic
Scan FF
DI
Scan Testing 28
techniques at the output of the scan cells inorder to eliminate the signal transitions atthe inputs of the combinational logic duringthe scan‐in/out operations.Dynamic power reduction.
Reordering of Scan Chain FlipReordering of Scan Chain Flip‐‐FlopsFlops (Ι)(Ι)
44FFFF8FF8FF
Typical Scan Chain
50Test
Vectors
300Test
Vectors
2FF
2FF
50 TV 300TV
ΙΝ
Scan Testing 40
SO2FF2FF44FFFF
Test Application: 300(20+1)+20 = 6320 clock cycles“Random” register
connection
1st Alternative Test Application: 300(14+1)+8 = 4508 clock cyclesImprovement
29% !
21
SI 44FFFF8FF8FF
2nd Alternative Scan Testing Application
Reordering of Scan Chain FlipReordering of Scan Chain Flip‐‐FlopsFlops ((IIII))
50Test
Vectors
300Test
Vectors
2FF
2FF ΙΝ
Scan Testing 41
SO
Test Application:
2FF2FF44FFFF
50(14+1) = 750 clock cycles
250(12+1)+8 = 3258 clock cycles
4008 clock cycles
Improvement37% !
SI44FFFF8FF8FF
3rd Alternative Scan Testing Application with cell reordering
Reordering of Scan Chain FlipReordering of Scan Chain Flip‐‐FlopsFlops ((IIIIII))
50ΔιανύσματαΕλέγχου
300ΔιανύσματαΕλέγχου
2FF
2FF ΙΝ
Scan Testing 42
SO
Test Application: 50(18+1) = 950 clock cycles
250(4+1)+4 = 1254 clock cycles
2204 clock cycles
2FF2FF44FFFF
Improvement65% !
In addition, test powerreduction is achieved!
22
ReferencesReferences
• “Principles of Testing Electronics Systems,” S. Mourad and Y. Zorian, John Wiley& Sons, 2000.
• “Essentials of Electronic Testing: for Digital Memory and Mixed‐Signal VLSI• Essentials of Electronic Testing: for Digital, Memory and Mixed‐Signal VLSICircuits,” M. Bushnell and V. Agrawal, Kluwer Academic Publishers, 2000.
• “Power‐Constrained Testing of VLSI Circuits,” N. Nicolici and B. Al‐Hashimi,Kluwer Academic Publishers, 2003.
• “Digital Systems Testing and Testable Design,” M. Abramovici, M. Breuer and A.Friedman, Computer Science Press, 1990.
• “System‐on‐Chip Test Architectures,” L‐T Wang, C. Stroud and N. Touba,Morgan‐Kaufmann, 2008.
Scan Testing 43
• “VLSI Test Principles and Architectures,” L‐T Wang, C‐W. Wu and X. Wen,Morgan‐Kaufmann, 2006.