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A .
.
.F D.C
.
F:A S
A
.
A .
S : ,
.E ,
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.A
.
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A .
1 0, HIGH LO, RE FALSE.D
, ,
0 1. .
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,
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:
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:
D ,
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D .I
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.,
.
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.
:
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,
.
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.
.
D ,
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. D
, . I
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"",
.
A
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:
1.D D 3 E M.M.M,2002.
2.F C.H.R, J P,1998.
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A D D
D S A
C C
A C A
I , 10 (09) .
H
0 1.B 10
. 0 1 .
.
A
. .
.
10 : 0,1,2,3,4,5,6,7,8,9. I
10.
2734
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21000 + 7100 + 310 + 41
= 2000+700+30+4
4 LSD 2 MSD
I , 0 1
N=+
+++
=0,1,2,3,
=
= . 0 1
. F
N=+
++ +
0.7123
N = 0.7000 + 0.0100 + 0.0020 + 0.0003
= 7
= 1
= 2
= 3
2. A = 2, . 0
1.F , 10 10 .
E: 101010
N = (101010)
= 12+02+12+02+12+02
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= 43
F N , .
2 > N
F I N=26, 5 2=16 2=32
O :
O 8. 0 0 7(1)
E: 15.2
N = (15.2)
= 18 + 58 + 28
= 13.25
16. 16 .
0 9 ,
A,B,C,D,E,F 10,11,12,13,14 15 .
B , ,
.
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
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R .I
,
, .
.
.
R LSD MSD
R MSD LSD.
E: C 23 ( 2 )
0.
2 23
2 11 1 LSD
2 5 1
2 2 1
2 1 0
0 1 MSD
23= (10111)
E: C (0.7854)
0.78542=1.5708 ; = 1
0.57082=1.1416; =1
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0.14162=0.2832; =0
0.28322=0.5664; =0
F ,
1. G . 3 . I . 3, .
2. 1 E: 100 010 011
4 2 3
F ,
1. G . 4 .I , 4, 0 .
2. 1 .E: 1001 1110 0111 0000 ()
9 E 7 0 ()
C .
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D ,
.
. .
5 FF 0.
0 0
N 51
I 5 3.1 1 .
:
POSIIE LOGIC;
0 1
.
00 5
L 1 5 0
1 0 .
. 5 1>0 0
0 1
.
0 5
L 1 0
1 0 .
. 0 1 < 5 0
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O . N
.
. .
.
.
.
.
. , 0 5.
.
, , , , , , , .
. .
B: AD
F=A*B F A B.
:
1 E 0 FAE
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0 0 0
0 1 0
1 0 0
1 1 1
.
B:
F=A+B
A+B A B
A B F
0 0 0
0 1 1
1 0 1
1 1 1
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:
. ,
,
:
.
. , ( )
1 0
0 1
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. ., A B (A B)
B;
ABE;
0 0 1
0 1 1
1 0 1
1 1 0
0 0 1
1 0 0
0 1 0
1 1 0
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0 0 1
0 1 0
1 0 0
1 1 1
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,
. , , , ,
.
.
0
1
1
0
.
0 0 1
1 0 1
0 1 1
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1 1 0
2 3 . .
.
.
.
0 0 0
0 1 0
1 0 0
1 1 1
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.
.
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.
.
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0 0 1
1 0 0
0 1 0
1 1 0
2 3
0 1
1
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.
.
.
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.
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MODULE -5
BOOLEAN ALGEBRA
1. Boolean algebra works with binary variables.
2. A Boolean algebra is an algebraic system consisting of the set {0,1} the binary operations called
OR,AND,NOT and denoted by the symbols "+","." and "prime" respectively.
3. Boolean algebra enables the logic designer to simplify the circuit used achieving economy of
construction and reliability of operation.
4. Boolean algebra suggests the economic and straight forward way of describing the circuitary used in
any computer system.
5. Boolean algebra is unique in the way that , it takes only two different values either 0 or 1
a. it doesn't have negative number.
b. it doesn't have fraction number.
6. the basic boolean postulates
a. logical multiplication based on AND function.
* 0 . 0 =0 * 0 . 1 = 0 * 1 . 0 = 0 * 1 . 1 = 1
b. logical additions based on OR function.
* 0 + 0 = 0 * 0 + 1 = 1 * 1 + 0 = 1 * 1 + 1 = 1
c. complement based on NOT function.
* 0 = 1 * 1 = 0.
7. boolean properties.
a. properties of AND function
1. x . 0 = 0 2. 0 . x = 0 3. x . 1 = x 4. 1 . x = x.
b. properties of OR function.
5. x+ 0 =x 6. 0 + x = x 7. x + 1 = 1 8. 1 + x = 1 9. 0 + =
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c. combining a variable with itself OR its compliment.
10 . x . x = o 11. x . x = x 12. x + x = x 13. X + x = 1 14. X = x
d. commutative laws.
15. x . y = y . x 16. x + y = y + x
e. distributive laws.
17. x(y+z) = x.y + x.z 18. X + y.z = (x+y) (x+z)
f. associative laws.
19. x(y.z) = (x.y)z 20. X+(y+z)= (x+y)+z
g. absorption laws
21. x+xy=x 22. x(x+y) =x 23. x+ x y = x+y 24. x(x+ y)= xy
h. demorgans laws.
25.(x+y) = x . y 26. (x.y) = x + y
8. In boolean algebra 1 is called multiplicative identity and 0 is called additive identity.
* LITERAL : A primed or unprimed boolean variable is called literal. Each variable can havemaximum of two literals.
Eg: X Is a variable which can have two literals x and x .
Proof for some properties ;
17. X + YZ = (X+Y) (X+Z)
R.H.S = X.X+X.Z+X.Y+Y.Z
=X + XZ +XY +YZ
=X(1+Z)+XY+YZ
=X+XY+YZ [ 1+ Z = 1 ]
= X (1+Y)+(Y+Z) [1+Y= 1]
= X + YZ = L.H.S
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22. X+ XY = X+ Y
L.H.S = X + XY
=(X + X)(X+Y)
=X+Y = R.H.S
23. X(X + Y) = XY
LHS = XX + XY = 0 + XY = XY =RHS
9. logics circuits can be simplified by simplifying the boolean equation using any one of the following
methods :
a) applying boolean properties.
b) karnaugh map method of simplification
c) tabulation method
10. The properties of boolean algebra are useful for the simplification of boolean equation leading to
minimum structure.
11. simplify the boolean equation Z = XY + X (X+Y)
XY + X (X+Y) = XY + XX + XY
= XY + XY
= (X+ X) Y = Y
DUALITY PRINCIPLE : The important property of boolean algebra is the duality principle.
It states that every algebraic expression deducible from theorems of boolean algebra remains valid if the
operators and identify elements are interchanged.
EXAMPLES:-
X + X = X X.X= X BY duality
X + 1 = 1 x.0= 0 by duality
X + x y= x x(x +y)=x by duality
X + y= y + x xy=yx by duality
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X +(Y + Z)=(X+Y)+Z X (YZ)= (XY) Z
By duality
The dual of the exclusive OR is equal to its complement A simple procedure to find the complement of a function is to take the dual of the function and
complement of each literal.
12. Standard product or minterm (M): consider two binary variables x and y combined with
an AND operation. Since each variable appears in direct form or in its complement form there are
four possible combinations X Y, X Y, X Y and XY. Each of these four AND terms is called a
minterm or a standard product.
X Y MINTERM m
0 0 XY m0
0 1 XY m1
1 0 XY
m2
1 1 XY m3
Standard sum or Maxterm (M): Two binary variables X and Y combined with an OR operation we will
an OR operation we will get four possible combinations X+Y, X+, +Y and +. Each of these four
OR terms is called a Maxterm or a standard sum term.
X Y Maxterm (M)
0 0 M0X+Y
0 1 M1X+
1 0 M2+Y
1 1 M3+
Each Maxterm is the compliment of its corresponding minters and vice versa.
Eg: - XY = Minterm
The compliment of minterm = (XY) = + = Maxterm
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13. CANONICAL FORM: Expressing the Boolean function in standard sum of product form (SSPO)
or standard product of sums form (SPOS) is called canonical form.
1. A Boolean function may be expressed algebraically from given truth table by forming a minterm for
each combination of variables which produces 1 in the function, and then taking the OR of all thoseterms.
X Y F
0 0 0
0 1 1
1 O 1
1 1 1
F(X, Y) = X + Y = m (1, 2)
This representation is called SSOP form. minterm or product of maxterm are said to be canonical form.
3. Sum of products form can be implemented by using NAND NAND realization.
4. NAND-NAND realization is same as AND OR.
5. Product of sums form can be implemented by using NOR- NOR realization.
6. NOR NOR realization is same as OR - AND.
7. If the signals are propagating through two stages of gates, then it is called two level gate network.
DEGENERATIVE FORM: A two level gate network is said to be degenerative if it degenerates
to a single operation. The following two level gate networks are degenerative.
Forms:
AND-AND AND
OR-OR OR
OR -NOR NOR
NOR -NAND OR
NAND -NOR AND
AND -NAND NAND
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Realizing the minimal sum of products form of a function form truth table using Boolean
algebra
We are not sure that the given function or logical circuit is in its simplest form. It is possible to
design a circuit having less number of gates and inputs to realize the same function , then it saves
hard ware. Reduction at gate level is important.
*Characteristic table of given function;
IN PUTS
A B C
OUTPUT
F(A,B,C)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
0
1
0
1
1
1
1
*Here three input variables (A,B,C) are present. The possible minterms are 8.
They are:-
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)111(),110(,)101(,)100(
,)011(),010(),001(),000(
7654
3210
ABCmCABmCBAmCBAm
BCAmCBAmCBAmCBAm
====
====
Each row in the truth table is a minterm . Output is true i.e 1 for 5 minterms. Output is false i.e 0
for 3 minterms. Function is expressed as a sum of minterms for which output is true i.e1
=
++++=
)7,6,5,4,2(
),,(
m
ABCCABCBACBACBACBAF(SOP)
NOTE; Reduction means reducing the number of terms and number of variables in each term. Our
goal is to make it as minimum sum of products beyond which we can not reduce further
ACB
ACB
ACBAA
ACBA
ACBA
BBACBA
ABBACBA
CCABBACBA
CCABCCBACBACBAF
+=
+=
++=
+=
+=
++=
++=
+++=
++++=
))(1(
))((
)1(
)(
)()1(
)()(),,(
Alternative:-
+=
+=
++=
++=
++++=
CBA
ACB
ACBAA
ACABCBA
ABCCABCBACBACBACBAF
)(
),,(
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This is the minimal sum of products form.
By using De Morgans Theorem ; we can use the minterms for which the output is false i.e 0. To
realise the function instead of using minterms for which the output is true i.e 1. Complement of the
function (
F) is the sum of minterms for which the output is false i.e 0.
From this we can realize that the given function is the product of max terms for which output is false i.e
0. For max terms 0-variable ; 1- complement of variable.
3
1
0
)011(
)001(
)000(
MCBA
MCBA
MCBA
++
++
++
M B KARNAGH ( K):
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F : A C BC
. = C + BC
=C(+B)
=C H B
S .
D 11 01 .
C F= A+B
C 1, .
(I) I 2 6B+ AB= B(+A) =B A
A .
A B C F
F 0 0 0
S 0 0 1
0 1 0
F 0 1 1
F 1 0 0
S 1 0 1
S 1 1 0
E 1 1 1
0
0
1
0
1
1
1
1
1
1 1 1 1
BCA
00 01 11 10
0
1
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II 4,5,7 6 . A B C
.
II = A
N F (I) + (II)
, F = A+B
B K .
F :E: B
F (P,Q,,) = (0,2,3,7,11,13,14,15)
0,2,3,7,11,13,14,15
.. 1 . , 1 .
PQ 00 01 11 10
00
01
11
10
NOE: 8
00, 01, 11, 10
1) , .2) A
.
3) 1 .4) E (1) .
I . H PQ . 3,
7, 15, 11. PQ .
I=
II 13, 15. I PQ .
II= PQ
III 14,15. H . III= PQ
1 1 1
1
1 1 1
1
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I 0,2. H 0 2 I=
2 0.
F
F= (I) + (II) +(III) +(I)
F= + PQ + PQ +
E (I, II, III, I) .
A .
E: 1) 0,2 2) 3,2 3) 3,7 4) 7,5 5) 13,15 6) 14, 15
7) 11, 15 8) 3,7,15,11
. I .
E: 0,2, 3,7,5,11, 13,15, 14,15
A 1
.
E: 0,2, 3,7,5,11, 13,15, 14,15
1
.
2 .. 1
A
E: F= (12,15,13,7,15,6,11)
F K K
.
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VARIABLE MAPS
INTRODUCTION:
In the last lecture we introduce the map method of boolean simplification. we
use a karnaugh map which is a graphical representation of a truth table, filled this graph
with 1's corresponding to the cells whose minterms had a output true. The object is to
identify groups of 1's as large as possible with satisfying the adjacency rule.
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FOUR VARIABLE K-MAP:
Four variable k-map consists of 24=16 squares or 16 cells. The rows and columns
are numbered in a gray code sequence, with only one digit changing value between two
adjacent rows or columns.
RULES TO SIMPLIFY K-MAPS:
1. At thetime of grouping the adjacent cells containing 1's always use maximum
possible group.
2. All the 1's must be covered atleast once in any group.
3. At the time of grouping don't care(x) values can be taken as 1's.
4. All don't care values need not be covered.
fig: Four variable map
The combination of adjacent squares that is useful during the simplification
process is easily determined from the inspection of four variable map.
One square represents one minterm, giving a term of four literals. Grouping two adjacent squares containing 1's represents a term of three literals. Grouping four adjacent squares containing 1's represents a term of two literals. Grouping eight adjacent squares containing 1's represents a term of one literal.
m0 m1 m3 m2
m4 m5 m7 m6
m12 m13 m15 m14
m8 m9 m11 m10
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Grouping sixteen adjacent squares containing 1's represents the function=1(a termof zero literals).
No other combination of squares can simplify the function.
PRIME IMPLICANTS:
In choosing adjacent squares in a map, we must ensure that
1. All the minterms of the function are covered when we combine the squares.
2. The number of terms in the expression is minimized, and
3. There are no reduntant terms. some times there may be two or more expressions that
satisfy the simplification criteria.
Any group of 1's is an implicant. A prime implicant is a product term obtained by
combining the maximum possible number of adjacent squares in the map. If a minterm in
a square is covered by only one prime implicant, that prime implicant is said to be
essential.
FIVE VARIABLE MAP:
A five variable map needs 32 squares and a six variable map needs 64
squares. The five variable map shown in below fig. It consists of 2 four variable maps
with variables A,B,C,D and E. Variable A distinguishes between the two maps, as
indicated at the top of the diagram. The left hand four variable map represents 16 squares
in which A=0, and the other four variable map represents the squares in which A=1.
Minterms 0 through 15 belong with A=0 and minterms 16 through 31 with A=1. Each
four variable map retains the previously defined adjacency when taken separately. In
addition each square in the A=0 map is adjacent to the corresponding square in the A=1map. For example, minterm 12 is adjacent to minterm 10to21.The best way to visualize
this new rule for adjacent squares is to consider the two half maps as being one on top of
the other. Any two squares that fall one over the other are considered adjacent.
SIX VARIABLE MAP:
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By following the procedure used for the five variable map ,it is possible to
construct a six variable map with 4 four variable maps to obtain the required 64 squares.
Maps with six or more variables need too many squares and are impractical to use. the
alternative is to employ computer functions with large number of variables.
Module-8
CODE CONVERTERS
INTRODUCTION:
We have seen the techniques for reduction of boolean functions by using
boolean algebra as well as kmaps. The object is to design circuits as per the given
specifications by using these techniques.
There are two types of the digital circuits i.e., combinational and sequential
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circuits. Combinational circuits are the circuits whose output is based on the inputs and
the sequential circuits are the circuits whose output is depends on the input and as well as
the previous behaviour of the circuit.
DESIGN OF COMBINATIONAL CIRCUITS:
Code converters are one class of circuits in combinational logic. Code
converters, more specifically encoders and decoders, have been used by security agencies
to protect private information. Indeed code converters have proven to be so effective that
the National Security Agency (NSA) has made a career out of creating and breaking
codes.
Example:
When we speak into cellular phone, an encoder converts the sound of our voice
into electrical signals. which can travel very fast over very long distances. When the
electrical signal get to another cellular phone, a decoder converts the electrical signal
back to the sound of our voice.
So code converters are used for more than protecting private information from
spies.
The class of codes which are used for simplification of hardware one is calledexcess-3 code and other is called gray code.
DECIMAL TO EXCESS-3 CODE CONVERTER:
Excess-3 code is used to convert a set of numbers to another set of numbers. By this
code arithmetic complementing operation is easier. This is the reason why we go for
excess-3 code. The excess-3 system simply adds 3 to each number to make the codes
look different. The excess-3 BCD system has some properties that made it useful in early
computers.
BCD EXCESS-3
b3 b2 b1 b0 E3 E2 E1 E0
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: BCD 3
N E,E,E,E
E,E,E,E in terms of b0,b1,b2,b3.
E0,E1,E2,E3 = f(b0,b1,b2,b3)
BINARY TO GRAY CODE CONVERTER:
The gray code is often used in digital systems that because it has the advantage
that only one bit in the numerical representation changes between successive numbers.
Binary Code Gray Code
Decimal
number
D C B A G3 G2 G1 G0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 00 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
. . . .
. . . .
. . . .
. . . .
1 1 1 1
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 11 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
X X X X
. . . .
. . . .
. . . .
. . . .
X X X X
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0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 114 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
Table: Truth table for binary to gray code conversion
GRAY CODE:The gray code belongs to a class of codes called minimum change codes, in
which only one bit in the code changes when moving from one code to the next. The gray
code is non weighted code, as the position of bit does not contain any weight. The gray
code is a reflective digital code which has the special property that any two subsequent
numbers codes differ only by one bit. This is also called a unit distance code. In digital
gray code it has got a special place.
CONVERSION FROM BINARY NUMBER TO GRAY NUMBER:
It is easy to convert the binary number to gray number. For example take a binary
number i.e., 101101
Step 1: 101101 first write the MSB as it is i.e., 1
Step 2: add and bit next to the MSB i.e., 1+0=1
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. A
.
I 1
1
. A .
I
,
. .
S
1
1, .
PEC(
E ) 1 ,
.
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3
I
A B C P
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
F
P (A,B,C)= (0,3,5,6)
F .
P= ABC+ABC+ABC+ABC
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= A (BC+BC) + A (BC+BC)
P
= AP+AP
= PA
= CBA
C D:
4B :
B3 2 1 0
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 11 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
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4 G:
BCD 7 :
E .I
.A LED
. 7 7 .
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INPS OPS
A B C D B D G
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 0 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 0 1 1 1 0 0 1 1
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+++= DCCBCBAg
.S
.M
.
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:
1.
2.
1. :
.
.
() ()
+
0 1 1 0
1 0 1 0
1 1 0 1
.
.
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:
:
B
1 . . .
.
.
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3
, 1
1 (1)
. .
CiB
0++
+(+)
.
0+( BA )
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. .
.
:
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.
:
0
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
1
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.
.
4 :
0
.
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. . 16 32 4 8
.
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P .I
.
.
,
.
A
.
, .
H
. F ,
A = A A A A
B = B B B B
C
F
A B C C
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0 A B = 1 C = 1
1 0 1 1
B A & B 1 , AB = 1
H 1 A & B 1 1. I
A 1 1.
1 1 0 1
1 1 1 1
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C = AB + (A B) C = G + PC
C C
I A B 1 . ,
.
I A B I 1 =1
. , .
L 4
B A B A B A B A
C C C
C
C = G + P C
C = G+ PC
C G+ PC = G + PG + PPCC G+ PC = G+ P(G+PG+PPC)
C G+ PC = G+ PG+P P (G+ PG+ P P C)
N P G C C .
4 .
C C C
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, . I
.
F : . .
F : .
.
CA
.
1) CA 2) . CA , CA
.
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COMPLEMENS :
. .
(1) .
F 2 2
10 9 .
(1)
RADI COMPLEMEN :
, 0 0 =0
.
EG: 10 (1725) 10 1725 = (8275)
2 (101) 2
101 = 1000101 = (011)
DIMINISHED RAID COMPLEMEN :
G N , (1) N (1)N.
E: 729 10 (101)
9 = (101)729=999729=270
F 1101 2 (21)
1 = (21) 1101 = (100001)1101 =11111101 = (0010)
(1) 1 .
SBSRACION SING COMPLEMENS :
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,
.
, . 2 .
1) > 2) MN = 1001 10000 = 00011 3
END AROND CARR (EAC):
EG : M = 0101, N = 0010
1 N =1101
M + 1 N 0101 + 1101 = *0010 + 1 = 0011
H 1 N M. N M
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M 2 N. 1 2
. A .
1 , . 0,
.
CAE 2 :
H M
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2'S COMPLEMENT SUBTRACTOR AND BCD ADDER
1'S COMPLEMENT: The invertor of the given number.
Ex: Q: 101001
Ans : 0101102'S COMPLEMENT: 1's complement of given number plus one.
Ex: Q: 1001
1's complement of number - 0110
Adding one to the number - 1
2's complement of number - 0111
Let A, B are two binary numbers
If both are positive then add those numbers
If A or B or both are negative, then to add these numbers we have to use 2's complement method.
Ex: (1) A 0101
B 1001
A+B 1110
(2 A 0101 1's complement of B 0110B 1001 2's complement of B 0111 (-B)
A-B 1100 A 0101(-B) 0111
A+ (-B) 1100 -4Since 1 100 indicates - 4
If MSB is 1 then the number is negative.
If MSB is 0 then the number is addition of complement numbers.
In case of binary numbers, it is 2's complement.
4 - BIT REPRESENTATION OF NUMBERS:
Here Most Significant Bit is singed bit and remaining three are magnitude bits. If MSB is Zero then number is greater than or equal to zero (>=) that is positive. If MSB is one then number is less than Zero (
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The minimum "+ve" number is 0 "0000"
Similarly, The maximum "-ve" number is -1 "1111"
The minimum "-ve" number is -8 "1000"
Therefore, The positive numbers are from 0 to7.
The negative numbers are from 0 to 8.
Truth table for 4-bit representation of numbers
Signed numbers 4 bit binary number
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 01107 0111
-8 1000
-7 1001
-6 1010
-5 1011
-4 1100
-3 1101
-2 1110
-1 1111
Ex: (1) + 5 : 0 1 0 1
(2) + 7 : 0 1 1 1
(3) - 5 : 1 0 1 1
1 0 0 ( 1's complement of magnitude bits )
+ 1 (adding one to get 2's complement)
1 1 0 1 (-5)
(4) - 8 : 1 0 0 0
1 1 1 (1's complement of magnitude bits )
+ 1 (adding one to get 2's complement)
1 0 0 0 (-8)
GENERAL 4-BIT ADDER/ SUBTRACTOR (A+B) OR (A-B)
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If we want to add A,B then it takes ADD = 0 and Cin =0next 0 B = B then B Cin(0) = B. Therefore, the adder directly adds the A,B.
If we want subtraction of A, B then it takes SUB = 1 and Cin=1. When SUB = 1, then SUB B= B *(complement of B) and Cin=1. So, when we add 1 to B
'we get 2' s complement of B, that is
"B", then the adder will adds the A and -B, so we get A-B.
The circuit will gives adder as well as subtraction. Since it is a 4- bit adder , it adds upto 15 only. If sum is greater than fifteen then it will not give and
appropriate answer.
Up to "BOX1" it gives only magnitude that is unsigned bit (i.e. it gives sum upto15). If we consider the whole circuit then it gives the signed output. If output is signed bit then it gives sum upto +7 only. If sum is greater than '7' then it won't give exact answer.
BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with a possible carry from aprevious stage. Since each input digit does not exceed '9', the output sum cannot be greater than 9 +
9 + 1 = 19, where '1' is the input carry.
That is, if we apply to BCD digits to a four bit binary adder, the adder will from the sum in binaryand produce a result that may range from 0 to 19.
TRUTH TABLE FOR DERIVATION OF A BCD ADDER
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Decimal Binary sum BCD sum
Number C* S3* S2
* S1* S0
* C* S3* S2
* S1* S0
*
0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 1 0 0 0 0 1
2 0 0 0 1 0 0 0 0 1 0
3 0 0 0 1 1 0 0 0 1 1
4 0 0 1 0 0 0 0 1 0 0
5 0 0 1 0 1 0 0 1 0 1
6 0 0 1 1 0 0 0 1 1 0
7 0 0 1 1 1 0 0 1 1 1
8 0 1 0 0 0 0 1 0 0 0
9 0 1 0 0 1 0 1 0 0 1
10 0 1 0 1 0 1 0 0 0 0
11 0 1 0 1 1 1 0 0 0 1
12 0 1 1 0 0 1 0 0 1 0
13 0 1 1 0 1 1 0 0 1 1
14 0 1 1 1 0 1 0 1 0 0
15 0 1 1 1 1 1 0 1 0 1
16 1 0 0 0 0 1 0 1 1 0
17 1 0 0 0 1 1 0 1 1 1
18 1 0 0 1 0 1 1 0 0 0
19 1 0 0 1 1 1 1 0 0 1
Above table represents conversion binary sum to BCD sum.
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In this conversion, upto '9' the BCD number is same as the binary number. When the sum is greater than '9', we obtain non - valid BCD representation. so, the addition of binary
6 (0110) to the binary sum, converts it to the correct BCD representation and also produces an out
put carry as required.
The logic circuit that detects the necessary correction can be derived from the table entires.The correction is needed when C* = 1 (or)
S*3 S*2=1 (or)
S*3S*1= 1
Therefore, the Boolean function C = C*+ S*3 S*2 + S
*3S
*1
When C = 1, it is necessary to add 0110 to the binary sum and provide an output carry for the nextstage.
DESCRIPTION ABOUT BCD ADDER
BCDadder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD. BCD adder must include the correction logic in its internal construction. To add 0110 to the binary sum, we use a second 4 - bit adder. The two decimal digits, together with the input carry are first added in the top 4 - bit binary adder to
produce the binary sum.
When the output carry is equal to zero, nothing is added to the binary sum. When it is equal to one,binary 0110 is added binary sum through the bottom 4 - bit binary adder.
The output carry generated from the bottom binary adder can be ignored, since it suppliesinformation already available at the output carry terminal.
The BCD adder can be constructed with three IC packages. Each of the 4- bit adder is an MSIfunction and the three gates for the correction, logic need one SSI package. However, the BCD adder
is available in one MSI circuit. To achieve shorter propagation delays, an MSI BCD adder includes
the necessary circuits for look - ahead carries.
The adder circuit for the correction does not need all four full - adders, and this circuit can beoptimized within IC packages.
THE CIRCUIT DIAGRAM OF BCD ADDER
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NOTE :
A decimal parallel adder that adds 'n' decimal digits need ' n' BCD adder stages.
SUMMARY :
Explanation about two's complement with examples. A 4 -bit representation of numbers. Design of 4 - bit adder / subtraction. Design of BCD adder.
MODULE 14
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ARRAY MULTIPLIERARRAY MULTIPLIER:
It is a digital combinational circuit. It is used for the multiplication of two binary numbers by employing an array of
full adders and half adders.
This array is used for the nearly simultaneous addition of the various productterms involved. To form the various product terms, an array of ' AND' gates is used
before the adder array.
The main advantage of array multiplier over traditional bit serial multipliers is, itimproves the speed.
BASIC THINGS TO SPEED UP ARE :
Repeated addition - it is inefficient. Shift and add with a set of adders - we repeatedly do it. Shift and add several times - working all with same times.
DEFINITION OF ARRAY MULTIPLIER :
The circuit within do the "shift and add" all at ones is called as an array
multiplier.
It also called parallel multiplier. It takes array of adders.
EXAMPLES
(1) 2 - Bit array multiplier :
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a1 a0 ------- multiplicand
b1 b0 ------- multiplier
a1b0 a0b0
a1b1 a0b1
p3 p2 p1 p0 ------- product
p0= a0 b0
p1 = a1 b0 + a0 b1
p2 = a1 b1 + c1, where c1 = carry generator during the addition for p1 term.
p3 = c2 , where c2 = carry generator during the addition of p2 term.
LOGICAL DIAGRAM :
HA = half adder
pi = product terms ( i = 0,1,2,3 )
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c = carry
s = sum
Ts= sum bit propagation time
Tc= carry bit propagation time
(2) 3 * 3 array multiplier
a2 a1 a0 ------- multiplicand
b2 b1 b0 ------- multiplier
a2b0 a1b0 a0b0
a2 b1 a1b1 a0b1
a2b2 a1b2 a0b2
p5 p4 p3 p2 p1 p0 product terms
p0= a0 b0
p1 = a1 b0 + a0 b1
p2 = a2b0+ a1 b1 + a0b2 + c1
p3 = a2 b1 + a1b2 + c2
p4= a2b2+ c3
p5 = c4
where c1, c2, c3, c4 are carry generators during the addition for p1, p2, p3, p4respectively.
LOGIC DIAGRAM :
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Where
HA = half adder
FA = full adder
pi = product terms ( i = 0,1,2,3,4,5 )
c = carry
s = sum
Ts= sum bit propagation time
Tc= carry bit propagation time
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(3) 4 * 4 array multiplier
a3 a2 a1 a0
b3 b2 b1 b0
a3b0 a2b0 a1b0 a0b0
a3b1 a2 b1 a1b1 a0b1
a3b2 a2b2 a1b2 a0 b2
a3b3 a2b3 a0b3 a0b3
p7 p6 p5 p4 p3 p2 p1 p0
Logic Diagram
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For 2 * 2 multiplier (see ex :1)
Number of AND gates required are 2*2 = 4
Total number of adders required are (2-1) * 2 = 1 * 2 = 2
Numbers of 'HA' required are '2'
Numbers of 'FA' required are ' ( 2 - 2 ) * 2 ' = 0 * 2 = 2
Number of product terms = number of bits in multiplier * bitwidth of each partialproduct
= 2 * 2= 4
For 3 * 3 multiplier ( see ex 2)
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Number of AND gates required are 3*3 = 9
Total number of adders required are (3-1) * 3 = 2 * 3 = 6
Numbers of 'HA' required are ' 3 '
Numbers of 'FA' required are ' ( 3 - 2 ) * 3 ' = 1 * 3 = 3
Number of product terms = number of bits in multiplier * bit
width of each partial product
= 3 * 2
= 6
Similarly for m * n multiplier :
Number of AND gates = m * n
Total number of adders = ( m - 1 ) * n
Numbers of 'HA' = n
Numbers of 'FA' = ( m - 2 ) * n
Number of product terms = number of bits in multiplier * bit
width of each partial product
Even through it improves the speed, still there is a level of delay invovled in an
array multiplier before the final product is achieved. That is
For an " m * n" bit multiplier
Let Ta= AND gate propagation delay
Ts= sum bit propagation delay
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Tc= carry bit propagation delay
Final product delay is
T ={Ta+ [ (m-1) + (n -1) ] Tc, if Tc > Ts
Ta+ ( m-1) Tc + ( n - 1 ) Ts, if Tc Ts
Ta+ 3 Tc + 3 Ts, if Tc < Ts }
CONCLUSION:
Array multiplier is an electronic circuit used in digital electronics to
multiply two binary numbers.
ADVANTAGE :
It improves the speed.
DISADVANTAGE :
Even though it improves the speed it has some propagation delay.
SUMMARY:
Array multiplier definition Advantages and disadvantages of array multiplier. Examples of Array Multiplier. Knowledge about m * n array multiplier.
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,
. A ,
, .
I
. .
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.
.
. ,
. B
,
.
A
. S
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. .
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() .
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SR NOR NAND
. I S R . I
1 0. .
Q=1 Q=0, . Q=0 Q=1,
. Q Q
. H 1 ,
0 .
S=0 R=0 Q Q.
.
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S=1 R=0 Q=1 Q=0 SE .
S=0 R=1 Q=0 Q=1 RESE .
S=1 R=1 0. . B Q Q
.
HE NAND GAE ERSION OF SR LACH
A (
) .
.
. A RS
() .
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=1
I S=1 R=0 Q=1 Q=0 .
I S=0 R=1 Q=0 Q
=1 .
=0, .
D
G :
1. SE 2. RESE 3. MEMOR 4. OGGLE
A JK. B JK,
SR.
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. H S, R
1 , Q ,Q, Q ,Q, Q ,Q............
I (S=R=1) ,
.
C Q Q Q
Q
R.
R