Schottky-Barrier Engineering for Low-Resistance Contactscden.ucsd.edu/internal/Publications/Seminar/Device_100305.pdf · 10/03/05 29 FLCC φB Reduction by Dopant Segregation • φB

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Schottky-Barrier Engineering for Low-Resistance Contacts

Pankaj Kalra, Hideki Takeuchi, Tsu-Jae KingDepartment of Electrical Engineering and Computer Sciences

University of California, Berkeley, CA

Oct 03, 2005

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Outline

• Introduction

• Characterization Schemes

• Si1-xGex Source/Drain

• Dopant Segregation

• Strain

• Summary

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Parasitic Resistance Components• Rsl Silicide sheet resistance

• Rcsd Contact Resistance

• Rsd Silicon Sheet Resistance

• Rov Overlap resistance

Gate

RslRchRov

RcsdRsd

• Parasitic resistance must be <10% of total FET resistance

• CMOS scaling– reduces channel resistance ∝ 1/L– increases contact resistance Source: Prof. Jason Woo, UCLA

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Contact Resistance Scalingcontact area

Al-Si

Heavily doped Si

reduction of contact area

SALICIDEcontact area

WPlugMSix

contact area

WPlugMSix

– Change in contact scheme (adoption of SALICIDE) has extended the contact scaling

– Due to the reduction of active area, silicide/Si contact resistance is now an issue

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Int’l Technology Roadmap for Semiconductors (2004 update)

Target

2006 2008 2010 2012 2014 2016 2018

10-8

10-7

Ozturk et al., IEDM 2002

ρ c (oh

m-c

m2 )

– New materials and processes are needed

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Impact of Rc on FinFETH. Kam and T.-J. King, 2004 Silicon Nanoelectronics Workshop

Top Contact

DRAIN

GATE

SOURCE

DRAIN

GATE

SOURCE

End Contact

DRAIN

GATE

SOURCE

DRAIN

GATE

SOURCE

Wrapped Contact

DRAIN

GATE

SOURCE

0

400

800

1200

0 0.1 0.2 0.3 0.4 0.5 0.6

Wrapped Contact, ρ c = 0 Wrapped Contact

End Contact

Top Contactρc=10-8 Ω-cm2

Lgate = 18 nm, Leff = 22 nm

34% reduction

16% reduction

• Parasitic resistances dominate FinFET performance• ρC<10-8 Ω-cm2 required

Vds

Ids

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Specific Contact ResistivityBarrier Height and Active Dopant Concentration

⎟⎠

⎞⎜⎝

⎛∝

Nm B

c

φερh

*4exp

Metal Silicon Body

φB

c

cco A

R ρ=

ρc = Contact resistivty

Ac = Contact Area

– Dopant concentration, N– Barrier height, φB

• Fermi-level pinning results in:– Barrier height independent of metal work function

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Approaches to Lowering ρc• Material engineering

– SiGe source/drain• smaller bandgap smaller Schottky barrier

ρc ~10-8 Ω-cm2 for Ni germanosilicides on SiGe• lower resistivity

• Barrier height tuning– image force lowering by dopant segregation

– strain-induced φB reduction

• Fermi-level de-pinning by interface engineering– insertion of insulator layer– selenium passivation

A. Yagishita et al., SSDM, 2003

M. Ozturk et al, IEDM, 2002

M. Tao et al., APL, 2003

A. Kinoshita et al., Symp. VLSI Technology, 2004

D. Connelly et al., IEEE Trans. Nanotech., 2004

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Research Objective• To understand the mechanisms for tuning the effective

Schottky barrier height of a metallic electrode, to guide the engineering of contact-formation processes– Low-φB contacts for reduced parasitic resistance

GateGate

Silicon Substrate

TBOX

TSi

SiO2

SOI

GateGate

Silicon Substrate

TBOX

TSi

SiO2

SOI– Demonstrate fully silicidedsource/drain UTB MOSFETswith improved Idsat by reducing ρc (to <10-8 Ω-cm2) for silicide-to-silicon contacts Schematic Cross-section of

Silicide S/D UTB MOSFET

silicide

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Outline

• Introduction

• Characterization Schemes

• Si1-xGex Source/ Drain

• Dopant Segregation

• Strain

• Summary

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Contact Resistance Measurement

M. Ozturk et al, IEDM, 2002

Minimum measurable resistance is ~10 ΩNeed very small contact holes to determine ρc accurately

below 10-8 Ω-cm-2

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Test structuresmetal pad

active area

• Fabrication of Kelvin structures– Evaluation of contact resistance

• Fabrication of diode– Measure schottky barrier height

Kelvin Structure: Plan View

metalSiO2

lightly-doped Si

Diode: Schematic Cross section

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Fabrication of Sub-0.25µm Contacts

• Contacts were fabricated using DUV stepperASML5500/90; Cymer KrF excimer laser (l=248nm)

85mJ/cm265mJ/cm2 70mJ/cm2 75mJ/cm2 80mJ/cm2

after litho:

188nm 247nm 261nm 268nm 275nm

after etch:

171nm 211nm

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φB extraction • Measure diode I-V

characteristic at different temperatures

1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6

1E-9

1E-8

1E-7

1E-6

J/T2

1000/T

( ) ( )FBneF V

kTqAA

TI

−−≈⎟⎠⎞

⎜⎝⎛ φ**

2 lnln

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Outline• Introduction

• Characterization Schemes

• Si1-xGex Source/ Drain

• Dopant Segregation

• Strain

• Summary

(This work is sponsored by the FLCC project )

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Dopant Behavior in Ultra-Thin SOI

• P-channel thin-body FETs exhibit higher series resistanceDifferent behaviors of B and P in ultra-thin Si– dopant segregation to

interface(s), or into surrounding oxide?TSi=10nm

F.-L. Yang et al., 2004 Symp. VLSI Technology

TSi=80nm

D. Ha et al., IEDM 2004

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Epitaxial Si1-xGex Source/Drain• Epitaxial Si1-xGex source/ drain regions for lowering

Rseries and inducing compressive strain to enhance hole mobility– Conventional approach for epitaxial growth of Si1-xGex is

not possible for thin-body devices because there is not sufficient crystalline substrate after S/D etchback

Si1-xGex Si1-xGexSi1-xGex Si1-xGex

Silicon Substrate

Source Drain

SiO2

SOI

GateGate

Silicon Substrate

Source Drain

SiO2

SOI

GateGate

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Approach

• Develop a process for selectively forming strained Si1-xGex-in-SOI by intermixing Ge & Si– Study the intermixing of Ge with SOI films

• effects of anneal temperature, time, boron doping

– Investigate strain in the resultant Si1-xGex alloy

– Characterize metal-to-Si1-xGex contact resistance

– Germano-silicidation of Si1-xGex to achieve dopant pile-up (to study φB reduction)

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Advantages of This Approach• Selective deposition of Ge by conventional LPCVD

– GeH4 gas, 320oC, 200mT– high process throughput (batch process)

low cost

Ge Source Ge Drain

TSi = 3 nm

Gate

SiO2Si

XTEM of UTB MOSFET w/ raised Ge S/D

Y.-K. Choi et al., IEEE Electron Device Lett., Vol. 22, p. 447, 2001

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Ge/Si Interface Preparation• Selective Ge deposition in LPCVD furnace requires a

clean silicon surface – Interface preparation is critical

• Native oxide removal methods– in-situ HF vapor clean– in-situ HF vapor clean and Hydrogen bake– HF dip followed by Hydrogen bake– in-situ cleaning by GeH4

– Si I/I after Ge deposition• for breaking up any native oxide at the Ge/Si interface

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In-Situ GeH4 CleaningGeO

Silicon Substrate

GeH4

native oxide

H2O

Silicon Substrate

H2

Silicon Substrate

Decreased GeH4 flow to diffuse Ge on the surface

M. Moslehi, Proceedings of SPIE-The international Society for Optical Engineering, vol. 1393, pp.90-108, 1991.

Silicon Substrate

Clean surface

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Si Ion Implantation to Break Up Native Oxide

• Si+ implant has been used to break up the native oxide barrier for Solid-Phase Epitaxy (SPE)Y. C. Yeo et al., IEEE Transactions on Electron Devices, Vol. 49, No. 2, pp.279-286, 2002.

Si +

Silicon Substrate

Ge

Silicon Substrate

Ge

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Test Sample Process Flow• Starting wafers

– n-type, ρ=5-10 µΩ-cm• Cross-sectional TEM pattern

formation– CVD SiO2 deposition (52nm)

– Lithography– Oxide etching (90% dry + 10% wet)

Silicon substrate

Silicon substrate

CVD SiO2

SiO2 SiO2

Silicon substrate

Top-down view through optical microscope

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Process Flow (Cont’d)• Interface Preparation

– HF last / HF vapor• Selective Ge deposition (22nm)

– 320oC/200mTorr/100sccm– Capping layer (25nm)

• Si Implant– Si : 40keV, 1E15 cm-2

• Doping– B : 10keV, 2E15 cm-2

• Recrystallization – 500oC, 1 hour

• Intermixing anneal– 800oC/ 850oC, 1minute

SiO2 SiO2

Silicon substrateGe Ge Ge

Ge GeSiO2Ge SiO2

SiO2

Silicon Substrate

Silicon Substrate

SiO2 SiO2

SiO2

Si1-xGex

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Experimental Splits4 1

23Si Bon wafer splits = 4

B I/I4

none3

Si I/I2

Si I/I + B I/I1

B I/I4

none3

Si I/I2

Si I/I + B I/I1

Split Table:

xxxxxxxx850 C

xxxxxxxx800 CAnnealing

xxxxnone

xxxxSi I/I + B I/I

xxxxB I/I

xxxxSi I/II/I splits

xxxxxxxxHF vapor

xxxxxxxxHF LastCleaning

Wafer ID

xxxxxxxx850 C

xxxxxxxx800 CAnnealing

xxxxnone

xxxxSi I/I + B I/I

xxxxB I/I

xxxxSi I/II/I splits

xxxxxxxxHF vapor

xxxxxxxxHF LastCleaning

Wafer ID

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Determining Ge and B profiles(in collaboration with Prof. Haller’s group)

• Characterization of vertical and lateral co-diffusion of Ge and B– Available Options:

• Cross-sectional TEM with EDX nanoprobe• Cross-sectional TEM with EELS• Cross-sectional SEM with EDX nanoprobe

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Summary and Future GoalsSi1-xGex Source/Drain

• Fabrication of first batch is finished– Splits for Doped/ undoped Ge, interface preparation,

annealing conditions etc.

– Results of this batch are awaited

• Future Work:– Characterization of boron-doped Si1-xGex-on-insulator

resistance

– Characterization of metal-to-Si1-xGex contact resistance• Germano-silicidation of Si1-xGex to achieve dopant pile-up

for Schottky barrier height (φB) reduction

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Outline

• Introduction

• Characterization Schemes

• Si1-xGex Source/ Drain

• Dopant Segregation

• Strain

• Summary

(This work is sponsored in part by Intel Corp.)

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φB Reduction by Dopant Segregation• φB can be reduced by using an ultrathin (<10nm) heavily doped layer at the semiconductor surfaceJ. Shannon, Applied Physics Letters, Vol. 24, pp. 369-371, 1974.

– image force lowering (∆φ) due to surface electric field

N = dopant concentration in surface layer

a = width of heavily doped surface layerπεφ

4aNq

si

=∆

Such a thin heavily doped layer can be formed by silicidation-induced dopant segregation:A. Kinoshita et al., 2004 Symp. VLSI Technology, Digest of Technical Papers, pp. 168-169.

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ExperimentGoals: Confirm dopant segregation w/ NiSi

Investigate dopant activation

Process sequence:• starting Si wafer (n-type/ p-type)• deposit capping layer, CVD SiO2• blanket implantation (B- 20KeV, 1016cm-2 As- 80KeV, 6×1015cm-2)• spike annealing@1000C• strip capping layer• excimer laser annealing• Ni deposition• silicidation• strip unreacted Ni

starting substrate

Ni

unreacted Ni

NiSi

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Results: SIMS Analyses

0 20 40 60 80 100 120 140 1601E17

1E18

1E19

1E20

1E21

1E22

O

NiSi

As

Con

cent

ratio

n (a

tom

s/cm

-3)

Depth (nm)

1

10

100

1000

10000

100000

Cou

nts/

sec

– Dopant pile-up at silicide/ Si interface is seen for both As and B doping (only As shown here)

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Schottky Barrier Lowering• Image Force Effect

– Induced charges at the interface– Equivalent to an image charge

16mS

qxEπε

=

SemiconductorMetal

EF

EC

xqV

qφB

qVb

qφBO

q∆φ

xm W

-qψ(x)

qExx

qxPEs

−−=επ16

)(2

Eqs

•=∆⇒επ

φ4

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Tailoring the Surface Electric Field

• ∆φ depends on the surface electric field– Lightly doped substrate:

• Low E, barrier-lowering is sensitive to reverse bias– Heavily doped substrate:

• High E φB is reduced, but reverse current increasestunneling Ohmic contact !

• To retain Schottky junction properties and to achieve ∆φ that is insensitive to bias, a heavily doped surface layer that is fully depleted by the built-in potential is needed

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Fully-Depleted Doped Surface Layer

• The required electric field has been shown to be >5×105 V/cmJ. Shannon, Applied Physics Letters, Vol. 24, pp. 369-371, 1974.

– Maximum surface field arising from implantation of a symmetrical distribution of charge about range Rp:

p

bs R

VE ≅max,

)(0 fcBb EEqqV −−= φqφB

q∆φ

qφBO

q∆φ

higher carrier concentration

lower carrier concentration

qVb

For a metal contacting a lightly doped substrate, built-in potential Vb~0.45V

ARp 100<⇒

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ΦB Reduction Model• Maximum surface field, Es,max

NB

NiSi

Np

NiSiNB

Np

a

[ ])(max, aWNaNqE Bp

s

s −+=ε

aNqE p

s

s ε≅max,

πεφ

4aNq p

s

≅∆⇒

Expected barrier height lowering due to a thin highly doped surface layer:

1018 1019 10200.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

design space

a=100A0

a=50A0

Bar

rier l

ower

ing,

eV

active dopant conc. in surface layer (cm-3)

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Effect of Interface States• Metal-induced gap states (MIGS)

– Penetration of wave function from the metal into the forbidden energy gap of Si

qφBO

Ef

Metal Semiconductor

Metallic wave penetration in metal-semiconductor system

λ

ελ

επx

ss

eqQqExx

qxPE −−−−=16

)(2

Electron potential energy including the contributions of image force and MIGS K. Shenai et al., IEEE TED, Vol. ED-32, No. 4, pp. 793-799, 1985

Q = magnitude of surface state charge

λ = penetration depth of surface state charge

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∆φ Inverse Modeling Approach– Find the location of PE(x) minimum

– Total barrier lowering is given by

– Solve Poisson’s equation to find Ψ0(x)

– Extract Q and λ from measured forward I-V characteristics

– Predict total barrier lowering from the model • Np, work-function difference, Q, and λ are input parameters

0)(16 2

2

=+−⇒ − λ

επεmx

s

m

ms

eqQxqEx

q0))(( =

= mxxxPE

dxd

λ

ελψψ

πεφ

mx

s

m

ms

eQxx

q −+−−=∆ )()0(16 00

s

xxερψ )()(0

2 −=∇

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Determining Active Dopant Concentration• Spreading Resistance Probe (SRP):

– within 1/2 the probe spacing (~10µm) of the Si/ silicide interface, silicide starts affecting readings because of low resistanceNeed to remove NiSi selectively• surface roughness increase• difficult to find bevel edge

NiSi

Si

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Summary and Future WorkDopant Segregation

• Ni silicidation induced dopant segregation phenomenon confirmed

• A quantitative inverse-modeling approach has been established for determining the amount of Schottky-barrier lowering

• Future Work:– Fabrication and characterization of diode structures and

Kelvin structures– Application of dopant-segregation technique to improve

FinFET performance by reducing S/D contact resistance

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Outline

• Introduction

• Characterization Schemes

• Si1-xGex Source/ Drain

• Dopant Segregation

• Strain

• Summary

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φB Reduction by Si StrainA. Yagishita et al., SSDM 2003

– 1% bi-axial strain reduces φB by 0.1eV (ErSi1.7 S/D NMOSFET)

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Experimental Plan

K. Uchida et al., IEDM 2004

• Use a bending apparatus– apply uniaxial or biaxial bending

stress to Si chips

• Study φB reduction– Fabricate Schottky diodes and

contact test structures to measure effect of strain on ρc

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Outline

• Introduction

• Characterization Schemes

• Si1-xGex Source/ Drain

• Dopant Segregation

• Strain

• Summary

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Summary• Source/drain contact resistance can limit the

performance of nanoscale FETs– ρc ~10-9 Ω-cm2 will be required

• Approaches for reducing ρc include use of Si1-xGexin the source/drain regions, dopant segregation, and strain

• Work in progress will clarify the mechanisms for lowering the effective Schottky barrier height φB

Application to nanoscale thin-body FETs

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Acknowledgements

• Akira Hokazono (Toshiba Corporation)• Dr. Chi On Chui (Intel Corporation)

• Research funding from– UC Discovery Grant program and member companies

of the Feature-Level Compensation and Control (FLCC) project at UC-Berkeley

– Intel Corporation