Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN74LVC1G17 SCES351V – JULY 2001 – REVISED APRIL 2014 SN74LVC1G17 Single Schmitt-Trigger Buffer 1 Features 3 Description This single Schmitt-trigger buffer is designed for 1• Available in Ultra Small 0.64-mm 2 1.65-V to 5.5-V V CC operation. Package (DPW) With 0.5-mm Pitch The SN74LVC1G17 device contains one buffer and • Supports 5-V V CC Operation performs the Boolean function Y = A. • Inputs Accept Voltages to 5.5 V The CMOS device has high output drive while • Max t pd of 4.6 ns at 3.3 V maintaining low static power dissipation over a broad • Low Power Consumption, 10-μA Max I CC Vcc operating range. • ±24-mA Output Drive at 3.3 V The SN74LVC1G17 is available in a variety of • I off Supports Live Insertion, Partial-Power-Down packages, including the ultra-small DPW package Mode, and Back-Drive Protection with a body size of 0.8 mm × 0.8mm. • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Device Information (1) DEVICE NAME PACKAGE BODY SIZE • ESD Protection Exceeds JESD 22 SOT-23 (5) 2.9mm × 1.6mm – 2000-V Human-Body Model (A114-A) SC70 (5) 2.0mm × 1.25mm – 200-V Machine Model (A115-A) SN74LVC1G17 X2SON (4) 0.8mm × 0.8mm – 1000-V Charged-Device Model (C101) SON (6) 1.45mm × 1.0mm SON (6) 1.0mm × 1.0mm 2 Applications (1) For all available packages, see the orderable addendum at • AV Receiver the end of the datasheet. • Audio Dock: Portable • Blu-ray Player and Home Theater • MP3 Player/Recorder • Personal Digital Assistant (PDA) • Power: Telecom/Server AC/DC Supply: Single Controller: Analog and Digital • Solid State Drive (SSD): Client and Enterprise • TV: LCD/Digital and High-Definition (HDTV) • Tablet: Enterprise • Video Analytics: Server • Wireless Headset, Keyboard, and Mouse 4 Simplified Schematic 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SN74LVC1G17SCES351V –JULY 2001–REVISED APRIL 2014
SN74LVC1G17 Single Schmitt-Trigger Buffer1 Features 3 Description
This single Schmitt-trigger buffer is designed for1• Available in Ultra Small 0.64-mm2
1.65-V to 5.5-V VCC operation.Package (DPW) With 0.5-mm PitchThe SN74LVC1G17 device contains one buffer and• Supports 5-V VCC Operationperforms the Boolean function Y = A.• Inputs Accept Voltages to 5.5 VThe CMOS device has high output drive while• Max tpd of 4.6 ns at 3.3 Vmaintaining low static power dissipation over a broad• Low Power Consumption, 10-μA Max ICC Vcc operating range.
• ±24-mA Output Drive at 3.3 VThe SN74LVC1G17 is available in a variety of• Ioff Supports Live Insertion, Partial-Power-Down packages, including the ultra-small DPW packageMode, and Back-Drive Protection with a body size of 0.8 mm × 0.8mm.
• Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II Device Information(1)
DEVICE NAME PACKAGE BODY SIZE• ESD Protection Exceeds JESD 22SOT-23 (5) 2.9mm × 1.6mm– 2000-V Human-Body Model (A114-A)SC70 (5) 2.0mm × 1.25mm– 200-V Machine Model (A115-A)
(1) For all available packages, see the orderable addendum at• AV Receiverthe end of the datasheet.
• Audio Dock: Portable• Blu-ray Player and Home Theater• MP3 Player/Recorder• Personal Digital Assistant (PDA)• Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital• Solid State Drive (SSD): Client and Enterprise• TV: LCD/Digital and High-Definition (HDTV)• Tablet: Enterprise• Video Analytics: Server• Wireless Headset, Keyboard, and Mouse
4 Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.
Changes from Revision T (November 2012) to Revision U Page
• Added Applications. ................................................................................................................................................................ 1• Moved Tstg to Handling Ratings table. .................................................................................................................................... 4• Changed MAX operating free-air temperature from 85°C to 125°C....................................................................................... 5• Added –40°C to 125°C to Electrical Characteristics table...................................................................................................... 6• Added Switching Characteristics table for –40°C to 125°C temperature range..................................................................... 7
Changes from Revision S (June 2011) to Revision T Page
• Removed Ordering Information table. .................................................................................................................................... 3
SN74LVC1G17SCES351V –JULY 2001–REVISED APRIL 2014 www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 VVI Input voltage range (2) –0.5 6.5 VVO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 VVO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 VIIK Input clamp current VI < 0 –50 mAIOK Output clamp current VO < 0 –50 mAIO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions tables is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3) The value of VCC is provided in the Recommended Operating Conditions table.
7.2 Handling RatingsMIN MAX UNIT
Tstg Storage temperature range –65 150 °CHuman-Body Model (HBM) (2) 0 2 kV
VESD(1)
Charged-Device Model (CDM) (3) 0 1 kV
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges into the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allowssafe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
SN74LVC1G17www.ti.com SCES351V –JULY 2001–REVISED APRIL 2014
7.3 Recommended Operating Conditions (1)
MIN MAX UNITOperating 1.65 5.5
VCC Supply voltage VData retention only 1.5
VI Input voltage 0 5.5 VVO Output voltage 0 VCC V
VCC = 1.65 V –4VCC = 2.3 V –8
IOH High-level output current –16 mAVCC = 3 V
–24VCC = 4.5 V –32VCC = 1.65 V 4VCC = 2.3 V 8
IOL Low-level output current 16 mAVCC = 3 V
24VCC = 4.5 V 32
TA Operating free-air temperature –40 125 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 .
D. The outputs are measured one at a time, with one transition per measurement.E. t and t are the same as t .
F. t and t are the same as t .
G. t and t are the same as t .
H. All parameters and waveforms are not applicable to all devices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
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VOLTAGE WAVEFORMSPULSE DURATION
VOLTAGE WAVEFORMSSETUP AND HOLD TIMES
VI
VI
VI
VM
VM
V /2LOAD
tPZL tPLZ
tPHZtPZH
V – VOH D
V + VOL D
VM
VM VM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLHtPHL
SN74LVC1G17SCES351V –JULY 2001–REVISED APRIL 2014 www.ti.com
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 .
D. The outputs are measured one at a time, with one transition per measurement.E. t and t are the same as t .
F. t and t are the same as t .
G. t and t are the same as t .
H. All parameters and waveforms are not applicable to all devices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGE WAVEFORMSPULSE DURATION
VOLTAGE WAVEFORMSSETUP AND HOLD TIMES
VI
VI
VI
VM
VM
V /2LOAD
tPZL tPLZ
tPHZtPZH
V – VOH D
V + VOL D
VM
VM VM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLHtPHL
SN74LVC1G17www.ti.com SCES351V –JULY 2001–REVISED APRIL 2014
SN74LVC1G17SCES351V –JULY 2001–REVISED APRIL 2014 www.ti.com
9 Detailed Description
9.1 OverviewThe SN74LVC1G17 device contains one Schmitt trigger buffer and performs the Boolean function Y = A. Thedevice functions as an independent buffer, but because of Schmitt action, it will have different input thresholdlevels for a positive-going (VT+) and negative-going signals.
The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint savessignificant board space over other package options while still retaining the traditional manufacturing friendly leadpitch of 0.5 mm.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
9.2 Functional Block Diagram
9.3 Feature Description• Wide operating voltage range.
– Operates From 1.65 V to 5.5 V.• Allows Down voltage translation.• Inputs accept voltages to 5.5 V.• Ioff feature allows voltages on the inputs and outputs, when VCC is 0 V.
SN74LVC1G17www.ti.com SCES351V –JULY 2001–REVISED APRIL 2014
10 Applications and Implementation
10.1 Application InformationThe SN74LVC1G14 is a high drive CMOS device that can be used for a multitude of buffer type functions wherethe input is slow or noisy. It can produce 24 mA of drive current at 3.3 V making it Ideal for driving multipleoutputs and good for high speed applications up to 100 MHz. The inputs are 5.5 V tolerant allowing it to translatedown to VCC.
10.2 Typical Application
10.2.1 Design RequirementsThis device uses CMOS technology and has balanced output drive. Care should be taken to avoid buscontention because it can drive currents that would exceed maximum limits. The high drive will also create fastedges into light loads so routing and load conditions should be considered to prevent ringing.
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC .2. Recommend Output Conditions
– Load currents should not exceed (IO max) per output and should not exceed (continuous current throughVCC or GND) total current for the part. These limits are located in the Absolute Max Ratings table.
11 Power Supply RecommendationsThe power supply can be any voltage between the min and max supply voltage rating located in theRecommended Operating Conditions table.
Each Vcc pin should have a good bypass capacitor to prevent power disturbance. For devices with a singlesupply a 0.1-μF capacitor is recommended and if there are multiple Vcc pins then a 0.01-μF or 0.022-μFcapacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject differentfrequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should beinstalled as close to the power pin as possible for best results.
12 Layout
12.1 Layout GuidelinesWhen using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functionsof digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only3 of the 4 buffer gates are used. Such input terminals should not be left unconnected because the undefinedvoltages at the outside connections result in undefined operational states. Specified below are the rules that mustbe observed under all circumstances. All unused inputs of digital logic devices must be connected to a high orlow bias to prevent them from floating. The logic level that should be applied to any particular unused inputdepends on the function of the device. Generally they will be tied to Gnd or Vcc whichever make more sense oris more convenient.
SN74LVC1G17www.ti.com SCES351V –JULY 2001–REVISED APRIL 2014
13 Device and Documentation Support
13.1 TrademarksAll trademarks are the property of their respective owners.
13.2 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
13.3 GlossarySLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
14 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical packaging and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.
SN74LVC1G17DSF2 PREVIEW SON DSF 6 5000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 C7
SN74LVC1G17DSFR ACTIVE SON DSF 6 5000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 C7
SN74LVC1G17YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS& no Sb/Br)
SNAGCU Level-1-260C-UNLIM -40 to 85 (C77 ~ C7N)
SN74LVC1G17YZVR ACTIVE DSBGA YZV 4 3000 Green (RoHS& no Sb/Br)
SNAGCU Level-1-260C-UNLIM -40 to 85 C7(7 ~ N)
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G17 :
• Automotive: SN74LVC1G17-Q1
• Enhanced Product: SN74LVC1G17-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
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