Scaling Formal Methods Toward Hierarchical Protocols in Shared Memory Processors Presenters: Ganesh Gopalakrishnan and Xiaofang Ch School of Computing , University of Utah, Salt Lake City, UT 84112 {ganesh, xiachen}@cs.utah.edu http://www.cs.utah.edu/formal_verification GRC CADTS Review, Berkeley, March 18, 2008 Supported by SRC Contract TJ-1318 (Intel Customization)
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Scaling Formal Methods Toward Hierarchical Protocols in Shared Memory Processors
Scaling Formal Methods Toward Hierarchical Protocols in Shared Memory Processors. GRC CADTS Review, Berkeley, March 18, 2008. Presenters: Ganesh Gopalakrishnan and Xiaofang Chen School of Computing , University of Utah, Salt Lake City, UT 84112 {ganesh, xiachen}@cs.utah.edu - PowerPoint PPT Presentation
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Scaling Formal Methods Toward Hierarchical Protocols in Shared Memory Processors
Presenters: Ganesh Gopalakrishnan and Xiaofang ChenSchool of Computing , University of Utah, Salt Lake City, UT 84112
{ganesh, xiachen}@cs.utah.edu
http://www.cs.utah.edu/formal_verification
GRC CADTS Review, Berkeley, March 18, 2008
Supported by SRC Contract TJ-1318 (Intel Customization)
2
Multicores are the future! Their caches are visibly central…
(photo courtesy of
Intel Corporation.)
> 80% of chipsshipped will bemulti-core
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Hierarchical Cache Coherence Protocols will play a major role in multi-core processors
Chip-level protocols
Inter-cluster protocols
Intra-cluster protocols
dirmem dirmem
…
State Space grows multiplicatively across the hierarchy!
Verification will become harder
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Protocol design happens in “the thick of things” (many interfaces, constraints of performance, power, testability).
From “High-throughput coherence control and hardware messaging in Everest,” by Nanda et.al., IBM J.R&D 45(2), 2001.
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Future Coherence Protocols
Cache coherence protocols that are tuned for the contexts in which they are operating can significantly increase performance and reduce power consumption [Liqun Cheng] Producer-consumer sharing pattern-aware protocol [Cheng
et.al, HPCA07] 21% speedup and 15% reduction in network traffic
Interconnect-aware coherence protocols [Cheng et.al., ISCA06] Heterogeneous Interconnect Improve performance AND reduce power 11% speedup and 22% wire power savings
Bottom-line: Protocols are going to get more complex!
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Main Result #1 : Hierarchical
RAC
L2 Cache+Local Dir
L1 Cache
Main Mem
Home ClusterRemote Cluster 1
Remote Cluster 2
L1 Cache
Global Dir
RAC
L2 Cache+Local Dir
L1 Cache
L1 Cache
RAC
L2 Cache+Local Dir
L1 Cache
L1 Cache
Intra-cluster
Inter-cluster
Developed way to reduce verification complexity of
hierarchical (CMP) protocols using A/G
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Main Result #2 : Refinement
Developed way to Verify a Proposed Refinement of
ONE unit into its low level (RTL) implementation
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Main Result #2 : Refinement
Developed way to Verify a Proposed Refinement of
ONE unit into its low level (RTL) implementation
Murphi
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Main Result #2 : Refinement
Developed way to Verify a Proposed Refinement of
ONE unit into its low level (RTL) implementation
Murphi
10
Main Result #2 : Refinement
Developed way to Verify a Proposed Refinement of
ONE unit into its low level (RTL) implementation
Murphi
HMurphi
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Differences in Modeling: Specs vs. Impls
home remote
One step in high-level
Multiple steps in low-level
an atomic guarded/command
home
router
buf
remote
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Our Refinement Check
Spec(I)
I
Spec(I’)Spec
transition
Multi-step Impl
transactionI’
Guard for Spec transition must
hold
I is a reachable Impl state
Observable vars changed
by either must match
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Workflow of Our Refinement Check
Hardware Murphi
Impl model
Product model in
Hardware Murphi
Product model in VHDL
MurphiSpec model
Property check
Muv
Check implementation meets specification
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Anticipated Future Result
Developed way to Verify a Proposed Refinement of
the ENTIRE hierarchy
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Anticipated Future Result
Deal with pipelining
Sequential InteractionPipelined Interaction
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Anticipated Future Result
Develop ways to “tease apart” protocols that are “blended in”
e.g. for power-down or post-si observability enhancement
More protocols…
.. do they interfere?
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Basics
PI : Ganesh Gopalakrishnan Industrial Liaisons : Ching Tsun Chou (Intel), Steven M. Geman (IBM),
John W. O’Leary (Intel), Jayanta Bhadra (Freescale), Alper Sen (Freescale), Aseem Maheshwari (TI)
Primary Student : Xiaofang Chen Graduation Date : Writing PhD Dissertation; in the market Other Students :Yu Yang (PhD), Guodong Li (PhD), Michael DeLisi
(BS/MS) Anticipated Results:
Hierarchical : Methodology for Hierarchical (Cache Coherence) Protocol Verification, with Emphasis on Complexity Reduction (was in original SRC proposal)
Refinement : Methodology for Expressing and Verifying Refinement of Higher Level Protocol Descriptions (not in original SRC proposal)