SCALe-UVM-REG -Flow.pptx

Slide 1

UVM REG Migration PlanAug 2013PAGE #| QUALCOMM CONFIDENTIAL & PROPRIETARY | RESTRICTED DISTRIBUTION1OVM/UVM RGM Generation Flow

PAPI.mif.vRTL.html.htmlVisualizationSW/FWVeraDocumentDelta ReportAutoreg Golden Source.blk.blkHDL Headers.vh.vhd.h.asm.vri.vri.vri.vr.vr.svFLATfileLegacyUVM RGMAutoreg Perl WrapperAutoregPAPI GeneratorsPAGE #| QUALCOMM CONFIDENTIAL & PROPRIETARY | RESTRICTED DISTRIBUTIONAutoreg

IP-XACT XMLAutoreg Golden Source.blk.blkVendor UVM Generator.vr.svUVM REG/RALAutoreg Perl Wrapper.seq.vr.svUVM SequenceUVM REG Generation FlowLeverage existing UVM generators from vendorsIntercept vendor generators with IP-XACT XMLs to make SCALe solution vendor-neutralGenerate IP-XACT from Scale (Autoreg version 1.9)Use reg gen scripts from Cadence(IREGGEN) or Synopsys(RALGEN) to generate UVM REG. Added the support for Synopsys script, Autoreg itself generates the Data base file for Synopsys. Generated code can be used with any simulator. PAGE #| QUALCOMM CONFIDENTIAL & PROPRIETARY | RESTRICTED DISTRIBUTIONWhy UVM REGIndustry Accellera standardVendor neutral. Vendors are moving to UVM REG and dropping custom solutions like RGMBetter architecture than RGM and more functionality

PAGE #| QUALCOMM CONFIDENTIAL & PROPRIETARY | RESTRICTED DISTRIBUTIONSupported FeaturesArray registerUser-specified address interval stride per index incrementNon-zero start index2-D arrayRead-write conjugates (twin register, overlap) Same address but separate storagesOne is read-only and the other one is write-onlyWrite-1-to-clear , RTC , WITSWrite 1 to certain bit field to clear the bit field or the entire parent registerSimilar support for write-0-to-clear, read-to-clearExclude registers from standard test sequence :csrsettingExclude read and/or write accessesExclude selected registers and/or bit fieldsExclude from certain test, e.g. alias, reset, etc.Banked registersSame address but separate storagesControlled by an external signalUVM base class library support for banked registers

PAGE #| QUALCOMM CONFIDENTIAL & PROPRIETARY | RESTRICTED DISTRIBUTIONNon supported RegistersMode-dependent register Same address and same storageBit field and enum definitions changeControlled by a bit field from the same register or another registerRegister AliasingSame register (same storage) accessible from different address offsetsIndirect registersSW only accesses a control register which contains index field and data fieldIndirect access to shadow (indirect) registers based on the index and data fields of the control registerShadow registers not accessible by SWDouble-buffer registersA pair of registers: front-end and shadowSW writes to the front-end register onlyHW reads from the shadow register onlyAn external signal latches data from front-end register to the shadow registerRetention Register

PAGE #| QUALCOMM CONFIDENTIAL & PROPRIETARY | RESTRICTED DISTRIBUTIONIP-XACT support and Vendor ExtensionsScale IP-XACT supports vendor extensions for below features in cadence define format:Array registersOverlap registersBanked registersField access events (W1TC, W1TS, RTC)Exclude registers/fields from tests (CSR)Scale IP-XACT supports vendor extensions for below features in Synopsys define format:Array registers(Multi Dimensional Array Registers)Overlap registersBanked registersLinear stride index in IPXACT

PAGE #| QUALCOMM CONFIDENTIAL & PROPRIETARY | RESTRICTED DISTRIBUTIONIP-XACT ExamplesFor Bank registers

secure true

For Array Registers

0 3 'h110+'h4*x ("BLK_ARR2_%0d%0d%0d", x)

PAGE #| QUALCOMM CONFIDENTIAL & PROPRIETARY | RESTRICTED DISTRIBUTIONHow to Generate UVM REG (Cadence)Use SCALe Autoreg version 2.1 setenv AUTOREG_VERSION 2.1

Generate IP-XACT from AutoregAutoreg -gen_ipxact cadence -gen_qcsr ARM This will generate IP-XACT (xml) file.

Set the path of UVM_HOME and IREG_GEN and use ireggen script as below$IREG_GEN/bin/iregGen \ -i \ -d output_ireggen \ -pkg my_pkg -ta _t -ncThis will generate UVM REG files.

PAGE #| QUALCOMM CONFIDENTIAL & PROPRIETARY | RESTRICTED DISTRIBUTIONHow to Generate UVM REG Use SCALe Autoreg version 2.1 setenv AUTOREG_VERSION 2.1

Generate IP-XACT from Autoreg Autoreg -gen_ipxact synopsys -gen_qcsr ARM This will generate IP-XACT(xml) file and UVM REG files too.

No need to generate UVM REG files separately for Synopsys as Autoreg calls ralgen scripts internally and generates the UVM REG files

Complete working example is available at/prj/iceng/SCALe/release/examples/integartion_and_simulation/uvm_reg/

PAGE #| QUALCOMM CONFIDENTIAL & PROPRIETARY | RESTRICTED DISTRIBUTIONUVM REG Access APIswrite()/read(): Write/read immediate value to DUT. set()/get() : Sets or gets mirrored/shadow-registers value. randomize() : Using the randomize() method copies the randomized value in the uvm_reg_field::value property into the desired value of the mirror by the post_randomize() method.update() : Invokes the write() method if the desired value (previously modified using set() or randomize()) is different from the mirrored value.mirror() : Invokes the read() method to update the mirrored value based on the readback value. mirror() can also compare the readback value with the current mirrored value before updating it.

PAGE #| QUALCOMM CONFIDENTIAL & PROPRIETARY | RESTRICTED DISTRIBUTIONExample of Register Sequencesclass blk_seq extends uvm_reg_sequence; my_regfile model; `uvm_object_utils(blk_seq) function new ( string name=blk_seq ); super.new(name); endfunction : new virtual task body(); uvm_status_e status; int data; model.config.write(status, h12, .parent(this)); model.config.write(status, h34, UVM_BACKDOOR, .parent(this)); model.config.read(status, data, UVM_BACKDOOR, .parent(this)); model.my_mem.write(status, h8, h1234_5678, .parent(this)); void'(model.randomize()); model.update(status, UVM_BACKDOOR, .parent(this)); model.mirror(status, UVM_CHECK, UVM_BACKDOOR, .parent(this)); endtask : bodyendclass : blk_seq12Frontdoor WriteBackdoor WriteBackdoor ReadContainer levelBackdoor updateContainer levelBackdoor mirrorPointer to the register model containerMemory frontdoorNote that there are read/write tasks that cover the do itemsPAGE #| QUALCOMM CONFIDENTIAL & PROPRIETARY | RESTRICTED DISTRIBUTIONMore Information on SCALeSCALe Wikigo/scaleIncludes FAQ, documentation, training, examples, and link to eRoom

SCALe email listsscale.usersUser email list.Receive notification emails for new releases.This email list also controls eRoom access.scale.helpOpen an RT ticket to ask for help with tool.

PAGE #| QUALCOMM CONFIDENTIAL & PROPRIETARY | RESTRICTED DISTRIBUTIONThank YouQUALCOMM CONFIDENTIAL AND PROPRIETARY | INTERNAL USE ONLY | RESTRICTED DISTRIBUTIONPAGE #PAGE #| QUALCOMM CONFIDENTIAL & PROPRIETARY | RESTRICTED DISTRIBUTION