SBCCI’08 - 1-4 September - Gramado, Brazil :: These slides are available at http://www.slideshare.net/josemmf (1) A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures J. M. Martins Ferreira [ [email protected] ] FEUP / DEEC Rua Dr. Roberto Frias 4200-465 Porto - PORTUGAL André Fidalgo, Gustavo R. Alves Manuel Gericota [ anf/gca/mgg @isep.ipp.pt ] ISEP / DEE Rua Ant. Bernardino Almeida, 431 4200-072 Porto - PORTUGAL SBCCI’08: Gramado, Brazil, 1-4 September 2008 These slides are available at http://www.slideshare.net/josemmf
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SBCCI’08 - 1-4 September - Gramado, Brazil :: These slides are available at http://www.slideshare.net/josemmf (1)
A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures
A comparative analysis of fault injection methods via enhanced on-chip debug infrastructuresJ. M. Martins Ferreira [ [email protected] ]FEUP / DEECRua Dr. Roberto Frias4200-465 Porto - PORTUGAL
André Fidalgo, Gustavo R. Alves Manuel Gericota [ anf/gca/mgg @isep.ipp.pt ]ISEP / DEE Rua Ant. Bernardino Almeida, 4314200-072 Porto - PORTUGAL
SBCCI’08: Gramado, Brazil, 1-4 September 2008These slides are available at http://www.slideshare.net/josemmf
SBCCI’08 - 1-4 September - Gramado, Brazil :: These slides are available at http://www.slideshare.net/josemmf (2)
A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures
SBCCI’08 - 1-4 September - Gramado, Brazil :: These slides are available at http://www.slideshare.net/josemmf (3)
A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures
Scope, focus, setup
• Scope: usage of OCD resources for validating fault tolerance / fault injection
• Focus: comparative analysis of experimental results for various OCD configurations and debugging scenarios
• Setup: a) 32-bit Freescale MPC-565, iSystem IC3000 (iTracePro), Winidea 2005 b) OCD enhancements in VHDL
SBCCI’08 - 1-4 September - Gramado, Brazil :: These slides are available at http://www.slideshare.net/josemmf (4)
A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures
Motivation
• OCD offers controllability and observability features that may be used to inject faults and observe their effect (R/W access to registers and memory)
• Usefulness for fault tolerance validation may be limited in bandwidth, coverage and repeatability / representativeness of results
• Mitigation is possible by enhancing OCD
SBCCI’08 - 1-4 September - Gramado, Brazil :: These slides are available at http://www.slideshare.net/josemmf (5)
A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures
• Each application was implemented in two versions: normal and fault tolerant
• Fault tolerance by duplicating data in memory and repeating each operation
SBCCI’08 - 1-4 September - Gramado, Brazil :: These slides are available at http://www.slideshare.net/josemmf (9)
A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures
Fault injection campaigns
• Scripts that define 10 FI experiments during system operation
• 100 campaigns were executed for each scenario using the three workload applications (Madder, Vsorter, Xcontrol)
• FI campaigns mostly target memory positions and cause a bit-flip to emulate SEU effects
SBCCI’08 - 1-4 September - Gramado, Brazil :: These slides are available at http://www.slideshare.net/josemmf (10)
A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures
Predetermination to improve performance of FI campaigns• Predetermination of the contents of the
target memory cell at the FI instant may be done through a “gold run” or by ensuring:– Complete knowledge of the program flow– Full observability of external inputs– Precise control of the FI instant and location
• Otherwise the target memory cell must be read “immediately” before the FI instant
SBCCI’08 - 1-4 September - Gramado, Brazil :: These slides are available at http://www.slideshare.net/josemmf (11)
A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures
Experimental scenarios
Configur. &
ScenarioBandwidth
Predetermination of the faulty value
Fault injection method
Delays (Clk cycles)
Set-Up Insertion
BOF MDI=2 MDO=8 YES Offline 22 35
BOF+ MDI=2 MDO=8 NO Offline 22 44
EOF MDI=8 MDO=8 YES Offline 6 9
EOF+ MDI=8 MDO=8 NO Offline 6 18
BRT MDI=2 MDO=8 YES Real Time 22 35
BRT+ MDI=2 MDO=8 NO Real Time 22 44
ERT MDI=8 MDO=8 YES Real Time 6 9
ERT+ MDI=8 MDO=8 NO Real Time 6 18
OCD-FI MDI=2 MDO=8 YES Real Time 57 2
OCD-FI+ MDI=2 MDO=8 NO Real Time 57 4
B: Basic; E: Extended; OCD-FI : OCD for Fault InjectionOF: Off-line; RT: Real-time; +: predetermination not required
SBCCI’08 - 1-4 September - Gramado, Brazil :: These slides are available at http://www.slideshare.net/josemmf (12)
A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures
Experimental results (%): B, E, OCD-FI (results)
UERR: Undetected errors (incorrect final result that goes undetected)DERR: Detected errors (error detection signal activated)NERR: No errors (application ended correctly)