Santa Clara Valley Chapter, CPMT Society February 8, 2006 …ewh.ieee.org/soc/cpmt/presentations/cpmt0602a.pdf · 2006-02-09 · Bellcore/Telcordia Exception TR-NWT-000078 N/A Granted
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Santa Clara Valley Chapter, CPMT Societywww.cpmt.org/scv/
Impedance Characterization and Design Optimization of PCB Embedded Passive ComponentsPresented at the Feb. 8 2006 meeting, Santa Clara Valley Chapter, CPMT Society – www.cpmt.org/scv/
Nick Biunno and Franz GisinSanmina-SCI, CorpSan Jose, CA
Embedded Resistor Technology Drivers
High density component packages
Form factor reduction
Faster signal speed
Improved Signal Integrity noise margins
Weight reduction
Santa Clara Valley Chapter, CPMT Societywww.cpmt.org/scv/
February 8, 2006
Page 2
Embedded Passives Now All About Infrastructure
• CAD/CAM Design Support (what to embedded?)
• Cost Modeling
• Design Input and Design Rules
• Embedded Component Impedance Characterization
• Signal Integrity and Component Simulation
• NPI Proto-Typing and Volume Manufacturing
• Test and Reliability
• Standards
Future
Embedded Passive Technology Portfolio
C Capacitor L Inductor (Planar Magnetics)R Resistor
Embedded Passives
Discrete Networks DistributedBuried Capacitance®
C LR R C RCPower Distribution
NetworksDigital and AnalogApplications Low, High & Band Pass Filters
Resistive Networks
Santa Clara Valley Chapter, CPMT Societywww.cpmt.org/scv/
February 8, 2006
Page 3
Resistor Analysis for Embedded Conversion
Value Total Power Surface Embed Circuit Resistor Buried Buried Sheet(ohms) Qty. (watts) Tolerance Style Priority Tolerance Application Configuration Layer Quantity Resistance
20 60 0.063 1% 0402 ?? s R A 6033 9 0.063 5% 0402 s R A 933 3 0.063 5% 0603 s R A 3
33.2 31 0.100 1% RM0705 s R A 3175 81 0.063 1% 0402 s R A 81
Total 184
1K 30 5% 16 pin QSOP gnd(D) A B 301K 56 0.100 1% RM0705 gnd(D) A B 562K 6 0.100 1% RM0705 gnd(D) R B 6
4.75K 1 0.100 1% RM0705 gnd(D) R B 14.7K 15 5% 16 pin QSOP gnd(D) R B 15
Total 108
1K 2 0.063 5% 0402 2.5 V C11K 1 0.100 1% RM0705 2.5 V C12K 50 5% 16 pin QSOP 2.5 V C12K 4 0.100 1% RM0705 2.5 V C1
3.3K 0.063 5% 0603 2.5 V C13.32K 0.100 1% RM0705 2.5 V C14.75K 0.100 1% RM0705 2.5 V C14.7K 5% 16 pin QSOP 2.5 V C110K 4 0.063 5% 0603 2.5 V C110K 12 0.100 1% RM0705 2.5 V C1
1K 0.063 5% 0402 3.3 V C21K 12 0.100 1% RM0705 3.3 V C22K 5% 16 pin QSOP 3.3 V C22K 17 0.100 1% RM0705 3.3 V C2
3.3K 0.063 5% 0603 3.3 V C23.32K 0.100 1% RM0705 3.3 V C24.75K 20 0.100 1% RM0705 3.3 V A C2 204.7K 45 5% 16 pin QSOP 3.3 V A C2 4510K 1 0.063 5% 0603 3.3 V C210K 52 0.100 1% RM0705 3.3 V C2
1K 0.063 5% 0402 5.0 V C31K 9 0.100 1% RM0705 5.0 V C32K 5% 16 pin QSOP 5.0 V C32K 0.100 1% RM0705 5.0 V C3
3.3K 96 0.063 5% 0603 5.0 V A C3 963.32K 5 0.100 1% RM0705 5.0 V A C3 54.75K 0.100 1% RM0705 5.0 V C34.7K 15 5% 16 pin QSOP 5.0 V A C3 1510K 0.063 5% 0603 5.0 V C310K 22 0.100 1% RM0705 5.0 V C3
Total 659 Total 181
Basic Circuit Design Buried R-EP Design
25-50 ohms-sq.
50K ohm-sq.
50K ohm-sq.
10K ohm- sq.
50K ohm-sq.
Buried Capacitance® Drivers
Decreased Plane Inductances & Improves Broad Band Impedance
Reduced Size or Increased Functionality at Same Size
Lower Assembly Costs & Higher Reliability
Fewer Components = Less Solder Joints
Active Component
Gnd
PwrI & Z C
No BC™
Active Device
Decoupling Capacitors
Active Device
Decoupling Capacitors
With BC™
Santa Clara Valley Chapter, CPMT Societywww.cpmt.org/scv/
February 8, 2006
Page 4
Buried Capacitance® Product Family
Plane C
apac
itance
pf/in2
(pf/cm
2 )
BC12, BC16, BC8, BC16T, BC12T are all trademarks of Oak Mitsui TechnologiesHK-04 is a trademark of DuPont Electronic Materials
1000 (155) BC24™ & ZBC1000™1.0 mil (25µ)1600 (233) BC16™0.6 mil (16 µ)
Santa Clara Valley Chapter, CPMT Societywww.cpmt.org/scv/
February 8, 2006
Page 7
PDS Capacitor Estimator Electrical Model
PDS Capacitor Estimator Features:- Inductance calculation based on PCB construction- Estimates amount of surface capacitance needed- Choose either Zbank or Zcarpet Impedance Model
Lvia inside
Lvia above
LZBC
L/Nvia above
L/Nvia inside
Ccap
Rcap
Lcap
F
S
P
S
S
P
PBCTM Core
BCTM CoreP
P
P
S
S
S
F
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛+++++= LLLN
LNRZ ZBCviaabovevaiabove
cap
cap
cap
capBank 22jω
jωωC1
Ncap
ZBank
Zbank Impedance Model
PDS Capacitor Estimator Physical Model
S2
Ground
Power
H1
D
H2
H3
S1
R2 R1
Physical Model Inputs• Information About Board Construction• Information About Cap Chip and IC Package Placement
Santa Clara Valley Chapter, CPMT Societywww.cpmt.org/scv/
Based on 1156 Pin BGA Array, 3.3 V Power Distribution, 603 Style Bypass Caps
Santa Clara Valley Chapter, CPMT Societywww.cpmt.org/scv/
February 8, 2006
Page 9
Capacitive Coupling Test Board
Capacitive Dielectric8 micron FaradFlex BC8TM
Other Dielectrics In Test- FaradFlex BC12TM- Screen Printed PTF
Capacitor Dimensions1) .020” x .020”2) .040” x .040”3) .080” x .080”4) .160” x .160”5) .020” x .040”6) .080” x .040”7) .160” x .040”8) .320” x .040”9) .040” x .020”
10) .040” x .080”11) .040” x .160”12) .040” x .320”13) .020” x .020”14) .080” x .080”15) .160” x .160”16) .320” x .320”17) .080” x .080” ½ stub18) .080” x .080” 2x stub19) .160” x .160” 3x stub20) .160” x .160” 4x stub
2.000”50 ohm
.006”
Measurement Setup
Bit Pattern Test for Circuits 1-4 Pattern a
.020” x .020”
.040” x .040”
.080” x .080”
.160” x .160”
Santa Clara Valley Chapter, CPMT Societywww.cpmt.org/scv/
February 8, 2006
Page 10
Bit Pattern Test for Circuits 3,17,18 Pattern a
.080” x .080” ½ Stub
.080” x .080”
.080” x .080” 2x Stub
Bit Pattern Test for Circuit 12 Pattern (a) & (b)
.040” x .320” Capacitor Bit Pattern (b)
.040” x .320” Capacitor Bit Pattern (a)
Santa Clara Valley Chapter, CPMT Societywww.cpmt.org/scv/
February 8, 2006
Page 11
Eye Diagrams for Circuit 12 Pattern (a) & (b)
3.125 Gb/s 6.25 Gb/s 12.5 Gb/s
3.125 Gb/s 6.25 Gb/s 12.5 Gb/s
25 Bit Pattern (a)
25 Bit Pattern (b)
Resistor Impedance Measure Test Board
Two Objectives of Resistor Impedance Measurements are;1. Characterize by Geometry2. Characterize by Board Construction and Application
1 2 3
45
6
Sheet Resistance = 100 ohm-sq.
PTF Film Thickness = 0.007”
Rectangular Resistor Parameters
210.040”.120”6 -
140.040”.080”5 -
70.040”.040”4 -
420.020”.120”3 -
290.020”.080”2 -
160.020”.040”1 -OhmsWidthLength
Annular Resistor Parameters
Sheet Resistance = 1000 ohm-sq.
PTF Film Thickness = 0.007”
70.035”.045”Ohms
Inner Diameter
Outer Diameter
Santa Clara Valley Chapter, CPMT Societywww.cpmt.org/scv/
February 8, 2006
Page 12
PTF Resistor Design
B
L
B
L
RR
ttRRR ⎟
⎠
⎞⎜⎝
⎛=×= ρρ
B
L
S RRRR= NRR S×=or
ρ = Resistivity (ohm-unit length)t = Resistor film thickness RL = Length in direction of current flowRB = WidthRs = Sheet resistance (Ω/ ) N = The number of series squares
⎟⎟⎠
⎞⎜⎜⎝
⎛=DD
tR1
2ln2πρ
R = Resistor value (ohms)ρ = Resistivity (ohm-unit length)t = Resistor average thickness D1 = Resistor inner pad diameterD2 = Resistor outer ring diameter
RL
RB
Ohms
Ohms
D1
D2
D1
D2
Z(resistive) Measurement Set Up
Port Connections to the Annular Resistor are Asymmetric
Port 1 Port 2
Port 1 Port 2
.032”
Measurement Setup for AnnualrAnd Rectangular Resistors
Port Connections to Rectangular Resistors
Santa Clara Valley Chapter, CPMT Societywww.cpmt.org/scv/
February 8, 2006
Page 13
S21 Measurements for Rectangular Resistors
• Impedance Predictable to 7 GHz• Z Response Above 7 GHz Not Well Understood