M-PHY®: A Versatile PHY for Mobile Devices Patrick Moné, Texas Instruments SAME 2012 Conference
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M-PHY®: A Versatile PHY for
Mobile Devices Patrick Moné, Texas Instruments
SAME 2012
Conference
Session Title P 2
MIPI High-Speed
interfaces in a
SmartPhone
D-PHY applications:
- Camera
- Display
M-PHY® applications:
- Camera
- Display (in future)
- Modem
- RFIC
- Memory (Jedec UFS)
- USB3 IC
- Extension chips Source: MIPI Alliance
Session Title P 3
M-PHY versus D-PHY D-PHY M-PHY
Minimum
configuration 4 wires (1 data + 1 clock) + CTRL 4 wires only (1 TX + 1 RX)
Physical Medium < 30 cm PCB, flex, micro-coax < 30 cm PCB, flex, micro-coax
>1.0m optical
Data-rate / lane
HS: 80 Mbps to 1.5 Gbps HS: 1.25/1.5, 2.5/3, 5/6 Gb/s
LP: < 10 Mbps PWM: 1 Mb/s to 576 Mb/s
SYS: 26, 38.4, 52 Mb/s
Signaling HS: SLVS-200 (Differential) HS: 100/200 mV (Differential)
LP: LVCMOS 1.2V (Single-ended) LS: 200/400 mV (Differential)
HS clocking Synchronous clock (DDR clock) Embedded clock
HS line encoding None (8b9b optional) 8b10b
RCV CDR No Yes
Low Power States LP / ULPS STALL / SLEEP / HIBERN8
EMI friendly NO YES
Configurability NO YES
Session Title P 4
M-PHY/D-PHY Clocking Schemes
DATA
TX
DATA
RX DATA INTERCONNECT
CLK
TX
CLK
RX CLK INTERCONNECT
DATA INTERCONNECT
CLK INTERCONNECT CLK
GEN
TX DATA RX DATA
RX CLK
D P H Y
DATA
TX
CLK
&
DATA
REC DATA INTERCONNECT
DATA INTERCONNECT
CLK
GEN
TX DATA
RX DATA
RX CLK
M P H Y
CLK
GEN
Synchronous clock
Embedded clock
Session Title P 5
M-PHY Philosophy
The PHY, TX and RX, are specified as separate entities
– Each implementer can tailor its M-PHY interface to fit its needs
The interface to the protocol is defined (informative
normative)
Flexibility through capability, configuration and status
registers
Optimized for chip to chip interconnect
2 types of architecture supported
2 types of cloking schemes
Low power
Low EMI
Session Title P 6
2 Types of Architecture
TYPE I
General
2 clocking schemes
PWM scheme for LS
No side band signals
Optical capabilities
UniproSM, LLI, SSIC
TYPE II
Short interconnect
Shared clocking
Synch. clock for LS
Side-band signal
No optical support
DigRF v4 protocol
Session Title P 7
Clocking Schemes
DATA
TX
CLK
&
DATA
REC DATA INTERCONNECT
DATA INTERCONNECT
PLL
Mult
TX DATA
RX DATA
RX CLK
PLL
Mult Separate clock
Xtal1 Xtal2
DATA
TX
CLK
&
DATA
REC DATA INTERCONNECT
DATA INTERCONNECT
PLL
Mult
TX DATA
RX DATA
RX CLK
PLL
Mult Shared clock
Xtal1
Session Title P 8
Capabilities and Configuration
At link start-up, the local and remote protocols will read
the capabilities of the remote M-PHY, and will configure their
own M-PHY to the common denominator
Source: MIPI Alliance
Session Title P 9
M-PHY Data-Rates
3 9 to G1
6 18 to G2
12 36 to G3
24 72 to G4
48 144 to G5
96 288 to G6
192 576 to G7
1
2
4
8
A
1
4
5
8
B
G1
2
4
9
6
A
2
9
1
6
B
G2
4
9
9
2
A
5
8
3
2
B
G3
Low-Speed Gears
- PWM signaling
High-Speed Gears
- NRZ signaling
Session Title P 10
M-PHY State Machine
Source: MIPI Alliance
Session Title P 11
Power Comparison
STATE Squelch PLL RX
Termina-
tion
RX/TX
ckt
Power Exit
Latency
HIBERNA
TE
ON OFF OFF OFF 10 μW ms
SLEEP OFF OFF OFF LDO 100 μW μs
PWM
BURST
OFF
OFF OFF/ON ALL
PWM
1 mW μs
STALL OFF ON OFF LDO 10 mW ns
HS BURST OFF ON ON/OFF ALL
HS
25 mW ns
Active powers given for PWM-G1 and HS-G1
Session Title P 12
Power Optimization vs Link Traffic
HS-BURST w/ FILLER
– PHY remains in BURST when no data
– Zero latency between frames
HS-BURST to STALL
– PHY goes to STALL to save some power
– Latency in the ns range
HS-BURST to SAVE
– PHY goes to SAVE to save more power
– Latency in the μs range
HS-BURST to HIBERNATE (H8)
– 0 mW idle power
– Latency in the 100 μs range
Source: MIPI Alliance
Session Title P 13
Asymmetric Links In some applications, the link datarate is not
symmetrical in both directions
Camera, Display, …
M-PHY allows to operate the link in High-Speed in one
direction, and in Low-Speed in the reverse direction
It could also allow to have one direction in idle mode
and the other in active mode
M-TX M-RX
M-RX M-TX
M-RX M-TX
M-RX M-TX
PWM-G5: 144 Mbps
HS-G2B: 2915 Mbps
24 Mpix
CAMERA
APPLICATION
PROCESSOR
Session Title P 14
Electro Magnetic Interference
Common-Mode Voltage CM Voltage PSD
MPHY
TX
LNA
CM PSD results from co-existence
analysis with the different radios
Session Title P 15
Conclusion
Thanks to its un-precedented flexibility, the M-PHY
interface is enjoying a wide adoption in the phone
industry
Due to the explosion of the mobile market (tablets,
electronic readers,…), it is now being used in other
fields of applications
Its future extension to higher data-rates (10 Gbps in
2013) should also enable new applications
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