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Lab 1
Time Domain Analysis Lab 1-1 Synopsys SaberRD Electrical
Workshop
During this lab, you will perform a time domain analysis on an
RLC filter to determine its transient response to a pulse
input.
After completing this lab, you should be able to:
Perform a time domain analysis Turn simulation data into useful
information by plotting
waveforms and applying measurements to them
Lab Duration: 15 minutes
Learning Objectives
1 Time Domain Analysis
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Lab 1
Lab 1-2 Time Domain Analysis Synopsys SaberRD Electrical
Workshop
Instructions
Task 1. Invoke SaberRD and Open the RLC Design
1. Open SaberRD by selecting Start>Programs>Synopsys>
SaberRD version>SaberRD
Note that SaberRD initially comes up with the Start Page that
provides easy access to things like Recent Designs, Design
Examples, Documentation, and Help resources.
2. Click the SaberRD button for access to the file menu. Choose:
Open > Open Design.
3. Navigate to the install directory for the labs and go to the
directory SaberRD_Training_Labs/Lab01. Open the file
ex_rlc.ai_dsn.
The RLC schematic appears:
Task 2. Run a Time-Domain Analysis
1. Switch to the Simulate tab for access to the simulation
controls.
2. If needed, change the simulation type to Transient
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Lab 1
Time Domain Analysis Lab 1-3 Synopsys SaberRD Electrical
Workshop
3. Fill in the other fields with the following values:
End = 10m # Run the simulation for 10ms
Step = 0.1u # Set the initial time step to 0.1us
The quick simulation bar should now look like this:
4. Hit the green go button.
Task 3. View the waveforms for vin and vout
When the simulation completes, youll notice that the window
where the Design Browser was on the left has now changed. You
should now see a Results window in its place. You can toggle which
one youre viewing with the tabs along the bottom of this pane. Lets
plot the signals of interest, the stimulus, vin, and the output,
vout.
1. In the Results pane, if needed click the plus sign next to
ex_rlc to expand all of the signals available for plotting.
2. Double-click on the signal vout to plot its waveform. 3.
Double-click on the signal vin to plot its waveform.
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Lab 1
Lab 1-4 Time Domain Analysis Synopsys SaberRD Electrical
Workshop
This will place the two signals in separate graphs. You can
combine them into the same graph for easier comparison.
4. In the graph window you will notice the signal vin label to
the right of the graph. Left-click on this signal and drag it down
to the graph area for the vout signal. This should sumperimpose the
two signals onto the same graph.
As can be seen, the filter is under-damped, and causes the
output signal to overshoot the input signal. Since overshoot in a
circuit can be a problem, use the Measure tool to find out how
large the overshoot is.
Task 4. Perform Measurement on vout
1. Switch to the Analyze tab to access the data analysis
controls. 2. In the graph window, select the vout signal.
3. Click on the apply measures button to bring up the
measurement tool.
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Lab 1
Time Domain Analysis Lab 1-5 Synopsys SaberRD Electrical
Workshop
4. In the measurement tool, left-click the button next to
Measurement and select: Time Domain > Overshoot from the drop
down menu.
5. Click Apply:
Question 1. What is the overshoot measurement on the vout
signal?
___________
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Lab 1
Lab 1-6 Time Domain Analysis Synopsys SaberRD Electrical
Workshop
Task 5. Add a Probe to View Results on the Schematic
Often it is useful to be able to view results right on the
schematic itself. SaberRD allows you to do this via Probes. You
will add a probe to view the results on vout in this task.
1. In the center/main window, toggle back to the schematic view
using the
tabs along the top of that area: 2. Select the wire/net which is
labeled vout. It should turn light green when
selected. 3. Keep your mouse overtop of the wire/net and right
click for the context-
sensitive pop-up menu and select Probe 4. If you need to zoom in
and out, you can do so via the zoom buttons
within the View tab, the Zoom controls in the bottom right
corner,
or you can hold down the Ctrl-key on the keyboard and use the
mouse scroll wheel to zoom in and out.
This additional method of results analysis allows us to probe
around a schematic and get a good feel for how a circuit is
behaving. You can probe other wires/nets in the schematic simply by
dragging the Probe arrow with your mouse and placing it on the
desired wire/net.
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Lab 1
Time Domain Analysis Lab 1-7 Synopsys SaberRD Electrical
Workshop
Task 6. Close out Lab #1
1. Access the file menu from the SaberRD button and select Close
> Close Design. It is not necessary to save the schematic.
2. Leave SaberRD open.
Please let your instructor know when you have completed this
lab.
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Lab 1
Lab 1-8 Time Domain Analysis Synopsys SaberRD Electrical
Workshop
Answers / Solutions
Task 3. Perform Measurement on vout
Question 1. overshoot = 0.262 V
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Lab 2
Finding Parts and Creating Schematics Lab 2-1 Synopsys SaberRD
Electrical Workshop
During this lab, you will finish a schematic of a differential
amplifier
After completing this lab, you should be able to:
Find parts in the SaberRD parts library Create schematics and
wire components together
Parameterize components to match your design needs
Lab Duration: 15 minutes
Learning Objectives
2 Finding Parts and Creating Schematics
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Lab 2
Lab 2-2 Finding Parts and Creating Schematics Synopsys SaberRD
Electrical Workshop
Background
Finding the models you need in order to complete simulation is
one of the key enablers to the vast benefits of simulation or
virtual prototyping. One of SaberRDs biggest advantages is its
flexibility for using, creating, and providing models. The library
of multi-domain behavioral models in SaberRD is one of the largest
in the industry. In later labs, you will look at ways for
reading-in existing models and intuitive ways to create models on
your own.
In this lab, you will concentrate on finding parts in the
SaberRD model library.
It is also important to note that models fall into two
classifications: generic models and components. A generic model
describes some behavior and must be parameterized by the user in
order to meet the desired specification (e.g. a linear resistor
requires the user to specify its resistance). A component
represents the behavior of a specific part and has been
characterized according to measurements or manufacturers data (e.g.
a 2N2222 bipolar transistor). The SaberRD library has thousands of
models in both classifications.
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Lab 2
Finding Parts and Creating Schematics Lab 2-3 Synopsys SaberRD
Electrical Workshop
Instructions
Task 1. Open the Design and Add Parts
1. Click the SaberRD button for access to the file menu and
choose: Open > Open Design.
2. Navigate to the directory SaberRD_Training_Labs/Lab02. Open
the file diffamp.ai_dsn.
An unfinished DiffAmp schematic appears:
You will be adding an op-amp, resistor, and ground in the area
highlighted to complete the schematic.
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Lab 2
Lab 2-4 Finding Parts and Creating Schematics Synopsys SaberRD
Electrical Workshop
3. Display the SaberRD Parts Library by selecting the Parts tab
in the bottom left corner of SaberRD.
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Lab 2
Finding Parts and Creating Schematics Lab 2-5 Synopsys SaberRD
Electrical Workshop
4. Add the required op-amp: a. At the top of the Parts pane,
select the Search tab. b. Select (click on) components. c. Fill in
the search box with lm324 and hit Enter.
d. Select from Available Parts: lm324_1 (lower in the list).
Double-click on this entry to Place the Part into the
schematic.
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Lab 2
Lab 2-6 Finding Parts and Creating Schematics Synopsys SaberRD
Electrical Workshop
e. Left-click/hold on the part and drag it into place as shown
in the zoomed-in picture below. SaberRD will complete the
connections for you.
5. Next, lets browse the library to find a resistor and wire it
into the schematic:
a. Hit the Browse tab at the top next to the Search tab to go
back to the browsing pane.
b. Make sure Generic Parts is selected (ie the radio button is
switched back to Generic Parts.)
c. Expand the Category Electronic. d. Expand the sub-category
Passive Elements.
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Lab 2
Finding Parts and Creating Schematics Lab 2-7 Synopsys SaberRD
Electrical Workshop
e. Scroll down to find the vertical Resistor (|)
f. Doubleclick the Resistor (|) part to place on schematic.
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Lab 2
Lab 2-8 Finding Parts and Creating Schematics Synopsys SaberRD
Electrical Workshop
g. Drag and drop it into place, approximately as shown
below.
h. Hover over the small box (port) that represents the +
terminal of the op-amp (inp) and when it highlights red, left-click
once to start a wire connection.
i. Drag to route the wire to the p port (top port) of the
resistor and click to complete the connectionSaberRD will
automatically take care of the bend required to complete the
route.
6. Finally lets add the ground. a. Return to the search tab. b.
Switch to Generic Parts tab, if needed, and
search using the term, ground. c. Select the item labelled
Ground and double-click
to place it in the schematic.
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Lab 2
Finding Parts and Creating Schematics Lab 2-9 Synopsys SaberRD
Electrical Workshop
d. Drag and drop the ground symbol such that the top of the
ground lines up and connects with the bottom of the resistor as
shown below.
e. Drag and drop the ground slightly lower in the schematic and
SaberRD will automatically fill in the wire/net to maintain the
connection.
Task 2. Parameterize the Components and Save
Now that these parts are in place, we need to fill in the proper
parameter values.
1. Parameterize the op-amp. a. Select the op-amp. It will
highlight green when
selected.
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Lab 2
Lab 2-10 Finding Parts and Creating Schematics Synopsys SaberRD
Electrical Workshop
b. Notice that the Property Editor pane on the right will switch
to displaying all of the properties of the lm324.
c. Change the reference designator, or ref property to a value
of u1.
d. In the Attributes Editor pane below, change the visibility of
the ref property to value. (This will display only the value of the
property and not both the property name and value).
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Lab 2
Finding Parts and Creating Schematics Lab 2-11 Synopsys SaberRD
Electrical Workshop
2. Repeat this process to parameterize the resistor.
ref = r2 # Reference designator r2
visibility = value
rnom = normal(10k,0.1) #10k resistor, +/- 10% visibiltiy =
value
The finished schematic should look like the following:
3. Save your completed schematic. You can either use the file
menu from the SaberRD button or use the Save icon right next to
it.
Task 3. Close out Lab #2
1. Close the design from the SaberRD button:
Close > Close Design 2. Leave SaberRD open.
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Lab 3
Small Signal AC Analysis Lab 3-1 Synopsys SaberRD Electrical
Workshop
During this lab, you will perform a small-signal frequency
analysis on the RLC filter to determine its gain as a function of
frequency.
After completing this lab, you should be able to:
Perform a small-signal frequency analysis
Perform frequency domain measurements on results Enable looping
to see the effect of sweeping a
parameter.
Lab Duration: 20 minutes
Learning Objectives
3 Small-Signal Frequency Analysis
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Lab 3
Lab 3-2 Small Signal AC Analysi Synopsys SaberRD Electrical
Workshop
Instructions
For this lab we will be using an RLC filter as before.
Note that as the labs progress, some of the instructions will
become abbreviated for instructions which have already been covered
more explicitly in previous labs.
Task 1. Perform Small-signal Frequency Analysis
1. Click the SaberRD button for access to the file menu. Choose:
Open > Open Design.
2. Navigate to the install directory for the labs and go to the
directory SaberRD_Training_Labs/Lab03. Open the file
ex_rlc.ai_dsn.
3. Switch to the Simulate tab for access to the simulation
controls.
4. Change the simulation type to Small-Signal Frequency
analysis. 5. Set the frequency range over which the circuit is to
be swept as
indicated below:
Begin = 1 # Start frequency
End = 100k # End frequency
The quick simulation bar should now look like this:
6. Click the green go button.
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Lab 3
Small Signal AC Analysis Lab 3-3 Synopsys SaberRD Electrical
Workshop
Task 2. Perform Measurement on vout
1. When the simulation completes, the results window will
display on the left side of SaberRD. If needed, expand the ex_rlc
hierarchy. Double click on the vout signal to plot it.
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Lab 3
Lab 3-4 Small Signal AC Analysi Synopsys SaberRD Electrical
Workshop
Next you will make a measurement. Suppose you were interested in
the bandwidth of the filter. A typical measurement of bandwidth for
a lowpass filter such as this would be a -3dB measurement. This
measurement indicates at what frequency the gain falls to -3dB (or
where the output voltage falls to 0.707 of the input voltage).
2. Switch to the Analyze tab to access the data analysis
controls.
3. In the graph window, select the dB(vout) signal.
4. Click on the apply measures button to bring up the
measurement tool.
5. Left-click the button next to Measurement and select
Frequency Domain > Lowpass (3dB Point)
6. Click Apply and then Close (or the x in the upper right
corner of the measurement window) to close the measurement
tool.
The measurement is applied in the waveform window.
Question 1. What is the -3dB bandwidth? _________________
7. Close this graph window by left-clicking the x in the right
corner of this pane:
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Lab 3
Small Signal AC Analysis Lab 3-5 Synopsys SaberRD Electrical
Workshop
Task 3. Examine the Effect of Varying the Capacitor
For this filter design, it would be useful to know how the -3dB
point changes with respect to the capacitance of c1. In this task,
you will sweep the value of capacitance, simulate the response, and
measure the -3dB point for each iteration.
1. Switch to the Simulate tab for access to the simulation
controls.
2. From the simualtion controls, change the Looping control
to
Parameter Sweep 3. Toward the right youll see the box labaled
Param. Click the
Browse button on the right side of the field that shows up with
three
dots: 4. This will bring up a list of all the parameters
available for sweeping.
Expand ex_rlc and then c.c1 by clicking on the +. Click on c to
select the value c for c.c1:
5. Click OK.
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Lab 3
Lab 3-6 Small Signal AC Analysi Synopsys SaberRD Electrical
Workshop
6. Fill in the details of the parameter sweep:
Start = 0.1u # Start at 0.1uF
End = 1u # End at 1uF
By = 0.1u # increment in even steps of 0.1uF
The quick simulation bar should now look like this:
7. Click the green go button.
8. When the results pane displays on the left, double-click on
vout again to plot it. This time you should see a multi-membered
waveform:
Now lets see more specifically how the changing capacitance
value affects the -3dB point for this design.
9. Switch to the Analyze tab to access the data analysis
controls.
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Lab 3
Small Signal AC Analysis Lab 3-7 Synopsys SaberRD Electrical
Workshop
10. In the graph window, select the dB(vout) signal.
11. Click on the apply measures button to bring up the
measurement tool.
12. Left-click the button next to Measurement and select
Frequency Domain > Lowpass (3dB Point)
13. Click Apply and then Close.
This time you get a new graph showing the multiple values of the
the -3dB point.
Question 2. How does increasing capacitance affect the -3dB
point of this filter?
_______________________________________________________
Task 4. Close out Lab #3
1. Close the design from the SaberRD button: Close > Close
Design
2. Leave SaberRD open.
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Lab 3
Lab 3-8 Small Signal AC Analysi Synopsys SaberRD Electrical
Workshop
Answers / Solutions
Task 4. Perform Measurement on vout
Question 1. The -3dB bandwidth is 1.47kHz.
Task 5. Examine the Effect of Varying the Capacitor
Question 2. Increasing the capacitance decreases the -3dB point
of the filter.
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Lab 4
Operating Point Analysis Lab 4-1 Synopsys SaberRD Electrical
Workshop
Operating Point Analysis
During this lab, you will gain some basic familiarity with an
Operating Point analysis.
After completing this lab, you should be able to:
Run an Operating Point analysis Interpret an Operating Point
report
Lab Duration: 15 minutes
Learning Objectives
4
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Lab 4
Lab 4-2 Operating Point Analysis Synopsys SaberRD Electrical
Workshop
Instructions
Your goal is:
Run an Operating Point analysis on a simple RLC circuit.
Make changes to the RLC circuit and see how that affects the
operating point.
Task 1. Invoke SaberRD and Open the RLC Design
1. Click the SaberRD button for access to the file menu. Choose:
Open > Open Design.
2. Navigate to the install directory for the labs and go to the
directory SaberRD_Training_Labs/Lab04. Open the file
ex_rlc.ai_dsn.
The RLC schematic appears:
This is a simple design but the Design Browser can be a very
useful tool for navigating through design hierarchy and selecting
and manipulating various parts of a design. The Design Browser is
located on the left-hand side of the SaberRD window.
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Lab 4
Operating Point Analysis Lab 4-3 Synopsys SaberRD Electrical
Workshop
3. Expand the ex_rlc design to list all of the components that
comprise it.
This provides a means of viewing all of the contents of a design
so it is good to become familiar with this feature.
Task 2. Perform an Operating Point Analysis
One of the goals of SaberRD is to make it quick and easy to go
from start to results.
And, one of the more basic but important analyses to run is an
Operating Point Analysis which provides an understanding of the
steady state or dc response of a design.
1. Switch to the Simulate tab for access to the simulation
controls.
2. Change the simulation type to Operating Point in the top-left
corner of the Simulate ribbon.
Well stick with the default settings for the Operating Point
analysis making the simulation run very straightforward.
3. Hit the green go button.
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Lab 4
Lab 4-4 Operating Point Analysis Synopsys SaberRD Electrical
Workshop
At this point, it is good to become familiar with the transcript
window at the bottom of SaberRD. You might even want to expand the
window so that you can see the progress of the underlying
simulation steps. If there are warning or error messages during the
simulation, this is also where they will be reported .
When the simulation completes, an Initial Point Report is
displayed.
Note that all of the displayed values are zero. To find out if
this is
correct, look at the initial value of the voltage source that
drives the
filter.
4. In the center/main window, toggle back to the schematic view
using
the tabs along the top of that area:
The schematic shows that the voltage source has an initial value
of 0 and a pulse value of 1. This means that the source will supply
zero volts at time = 0. So the results are correct.
To get non-zero values for a DC analysis, you can change the
initial value of the source. For example, you could change the
initial value to 1V, and the pulse value to 0V. This way, you
invert the previous waveform.
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Lab 4
Operating Point Analysis Lab 4-5 Synopsys SaberRD Electrical
Workshop
Task 3. Change Input Voltage and Re-run Analysis
Lets invert that pulse source such that its initial value is 1
to see how that affects our Operating Point analysis.
1. Change the initial value of the voltage source as described
below: a. Select the voltage source symbol in the schematic.
It should highlight green. b. In the properties pane on the
right of SaberRD, left
click in the area to the right of the initial property. Change
the value from 0 to 1.
c. Left click in the area to the right of the pulse property.
Change the value from 1 to 0.
The values of initial and pulse in the properties pane should
now look like this:
You should also notice that the values being displayed next to
the source in the schematic changed.
2. Re-run the analysis by hitting the green go button again. 3.
Look at the results in the new Initial Point Report.
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Lab 4
Lab 4-6 Operating Point Analysis Synopsys SaberRD Electrical
Workshop
Question 1. What is the new voltage on vout? _____________ Does
this value make sense to you? Why or why not?
Task 4. Close Out Lab #4
1. Access the file menu from the SaberRD button and select Close
> Close Design and when prompted, do NOT save the schematic.
2. Leave SaberRD open.
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Lab 4
Operating Point Analysis Lab 4-7 Synopsys SaberRD Electrical
Workshop
Answers / Solutions
Task 3. Change Input Voltage and Re-run Analysis
Question 1. vout = 0.9091 V
At its steady-state, the RLC circuit behaves as a simple
resistor voltage divider with the voltage at vout calculated
as:
=2
1 + 2 =
1
100+ 1 1 = 0.9091
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Lab 5
Operating Point with Looping Lab 5-1 Synopsys SaberRD Electrical
Workshop
In this lab exercise, you will perform a DC Sweep Analysis on a
Loudspeaker Design.
After completing this lab, you should be able to:
Run a DC Sweep to see the effect of sweeping a parameter across
a range.
Graph the dc transfer function of a design.
Lab Duration: 20 minutes
Learning Objectives
5 DC Sweep
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Lab 5
Lab 5-2 Operating Point with Looping Synopsys SaberRD Electrical
Workshop
Background
The goal of this exercise is to sweep the loudspeaker with a
variable-amplitude input voltage, record the displacement of the
speaker diaphragm, and plot this displacement as a function of the
input voltage. In other words, this will generate a transfer
function for the loudspeaker.
This is a great example of SaberRDs ability to handle multiple
physical domains in a single simulation. In this example, well have
an electrical input and a mechanical output, with a voice coil to
perform the work of converting the electrical energy into
mechanical energy.
You will not need to know this for the lab, but just for your
information, here are the straightforward equations underlying this
model of a voice coil in a behavioral language (openMAST). Even
without knowledge of this language, it is fairly evident how the
physics equations represent the behavior:
i(p->m) += i frc_N(pos1->pos2) += force i: v(p)-v(m) = r*i
+ d_by_dt(l*i) + v_bemf vel: vel = d_by_dt(posn)
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Lab 5
Operating Point with Looping Lab 5-3 Synopsys SaberRD Electrical
Workshop
Instructions
Task 1. Open the Loudspeaker Design and Perform
Operating Point Analysis
1. Click the SaberRD button for access to the file menu and
choose: Open > Open Design.
2. Navigate to the directory SaberRD_Training_Labs/Lab05. Open
the file ex_lspkr.ai_dsn.
The loudspeaker schematic will appear as shown:
3. Perform an Operating Point Analysis.
a. Switch to the Simulate tab for access to the simulation
controls.
b. Change the simulation type to Operating Point
in the top-left corner of the Simulate ribbon.
c. Hit the green go button.
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Lab 5
Lab 5-4 Operating Point with Looping Synopsys SaberRD Electrical
Workshop
You should see an Initial Point Report with the following
results:
Task 2. Find the Transfer Function
1. Switch back to the Simulate tab for access to the simulation
controls.
2. Change the simulation type to DC Sweep in the top-left corner
of the Simulate ribbon.
3. Toward the right youll see the box labeled Source Click
the
browse button on the right side of the field: 4. This will bring
up a list of the sources available for sweeping. Expand
the ex_lspkr entry. Select the entry v_pulse.vin:
5. Click OK.
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Lab 5
Operating Point with Looping Lab 5-5 Synopsys SaberRD Electrical
Workshop
6. Fill in the following values for the v_pulse.vin initial
value:
Start = -30 # Start at -30V
End = 30 # End at 30V
The quick simulation bar should now look like this:
7. Click the green go button on the quick simulation bar. 8.
When the results pane displays on the left double click on the
signal
diaphragm to display the result.
The resulting graph of the loudspeaker displacement gives you a
good idea of the transfer function of this design. It looks like
the position of the speaker diaphragm follows the input voltage
fairly well, although there appears to be some non-linearity which
could be investigated subsequently.
Question 1. How does the voltage affect the position of the
loudspeaker diaphragm?
Task 3. Close out Lab #5
1. Close the design from the SaberRD button:
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Lab 5
Lab 5-6 Operating Point with Looping Synopsys SaberRD Electrical
Workshop
Close > Close Design 2. Leave SaberRD open.
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Lab 5
Operating Point with Looping Lab 5-7 Synopsys SaberRD Electrical
Workshop
Answers / Solutions
Task 2. Change Input Voltage and Re-run Analysis
Question 1. The larger the magnitude of the voltage, the farther
the loud speaker diaphragm is from 0mm (the resting point).
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Lab 6
FFT Lab 6-1 Synopsys SaberRD Electrical Workshop
pl
FFT
In this lab exercise, you will perform a FFT analysis using the
Waveform Calculator and examine the results.
After completing this lab, you should be able to:
Use FFT in the Waveform Calculator
Lab Duration: 20 minutes
Learning Objectives
6
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Lab 6
Lab 6-2 FFT Synopsys SaberRD Electrical Workshop
Background
This lab is designed to illustrate the difference between a
Small-Signal AC analysis (which is run at an operating point, on a
linearized system), and an FFT, which can be used to show
non-linear effects in the frequency domain.
In this lab exercise you will first perform a Small-signal AC
analysis on the Loudspeaker portion of an Audio Test System. The
next step is to run a Transient analysis and then a Fast Fourier
Transform (FFT) analysis on the results from transient. You can
then compare the FFT results to the Small-signal AC analysis. The
observed difference could be assumed to be due to the
nonlinearities in the system. The final step is a verification
which requires removing the nonlinearities and then re-running the
analysis.
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Lab 6
FFT Lab 6-3 Synopsys SaberRD Electrical Workshop
Instructions
Task 1. Open the Loudspeaker Design
1. Click the SaberRD button for access to the file menu and
choose: Open > Open Design.
2. Navigate to the directory SaberRD_Training_Labs/Lab06. Open
the file ex_lspkr.ai_dsn.
The loadspeaker schematic will appear as shown.
Task 2. Add AC Parameters to the Source
The first analysis you will run will be a Small-Signal AC
analysis. To run this analysis, the input source must be defined
properly. You will do this in the following steps.
1. Select the voltage source v_pulse.vin.
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Lab 6
Lab 6-4 FFT Synopsys SaberRD Electrical Workshop
2. Change the property ac_mag from 1 to 2.
You are setting the amplitude of the AC source to 2 since you
are going to compare the results of this analysis to the FFT
results. In FFT, the results are displayed as the sum of positive
and negative frequency components. These components are equal for
physical systems which means the FFT results are twice the expected
single-sided values.
Task 3. Run Small-Signal AC Analysis
Run a Small-Signal AC analysis to observe the loudspeakers
behavior in the frequency domain.
1. Switch to the Simulate tab for access to the simulation
controls.
2. Change the simulation type to Small-Signal Frequency
analysis.
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Lab 6
FFT Lab 6-5 Synopsys SaberRD Electrical Workshop
3. Set the frequency range over which the circuit is to be swept
as indicated below:
Begin = 1 # Start frequency
End = 1k # End frequency
We are going to want to compare these results to the FFT
results. Therefore, we need to make the results align and will need
to change the number of points in the sweep range to 1024. You can
do this with the advanced controls.
4. You can do this by clicking on the Advanced controls tab in
the
Quick Simulation group:
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Lab 6
Lab 6-6 FFT Synopsys SaberRD Electrical Workshop
5. In the Advanced Simulation controls window, switch to the
Small Signal AC tab if needed and modify the Number of Points field
to 1024 as shown below:
6. Click close on this window and then click the green go
button. 7. Plot the signal diaphragm.
Task 4. Perform Time-Domain Analysis
You will next perform an FFT on time domain analysis results,
and compare these results to the Small-Signal Frequency Response
results you just generated.
1. Change the simulation type to Transient analysis.
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Lab 6
FFT Lab 6-7 Synopsys SaberRD Electrical Workshop
2. Fill in the fields with the following values:
End = 1 # Run for 1s
Step = 100n # Initial step 100n
We will also need to change one accuracy setting in the Advanced
Controls. We will be changing the Truncation Error.
Truncation Error = 10u # Increase accuracy
3. You can do this by clicking on the Advanced controls tab in
the
Quick Simulation group: 4. In the Advanced Simulation controls
window, switch to the Transient
if needed and modify the Truncation Error field to 10u as shown
below:
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Lab 6
Lab 6-8 FFT Synopsys SaberRD Electrical Workshop
Note: You might be wondering why we need to change the
truncation error. If all we were doing was looking at the waveforms
for the transient analysis, this would not be necessary. Changes to
the transient waveforms from this accuracy change would probably
not be perceptible. However, we will soon be making an FFT
transformation on this result. Keep in mind that this is numerical
simulation. Reducing the truncation error will tighten up the
accuracy of the transient simulation such that subsequent
transformations such as FFT are better as well.
5. Click Close on the Advanced Simulation controls tab and click
the green go button.
6. View the signals vin and diaphragm from the transient
analysis plot file. Note that the input signal is a 4KV pulse, and
the output shows a damped sinusoid.
Task 5. Perform FFT Analysis
Next you will perform a Fourier transform on the signals you
just observed.
1. Switch to the Analyze tab for access to the Waveform
Calculator.
2. Click on the Waveform Calculator button
3. Select the signal diaphragm and use the middle mouse button
to paste it into the Waveform Calculator. The Waveform Calculator
should appear as shown below.
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Lab 6
FFT Lab 6-9 Synopsys SaberRD Electrical Workshop
4. In the Waveform Calculator select Wave , then FFT. The form
to perform a fast fourier transform should appear.
5. Set Time Increment to log. The form should apprear as
below.
6. Click OK on the FFT form. The calculator should now show an
fft transform on the diaphragm signal.
7. Plot the results by clicking the Graph X icon 8. Observe the
resulting waveform. 9. Remove the transient versions of the vin and
diaphragm signals that
you plotted in Task 4. Left click to select them and then right
click to delete.
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Lab 6
Lab 6-10 FFT Synopsys SaberRD Electrical Workshop
Configure the X-axis to view from 10Hz to 1KHz.
10. At the bottom of the graph, select the x-axis as it
highlights red. The properties for the x-axis should now show on
the Properties pane. Change the minimum and maximum values as shown
below:
Note that it looks somewhat similar to the Small-Signal AC
response you ran previously, but the waveform is much less ideal.
This is due to the non-linear elements in the loudspeaker.
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Lab 6
FFT Lab 6-11 Synopsys SaberRD Electrical Workshop
Task 6. Linearize the System and Re-run Analysis
To verify that the differences in the frequency response curves
are due to loudspeaker nonlinearities, you will now remove the
nonlinearities from the loudspeaker and then re-run the FFT.
The models for the spring and the wind drag include coefficients
to represent non-linear behavior. Well set those to 0.
1. Return to the schematic window for the loudspeaker
design.
2. Select the spring symbol (spring_nl.susp). Change the
property k3 to 0.
3. Select the wind drag symbol (windrag.air). Change the
property w to 0.
4. Re-run the transient analysis as you did earlier (keep the
same settings).
Re-run the FFT analysis using the waveform calculator as you did
earlier.
5. Plot the signal diaphragm. 6. Bring up the waveform
calculator and delete the old entry by clicking
on the button.
7. Select the signal diaphragm and use the middle mouse button
to paste it into the Waveform Calculator. The Waveform Calculator
should appear as shown below.
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Lab 6
Lab 6-12 FFT Synopsys SaberRD Electrical Workshop
8. In the Waveform Calculator select Wave , then FFT. The form
to perform a fast fourier transform should appear. 9. Set Time
Increment to log. The form should apprear as below.
10. Click OK on the FFT form. The calculator should now show an
fft transform on the diaphragm signal.
11. Plot the results by clicking the Graph X icon 12. Observe
the resulting waveform.
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Lab 6
FFT Lab 6-13 Synopsys SaberRD Electrical Workshop
13. Remove the transient version of the diaphragm signal: left
click to select and then right click to delete.
14. Compare the results of this FFT analysis to the original
Small-Signal AC analysis. The waveforms should be nearly identical
(you may need to adjust the default Y-Axes to show how well they
match).
Task 7. Close out Lab #6
1. Close the design from the SaberRD button: Close > Close
Design
2. Leave SaberRD open.
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Lab 7
Mixed Signal Analysis Lab 7-1 Synopsys SaberRD Electrical
Workshop
In this lab exercise, you will run a simulation on a design with
both analog and digital components.
After completing this lab, you should be able to:
Plot signals from both the analog and digital domain.
Describe the concept of hypermodels and why they are needed in a
mixed-signal simulation environment.
Lab Duration: 10 minutes
Learning Objectives
7 Mixed-Signal Analysis
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Lab 7
Lab 7-2 Mixed Signal Analysis Synopsys SaberRD Electrical
Workshop
Background
This exercise will use the above circuit to show how SaberRD can
simulate a mixed-signal design. Digital parts include the 4-bit
counter in the middle of the schematic and the inverter on the
enable pin. Analog content makes up the rest of the circuit.
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Lab 7
Mixed Signal Analysis Lab 7-3 Synopsys SaberRD Electrical
Workshop
Instructions
Task 1. Run a Time domain Analysis
1. Click the SaberRD button for access to the file menu and
choose: Open > Open Design
2. Navigate to the directory SaberRD_Training_Labs/Lab07. Open
the file mm_lab.ai_dsn.
3. Run a time domain (Transient) analysis with the following
settings:
End = 32u # Run the simulation for 32us
Step = 1u # Set the initial time step to 1u
As usual, the Results pane will appear on the left when the
simulation completes. Notice that this time, it lists both analog
and digital signals for plotting.
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Lab 7
Lab 7-4 Mixed Signal Analysis Synopsys SaberRD Electrical
Workshop
4. Examine the digital signals under mm_lab. Note that some
digital nodes have been created that are not a part of the original
schematic, notably: d0_counter_q0 through d3_counter_q3.
5. Examine the analog signals under mm_lab. 6. Plot the analog
signal d0. 7. Plot the digital signal d0_counter_q0.
What you are seeing is that digital-to-analog hypermodels were
inserted under-the-hood in SaberRD to separate the digital pins
(d0-d3) and the analog resistors to which they connect. The nets on
the digital side of these hypermodels were renamed to
d0_counter_q0, d1_counter_q1, etc. The nets on the analog side of
the hypermodels kept the original net names (d0-d3).
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Lab 7
Mixed Signal Analysis Lab 7-5 Synopsys SaberRD Electrical
Workshop
8. Select and delete d0 from the graph, but keep signal
d0_counter_q0.
9. Plot the following signals: d1_counter_q1
d2_counter_q2 d3_counter_q3
clock
sumx2
clock_counter_clkup
10. Drag the signal sumx2 to on top of the clock signal. Your
Graph window should now look like this:
Note the step function shown by sumx2. Also note that when clock
spends too much time in the x region (>15ns between 1.8V and
3.2V) clock_counter_clkup = x. We will not do so here, but you
could further investigate and correct this design to eliminate this
issue.
11. Try zooming and measuring around in this window as you have
learned previously to gain an understanding of the signal
relationships.
Task 2. Close out Lab #7
1. Close the design from the SaberRD button: Close > Close
Design
2. Leave SaberRD open.
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Lab 8
Design Optimization Lab 8-1 Synopsys SaberRD Electrical
Workshop
In this lab, you will use design optimization to design a
bandpass filter
After completing this lab, you should be able to:
Find the stochastic parameters from a design Set up an
optimization task in the WCA tool
Define a target characteristic from a digitized plot Export the
results of an optimization back to the
simulator or schematic
If you are using the SaberRD Student Edition for the training,
skip this entire lab. Optimization is not enabled in the Student
Edition.
Lab Duration: 60 minutes
Learning Objectives
8 Design Optimization
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Lab 8
Lab 8-2 Design Optimization Synopsys SaberRD Electrical
Workshop
Background
This lab will demonstrate how the SaberRD WCA tool can be
applied to the synthesis of a band-pass filter. The L's and C's of
a passive network (12 parameters in all) are optimized so its
impedance matches a filter of passband [100Hz, 200Hz].
In particular, you will be shown how to extract the stochastic
parameters from a design, how to set up an optimization task in the
WCA tool, how to define a target characteristic from a digitized
plot, and how to export the results of an optimization back to the
simulator or schematic.
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Lab 8
Design Optimization Lab 8-3 Synopsys SaberRD Electrical
Workshop
Instructions
Task 1. Open the bandpass filter & WCA tool
1. Click the SaberRD button for access to the file menu and
choose: Open > Open Design.
2. Navigate to the directory SaberRD_Training_Labs/Lab08. Open
the file bandpass.ai_dsn.
3. The following schematic should appear, which represents a
bandpass filter:
The schematic "bandpass" shows the topology of the filter to
optimize.
The values of the capacitances and inductances are defined as
distribution functions in the "Saber Include" symbol instance (e.g.
uniform(0.1,0.01,0.5)).
These stochastic definitions are typically used for Monte Carlo
analyses.
Let's assume we want to reuse the same range as the Monte Carlo
distributions for our optimization task.
4. In the Analyze tab, click the Worst-Case Analysis icon to
open the WCA tool.
Task 2. Extract the stochastic parameters
The WCA tool allows you to extract the parameters defined in the
design with a stochastic distribution. This avoids duplicating the
effort of defining parameter variability information in the WCA
tool when this information is already defined in the design
schematic.
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Lab 8
Lab 8-4 Design Optimization Synopsys SaberRD Electrical
Workshop
1. In the WCA tool, click on the icon that looks like a die 2.
Click the button Extract and the WCA tool will automatically
identify the parameters which have tolerances associated. The
procedure takes around one minute to complete. A dozen parameters
get identified.
3. Click Append to add these parameters to the exisiting list of
parameters (in this case, it was empty).
The parameter table is now populated with the parameters current
values and domain information. You might want to expand the WCA
tool window to ensure that you can see the whole list of
parameters.
The capacitances have a current value of 10uF and are defined
over a continuous range between 1uF and 100uF.
The inductances have a current value of 0.1H and are defined
over a continuous range between 0.01H and 0.5H.
Note that the table allows parameters to be fixed to their
current values so they do not participate in a search (we will not
use this feature in this lab).
In this particular flat filter design, the stochastic parameters
happen to be defined in a top-level "Saber Include" instance. But
if you are dealing with a hierarchical design, nothing prevents you
from defining your parameter distributions at any
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Lab 8
Design Optimization Lab 8-5 Synopsys SaberRD Electrical
Workshop
level of the hierarchy (directly as model arguments or in a
"Saber Include"). The extraction procedure will work as well.
Task 3. Setup the optimization test
Now that we have defined the domain of the search, we need to
define the objective of the optimization. The goal is to minimize
the difference between the simulated Bode plot of the filter and a
target one.
The Bode plot of the impedance is obtained by running an ac
analysis and plotting the voltage at node "out".
1. Let's now define the simulation sequence. Add a dc analysis
first by clicking the menu item "Analyses" and then "DC Operating
Point".
2. Retain the default settings of the DC analysis. Click OK. 3.
In the same manner, add a Small Signal AC analysis. Set the
start
frequency to 20. Set the end frequency to 500. Click OK.
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Lab 8
Lab 8-6 Design Optimization Synopsys SaberRD Electrical
Workshop
The next step is to define the objective. The target waveform
needs to be made available to the WCA tool from a plotfile.
Assuming that the target characteristic is available as an image
from vendor datasheets or a lab instrument, the Scanned Data
Utility can be used to import the image, create digitized curves,
and export the curves into a plotfile.
A target characteristic defined in an ASCII file can also be
loaded in the Scanned Data Utility and exported the same way into a
plotfile. This step has been completed for you and a file named
target.ai_pl included in the lab directory. Here is what this would
look like in the Scanned Data Utility.
Let's now define a measure of waveform difference that
references the waveform in the plotfile target.ai_pl.
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Lab 8
Design Optimization Lab 8-7 Synopsys SaberRD Electrical
Workshop
4. Click New... in the Measures menu.
5. Set the name of the measure to "diff".
6. Set the Waveform to out" by browsing the signal hierarchy.
Click the down arrow to the right of the Waveform entry, select
Signals, expand bandpass and scroll down to select the signal out.
Click OK.
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Lab 8
Lab 8-8 Design Optimization Synopsys SaberRD Electrical
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7. Set Measurement to "Waveform Difference". 8. Set Plotfile to
"target.ai_pl" by using the file browser (select the
down arrow to the right of the Waveform entry and select
Browse...)
9. Enter "mag" as the target waveform. 10. Keep L1 as error
function and Y as the Direction.
11. Select "Magnitude" for the Y Transform option on the
Optional tab.
12. Click OK. You may have noticed that a selection of error
functions is available. For waveforms with a large dynamic range,
the logarithmic error functions are preferred. Please refer to the
WCA documentation for ampler information on the error
functions.
We set the Y transform option to "Magnitude" in order to compare
the magnitude of the complex waveform produced by simulation to the
real-valued target waveform.
Now that we have defined a measure "diff", the next step is to
define an objective seeking to minimize this measure. In other
words, we want to produce simulation results that match the target
waveform.
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Lab 8
Design Optimization Lab 8-9 Synopsys SaberRD Electrical
Workshop
13. Right mouse click the measure "diff" and click the menu item
Add Objective > Minimize
Allowed forms of objectives are: > min(expr1)
> max(expr1)
> expr1 = expr2
> expr1 > expr2
> expr1 < expr2
where expr1 and expr2 are algebraic expressions of measures
and/or parameter aliases.
The last step before running the optimizer is to define the
search algorithms. The search algorithms are evaluated
sequentially. Each algorithm takes the best point found by the
previous algorithm as starting point. The default algorithm
sequence consists of the following list:
1. Variable Neighborhood Search
2. Downhill Simplex
3. Steepest Descent
These are typically the most effective algorithms and the ones
used in this lab.
In order to increase the odds of finding the globally optimal
solution, the sequence of algorithms can be evaluated multiple
times.
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Lab 8
Lab 8-10 Design Optimization Synopsys SaberRD Electrical
Workshop
14. Set the number of iterations over the algorithm sequence is
set by clicking the Algorithms button and the Loops... menu
item.
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Lab 8
Design Optimization Lab 8-11 Synopsys SaberRD Electrical
Workshop
The default number of loops is 1.
15. Set the number of loops to 2 and click OK.
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Lab 8
Lab 8-12 Design Optimization Synopsys SaberRD Electrical
Workshop
Before we start the search, let's take a look at the progress
view (the graph in the bottom right corner). This view shows the
values of measures or parameters for the different evaluations of
the search.
16. Select "diff" from the signal menu.
We are now ready to run the optimizer.
17. Click the icon that looks like gears to start the search.
The active algorithm becomes highlighted.
The execution of the algorithm sequence will require thousands
of evaluations and should take between 5 to 20 minutes depending on
your computer performance.
You can interrupt the execution at any time by clicking the Stop
button, which will allow you to directly observe the results up to
that point.
You can re-click the Run button to start the next algorithm in
the sequence. It will take several thousand iterations to find the
optimal value but you can hit Stop when you are ready.
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Lab 8
Design Optimization Lab 8-13 Synopsys SaberRD Electrical
Workshop
This process will find the optimal values for the Ls and Cs in
the design to best match the bandpass filter response we targeted
with the scanned-in waveform.
This might be a good time to grab a cup of coffee to let the
optimizer complete all of the iterations.
When the optimization completes, you should see values chosen to
best match the desired bandpass which look similar to the
following:
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Lab 8
Lab 8-14 Design Optimization Synopsys SaberRD Electrical
Workshop
Task 4. Use the results of optimization
So, how do we use this information? There are many things that
we could do subsequently. We could re-run simulations with the new
optimal values or create a new schematic with the optimal values
and save that for printing or subsequent use. Suppose that we now
wanted to check how well we did with our optimization.
1. From the File > Export > Parameters... menu item..
Choose New Schematic and click OK.
2. Save the new schematic with a different name such as
optimized_bandpass
3. You can close the optimizer now to be able to view the new
schematic better.
Notice that the new optimized values are now annotated to the
schematic.
4. Run a Small-Signal Frequency analysis between 20 and 500
Hz.
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Lab 8
Design Optimization Lab 8-15 Synopsys SaberRD Electrical
Workshop
5. Plot the signal out and use the waveform calculator to take
the absolute value of db(out) and re-plot that signal.
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Lab 8
Lab 8-16 Design Optimization Synopsys SaberRD Electrical
Workshop
You should see a filter response that is a bandpass filter which
approaches the scanned-in image to which we were optimizing.
There is additional optimization refinement that we could do to
get our results to match the desired bandpass result even better.
This is beyond the scope of this class. However, if you would like
to do this on your own, the exercise is included as a tutorial in
the WCA tool. In the WCA tool, simply click on the menu item
Help > Tutorials > Filter Synthesis to complete this
refinement on your own.
Task 5. Close out Lab #8
1. Close the design from the SaberRD button: Close > Close
Design
2. Since this is the last lab of the day, close SaberRD.
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Lab 9
Design Optimization Lab 9-1 Synopsys SaberRD Electrical
Workshop
In this lab exercise, you will create a hierarchical model and
then encrypt it.
After completing this lab, you should be able to:
Find parts using Parametric Search. Automatically create a
symbol from a hierarchical
schematic.
Instantiate a custom created model. Encrypt a model.
Lab Duration: 60 minutes
Learning Objectives
9 Modeling: Hierarchical Models & Encryption
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Lab 9
Lab 9-2 Design Optimization Synopsys SaberRD Electrical
Workshop
Background
It is common in the design flow that you would want to make use
of one design simulation as part of a higher level. This
hierarchical approach to modeling is very straightforward to
accomplish in SaberRD.
Further, it is often common to want to share a model with a
customer or partner, without exposing the Intellectual Property
(IP) contained within. This is also straightforward to accomplish
in SaberRD and the benefits of using simulation models as the
supply chain communication mechanism can be tremendous.
In this lab, we will also get to take advantage of SaberRDs
Parametric Search feature.
Here is a summary of the steps that we will follow in the lab in
order to create this hierarchical model:
1. Create the sub-circuit that we wish to use as the model. 2.
Add hierarchical ports to the sub-circuit schematic that represent
the
pins of the device that we want to simulate. 3. Use SaberRDs
automatic symbol creation feature to create a symbol
from a schematic. 4. Test the new model by instantiating it in a
test circuit. 5. Encrypt the model.
a. Cut-and-paste the text netlist for the sub-circuit into a new
file.
b. Run SaberRDs encryption tool to automatically encrypt the
model.
c. Edit the symbol to refer to the encrypted text model rather
than the hierarchical schematic.
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Lab 9
Design Optimization Lab 9-3 Synopsys SaberRD Electrical
Workshop
Instructions
Task 1. Open the Sub-Circuit
1. Open SaberRD by selecting Start>Programs>Synopsys>
SaberRD version>SaberRD
2. Click the SaberRD button for access to the file menu and
choose: Open > Open Design.
3. Navigate to the directory SaberRD_Training_Labs/Lab09. Open
the file pwramp.ai_dsn.
The following schematic should appear, which represents our
power amplifier, but with a missing component, a BJT.
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Lab 9
Lab 9-4 Design Optimization Synopsys SaberRD Electrical
Workshop
In addition to the Parts Gallery search capability weve looked
at previously, the parametric search capability can be a powerful
tool for finding the parts in SaberRDs library that you need.
4. Switch to the Model tab . 5. Select the radio button for
Components. 6. Select the button marked Parametric Search.
7. When the Parametric Search Wizard appears, select the
category, BJT:
and click Next >
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Lab 9
Design Optimization Lab 9-5 Synopsys SaberRD Electrical
Workshop
8. Select the tab for Maximum Ratings, change two of the search
criteria from >= to = using the drop down arrow to the right as
shown below, and fill in the following values
Max Ic = 5 # Maximum collector current
Max Vce = 50 # Maximum collector-emitter voltage
and click Finish.
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Lab 9
Lab 9-6 Design Optimization Synopsys SaberRD Electrical
Workshop
9. When the list of Parametric Search results gets displayed,
scroll down and select the q2n718a
10. Select Place and then Close the Parametric Search
wizard.
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Lab 9
Design Optimization Lab 9-7 Synopsys SaberRD Electrical
Workshop
11. Select and move the q2n718a into place such that the
connections are automatically completed.
Task 2. Add hierarchical ports to the sub-circuit
1. In the Parts Search form, under the Model tab, in the top
left corner of SaberRD, switch the radio button back to Generic
Parts and type in the partial word hier and click on the binocular
icon to search:
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Lab 9
Lab 9-8 Design Optimization Synopsys SaberRD Electrical
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This will help find all of the hierarchical ports in the
library. Since the pins on this device are directionless or
conserved, we want the analog pin.
2. Select and hold the one labeled, Hierarchical Analog and
drag-and-drop it on top of the circle for the vsrc net as
shown:
3. Repeat this process for the vload net in the upper right
corner of the schematic.
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Lab 9
Design Optimization Lab 9-9 Synopsys SaberRD Electrical
Workshop
4. Save your completed schematic.
Task 3. Automatically create a symbol from schematic
1. Right-click somewhere blank in the schematic canvas and from
the context-sensitive menu that pops up choose: Create >
Hierarchical Symbol
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Lab 9
Lab 9-10 Design Optimization Synopsys SaberRD Electrical
Workshop
2. The symbol editor will open and the Symbol Editor Assistant
will display. In the Symbol Editor Assistant window, drag-and-drop
the vload pin to the right side of the symbol:
3. Click Save (use the default name, pwramp and file extension,
ai_sym) then Close
4. If needed, also close the SaberRD Symbol Editor Assistant
window.
Task 4. Test the new model in a test circuit
1. Click the SaberRD button for access to the file menu and
choose: Open > Open Design.
2. Navigate to the directory SaberRD_Training_Labs/Lab09. Open
the file test_pwramp.ai_dsn. Be sure to open the one with test_ in
the front of it.
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Lab 9
Design Optimization Lab 9-11 Synopsys SaberRD Electrical
Workshop
The following schematic for testing our power amplifier should
appear:
3. To instantiate our new model, right-click somewhere blank in
the schematic canvas, and from the context-sensitive menu choose:
Get Part > By Symbol Name
4. When the form pops up, choose Browse. 5. Select the symbol
pwramp.ai_sym. 6. Choose Place from the Get and Place Symbol By
Name form:
and then Close the Get and Place Symbol By Name form.
7. Move the symbol into place and complete the connections.
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Lab 9
Lab 9-12 Design Optimization Synopsys SaberRD Electrical
Workshop
8. Run a Transient Analysis with the following settings:
End = 50m # End time 50ms
Step = 1u # Set the initial time step to 1us
No Looping
9. Plot the vsrc and vload signals on top of one another. You
should see the following results:
Task 5. Encrypt the model
If you are using the Student/Demo Edition of SaberRD, skip this
Encryption part of the lab (Task 5 and Task 6). Encryption is not
enabled in the non-commercial version of SaberRD.
5.1. Cut-and-paste the sub-circuit netlist
1. Open a Notepad (or other) text editor. Start Menu >
Accessories > Notepad
2. Navigate to the directory SaberRD_Training_Labs/Lab09. Open
the file test_pwramp.sin. You might need to change the file
browsers Files of Type to All Files to see test_pwramp.sin.
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Lab 9
Design Optimization Lab 9-13 Synopsys SaberRD Electrical
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3. If youre using Notepad, turn on Word Wrap: Format > Word
Wrap
4. Resize (probably shrink) the window to make the text file
readable. 5. Highlight the text which contains the Intermediate
Template pwramp:
6. Copy this section of the netlist Edit > Copy
7. Open a new File File > New
8. Paste the Intermediate Template pwramp code. 9. Save the file
and give it the name pwramp.sin.
Be sure to change Notepads Save as Type box to all files such
that this file does not end up with an extra .txt extension.
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Lab 9-14 Design Optimization Synopsys SaberRD Electrical
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10. Close Notepad.
5.2. Run SaberRDs Encryption Tool
Next, we will prepare the pwramp.sin file that we just created
for encryption. In the process outlined below, you will add
encryption instructions into the code and then the Encryption Tool
will automatically encrypt your file for you.
1. Back in SaberRD, switch to the Model tab and select SaberRDs
Encryption Tool in the bottom right of the Modeling Tools
palette.
2. In the Saber Encryption Tool, choose the menu: File > Open
And open the file that you just saved: pwramp.sin
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Lab 9
Design Optimization Lab 9-15 Synopsys SaberRD Electrical
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3. Select the green circle for Encryption Start This will give
you a new cursor in the form of an arrow that will insert the
beginning of where you want encryption to start.
4. Click when the arrow is just below the line that reads
encrypted template pwramp vsrc:vsrc vload:vload
This will automatically insert two lines of directives for the
Encryption Tool as shown below:
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Lab 9
Lab 9-16 Design Optimization Synopsys SaberRD Electrical
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5. Select the red circle for encryption end. 6. Click when the
arrow is at the very end of the file after the last brace.
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Lab 9
Design Optimization Lab 9-17 Synopsys SaberRD Electrical
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7. Select the Encrypt icon which looks like a lock. 8. The
Encryption Tool will ask you to backup your original source
code. Save a backup of your original as pwramp.bak.
Your file is now encrypted and has been re-saved as pwramp.sin.
It should now look like an encrypted file.
9. Close the Saber Encryption Tool.
5.3. Modify the symbol to point to the encrypted model
1. In the test_pwramp schematic, right-click on top of the
pwramp symbol and in the context-sensitive menu, select Symbol
Editor.
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Lab 9
Lab 9-18 Design Optimization Synopsys SaberRD Electrical
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2. In the Properties pane on the right, select the schematic
property:
3. Just above that in the Properties pane, click on the red xxxx
to delete the
schematic property.
4. Click on the + sign next to that to add a new property.
5. Fill in the form with the values primitive and pwramp as
shown:
and click OK.
This will mean that the pwramp symbol will no longer use the
schematic model, but rather will use the encrypted model that you
created.
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Lab 9
Design Optimization Lab 9-19 Synopsys SaberRD Electrical
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6. In the Attributes pane in the lower right corner, change the
visibility of this new property to just show the value:
7. Next to the SaberRD button, click the Save Active icon to
save the new symbol.
8. Close the symbol schematic or simply go back to the
test_pwramp schematic window using the tabs in the middle pane.
9. Select the pwramp symbol and notice in the Properties pane
that the symbol has been automatically updated such that the
schematic property is no longer there but the primitive property
is.
10. Right click on the pwramp symbol and from the
context-senstive menu select View Model.
11. Notice that the model displays as encrypted and then close
this model viewer.
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Lab 9
Lab 9-20 Design Optimization Synopsys SaberRD Electrical
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Task 6. Re-run the simulation and check results
1. Re-run a transient simulation with the same settings as
before (they should still be entered in the Quick Simulation
bar).
2. Plot the signals vsrc and vload on top of one another again
and you should see the same results as when you used the schematic
version of the model.
Task 7. Close out Lab #9
3. Close the design from the SaberRD button: Close > Close
Design
4. Leave SaberRD open.
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Lab 10
Modeling: Table Look Up (TLU) Lab 10-1 Synopsys SaberRD
Electrical Workshop
In this lab exercise, you will import a Spice model and place it
in a blank schematic.
After completing this lab, you should be able to:
Import a Spice model for use in subsequent SaberRD
simulations.
Compile a user library.
Lab Duration: 10 minutes
Learning Objectives
10 Modeling: Import Spice Model
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Lab 10
Lab 10-2 Modeling: Table Look Up Synopsys SaberRD Electrical
Workshop
Background
In cases where you cannot find a model you need in the SaberRD
parts library, there are still many options for getting what you
need to complete your analysis. One place to look is on the web.
Some manufacturers provide Saber models. Some provide Spice models.
In this lab, we will walk through the process for how to take
advantage of a Spice model in SaberRD.
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Lab 10
Modeling: Table Look Up (TLU) Lab 10-3 Synopsys SaberRD
Electrical Workshop
Instructions
Task 1. Open the Design and Delete the Existing
OpAmp
1. Click the SaberRD button for access to the file menu and
choose: Open > Open Design.
2. Navigate to the directory SaberRD_Training_Labs/Lab10. Open
the file diffamp.ai_dsn.
3. Select the lm324 part in the design. Right click for a
context-sensitive menu and delete this part.
The schematic should now look like the following:
Task 2. Import the Spice model
1. Display the SaberRD Parts Library by selecting the Parts tab
in the bottom left corner of SaberRD.
2. Select the Browse tab. Notice toward the top of the Parts
Library the entry labeled, ai_User_Library. This is a
user-customizable entry for storing and using your own local
models.
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Lab 10
Lab 10-4 Modeling: Table Look Up Synopsys SaberRD Electrical
Workshop
3. Hover your mouse over ai_User_Library and right-click:
4. When the context-sensitive menu appears, choose Import
Spice
5. Navigate to the directory: SaberRD_Training_Labs/Lab10. Open
the file lm324_ns.mod
This is a Spice model provided by the manufacturer.
6. If prompted about copying files to the library, select
Yes.
This should bring up the Spice Wizard. SaberRD has started
importing the model and even helps you automatically create a
symbol for it. Since this is an OpAmp, lets change the symbol type
accordingly.
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Lab 10
Modeling: Table Look Up (TLU) Lab 10-5 Synopsys SaberRD
Electrical Workshop
7. In the Spice Wizard, toward the right side, select the
drop-down menu
next to Shape: 8. Choose OpAmp from the drop-down menu.
Unfortunately, the pins do not show up in the correct locations
for this model. Here is an excerpt from the source Spice model:
*//////////////////////////////////////////////////////////
*LM324 Low Power Quad OPERATIONAL AMPLIFIER MACRO-MODEL
*////////////////////////////////////////////////////////// *
* connections: non-inverting input * | inverting input * | |
positive power supply * | | | negative power supply * | | | |
output * | | | | | * | | | | | .SUBCKT LM324_NS 1 2 99 50 28
9. Select the yellow shaded boxes that get displayed as the pin
ports and drag and drop them into the correct locations. Your
symbol for the OpAmp should wind up looking like the following:
10. Click Finish. Notice that this part now shows up in your
user library. Notice that the small symbol associated with the user
library has turned red. This indicates that the
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Lab 10
Lab 10-6 Modeling: Table Look Up Synopsys SaberRD Electrical
Workshop
library has new information in it and needs compiled in order to
be ready for usage. This is a simple step.
11. Hover the mouse over the ai_User_Library in the Parts pane
again:
12. Right-click to get the context-sensitive menu and choose
Compile Library
13. When the Compile Library form appears, click OK.
14. When the Library Compile Complete prompt appears, click
Close. Notice that the red indicator on the ai_User_Library has
changed color to show that it is ready for use.
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Lab 10
Modeling: Table Look Up (TLU) Lab 10-7 Synopsys SaberRD
Electrical Workshop
15. Select the plus sign by the library to expand it and view
your new part. Click and hold on the lm324_ns part and drag and
drop it into place so that all of the pins get connected
automatically.
This section of the schematic should now look like this:
Task 3. Test the New Model
If you are using the SaberRD Student Edition, skip Task 3. This
model exceeds the node limits of the Student Edition.
1. Run a transient simulation with the following settings:
End = 10m # Run the simulation for 10ms
Step = 1u # Set the initial time step to 1u
No Looping
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Lab 10
Lab 10-8 Modeling: Table Look Up Synopsys SaberRD Electrical
Workshop
2. When the results pop up in the Results pane on the left, plot
the signal out1.
You should see a response on out1 like the following:
You have successfully imported a Spice model for subsequent use
in any of your SaberRD designs.
Task 4. Close out Lab #10
1. Close the design from the SaberRD button: Close > Close
Design
2. Leave SaberRD open.
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Lab 11
Modeling: Table Look Up (TLU) Lab 11-1 Synopsys SaberRD
Electrical Workshop
In this lab exercise, you will create a model using SaberRDs
Table Look Up (TLU) tool.
After completing this lab, you should be able to:
Create a model from a data sheet.
Use the Waveform Calculator and other SaberRD features to
validate its operation.
Lab Duration: 30 minutes
Learning Objectives
11 Modeling: Table Look Up (TLU)
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Lab 11
Lab 11-2 Modeling: Table Look Up Synopsys SaberRD Electrical
Workshop
Background
The data in the graph below was provided by Keystone Carbon Co.
for their thermistor 060412-103.5-46-C.
From this datasheet information, we were able to create a text
file shown below the graph. The independent variable data (X axis)
goes on the left (limited to 5 columns) and dependent variable data
(Y axis) goes on the right (limited to one column). Our example has
only one input (the thermal connection) so we have only one column
of X axis data. We saved the file with the extension .ai_dat.
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Lab 11
Modeling: Table Look Up (TLU) Lab 11-3 Synopsys SaberRD
Electrical Workshop
Instructions
Task 1. Open the Design and the TLU Tool
1. Click the SaberRD button for access to the file menu and
choose: Open > Open Design.
2. Navigate to the directory SaberRD_Training_Labs/Lab11. Open
the file Thermistor_ex_TLU.ai_dsn.
3. Switch to the Model tab to access the Modeling Tools. 4.
Hover your mouse over each of the icons in the Modeling Tools
palette and read through the tool tip that pops up with each
such that you have a feel for each of the tools which is available
in SaberRD.
5. Left-click on the Table Look Up tool.
The Table Look Up (TLU) Modeling tool will appear.
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Lab 11
Lab 11-4 Modeling: Table Look Up Synopsys SaberRD Electrical
Workshop
Task 2. Create the TLU Model
1. From the TLU Modeling tool, choose: File > New
2. As you recall from the Background section above, we have an
ASCII data file with our table. So, when it prompts you to select a
mode of data points input, select ASCII data file and click Ok.
3. If youre not already there, navigate to the directory
SaberRD_Training_Labs/Lab11. Open the file
keystone_060412_103_5_46_C.ai_dat.
Note that the data from our datafile is propagated into the TLU
Modeling tool.
4. In the TLU Modeling Tool, choose the menu: Properties >
Interface Setup
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Lab 11
Modeling: Table Look Up (TLU) Lab 11-5 Synopsys SaberRD
Electrical Workshop
This opens the Interface Setup window. The default connection
type is Control. Control means that it is a numerical value that is
non-conserved (vs. an electrical value, for example, which does
follow conservation of energy). With our thermistor, we would like
a temperature input and a resistance output.
5. Click on the arrow to the right of the Type field in the
Interface Setup windows to
choose these options.
Variable Type
x Thermal > temperature
y Electrical > resistance
Your Interface Setup should now look like this:
6. Click OK.
Note that the symbol and the axes on the models characteristic
curve for the thermistor changes to reflect our new choice of
connection types. Previously, it was somewhat meaningless data, now
it reflects a temperature input and a resistance output.
7. Save your new thermistor model by choosing the menu: File
> Save and name it keystone_thermistor. It is best to save the
model in the same location as the datafile.
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Lab 11
Lab 11-6 Modeling: Table Look Up Synopsys SaberRD Electrical
Workshop
8. In the TLU Modeling tool, left-click on the button place part
to place the part you just created into the thermistor test
circuit.
9. Close the TLU Modeling tool so that you can view the whole
schematic.
10. Move the new thermistor model into place in the middle of
the schematic so that the connections get automatically
completed.
11. Change the ref value of the thermistor to
keystone_thermistor1:
12. Save the schematic.
Task 3. Simulate the Test Circuit
1. Switch to the Simulate tab for access to the simulation
controls.
2. Run an Operating Point analysis:
Next, we will run a DC Parameter Sweep.
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Lab 11
Modeling: Table Look Up (TLU) Lab 11-7 Synopsys SaberRD
Electrical Workshop
3. From the simualtion controls, change the simulation type to
DC
Sweep 4. Toward the right youll see the box labeled Source Click
the
Browse button on the right of the field: 5. This will bring up a
list of the sources available for sweeping. Expand
the Thermistor_ex_TLU and select the t_dc.amb_temp entry.
6. Click OK.
7. Fill in the following values for the v_pulse.vin initial
value:
Start = -40 # Start at -40C
End = 85 # End at 85C
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Lab 11
Lab 11-8 Modeling: Table Look Up Synopsys SaberRD Electrical
Workshop
The quick simulation bar should now look like this:
Before hitting the go button, there is one more thing to note.
In checking the validity of the model that we created, we will want
to compare the output of the model with the data that we used to
create it. We can do this by measuring the resistance on the
output. This will be simple to find using the Waveform Calculator
by dividing the output voltage by the output current.
By default, and to improve simulation performance, SaberRD only
saves waveforms for across variables such as voltage. We will need
a through variable, that is, the current. This is easy to configure
in the advanced settings for the DC Sweep.
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Lab 11
Modeling: Table Look Up (TLU) Lab 11-9 Synopsys SaberRD
Electrical Workshop
8. In the bottom right-corner of the Quick Simulation bar,
left-click the icon to display the Advanced Simulation
controls.
9. If needed, select the tab for DC Sweep 10. Change the Signal
List to All Signals which will leave the Advanced
Simulation controls looking like the following:
Signal list options are explained in the table below.
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Lab 11
Lab 11-10 Modeling: Table Look Up Synopsys SaberRD Electrical
Workshop
Signal List Options
Description Syntax
All Toplevel Signals
Includes all signals which are part of the top level design. The
top level design corresponds to the highest level of the current
schematic.
:*:*
All Signals
Includes all signals at all levels of design hierarchy.
:...:*
Browse Design
Opens access to a design hierarchy browser to enable selecting
desired circuit signals.
-NA-
Choose the desired signal(s) from the Design Hierarchy box (LHS)
and add them to the Selected box (RHS)
11. Click the Close button on the Advanced Simulation controls
window.
12. Click the green go button in the Quick Simulation bar.
Task 4. Compare Waveforms to Check Model
1. When the results pane displays on the left, expand
short.short_tlu.
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Lab 11
Modeling: Table Look Up (TLU) Lab 11-11 Synopsys SaberRD
Electrical Workshop
2. Double click on the signal i for short.short_tlu to plot the
current.
3. Double click on the signal vout_tlu to plot the voltage.
4. Switch to the Analyze tab to access the data analysis
controls.
5. Click on the Waveform Calculator button to display the
Waveform Calculator tool. Click the Stack button and select
Clear All if needed.
6. Select the signal vout_tlu in the Graph window. 7. Use the
middle mouse button to paste the signal vout_tlu into the
entry line/box in the Waveform Calculator as shown below.
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Lab 11
Lab 11-12 Modeling: Table Look Up Synopsys SaberRD Electrical
Workshop
8. Next, select the signal i in the Graph window. 9. Use the
middle mouse button to paste i into the entry line/box in the
Waveform Calculator as shown below.
10. Divide these two signals by selecting the divide key on your
keyboard or by left-clicking on the divide key in the
calculator.
11. Plot the resulting signal using the Graph X button on the
Waveform Calculator and then close the Waveform Calculator.
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Lab 11
Modeling: Table Look Up (TLU) Lab 11-13 Synopsys SaberRD
Electrical Workshop
You should now see a waveform for the transfer function of the
thermistor model.
Delete the vout_tlu and i waveforms by selecting them in the
Graph window, right-clicking, and choosing Delete. You should be
left with just the waveform for vout_tlu/i.
Question 1. What does this graph of vout_tlu/i represent, i.e.
what is the x-axis and what is the y-axis?
_______________________________________________
_______________________________________________
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Lab 11
Lab 11-14 Modeling: Table Look Up Synopsys SaberRD Electrical
Workshop
Now lets compare this to our original data. SaberRD can read in
and plot many waveform formats, the most simple of which is just a
table of ASCII text like our original input file. Lets load this
waveform and compare it to our models response.
12. In the Analyze tab, click the button for Open Results. 13.
Open the file keystone_thermistor.txt 14. Plot the signal Y2 and
compare it to (vout_tlu/i). You might
want to drag and drop this signal into the region of
(vout_tlu/i) such that they are in the same graph.
You should see that they perfectly match. We can conclude that
our model works as expected.
Task 5. Close out Lab #11
1. Close the design from the SaberRD button: Close > Close
Design
2. Leave SaberRD open.
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Lab 11
Modeling: Table Look Up (TLU) Lab 11-15 Synopsys SaberRD
Electrical Workshop
Answers / Solutions
Task 6. Compare Waveforms to Check Model
Question 1. This waveform represents the change in resistance
vs. change in temperature (just like our original input data from
the manufacturer).
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Lab 12
Modeling: StateAMS Lab 12-1 Synopsys SaberRD Electrical
Workshop
In this lab exercise, you will create a model of a comparator
using SaberRDs StateAMS tool.
After completing this lab, you should be able to:
Create a behavioral model with StateAMS.
Lab Duration: 30 minutes
Learning Objectives
12Modeling: StateAMS
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Lab 12
Lab 12-2 Modeling: StateAMS Synopsys SaberRD Electrical
Workshop
Background
Saber has many flexible options for getting the models that you
need. One of the most powerful options is the StateAMS tool. Dont
let the State in the name fool you, this tool can be used to create
a model of a wide variety of devices.
In this lab, you will complete a functional model of a
comparator with hysteresis. The reason for creating this device
lies in the difficulty of creating the design using discrete
devices and the need to completely reformat the equations if the
threshold or hysteresis values change in the preliminary stages of
the design. Below is an example circuit and steps in calculating
the resistor values for hysteresis. Additional resistors are needed
to set the threshold and if the threshold voltage changes these
resistor values must also change.
From the Maxim website:
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Lab 12
Modeling: StateAMS Lab 12-3 Synopsys SaberRD Electrical
Workshop
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Lab 12
Lab 12-4 Modeling: StateAMS Synopsys SaberRD Electrical
Workshop
Instructions
Task 1. Open the Design and the StateAMS Tool
1. Click the SaberRD button for access to the file menu and
choose: Open > Open Design.
2. Navigate to the directory SaberRD_Training_Labs/Lab12 Open
the file test_comp.ai_dsn.
Notice the empty space where your comparator will reside.
3. Switch to the Model tab to access the Modeling Tools.
4. Left-click on the StateAMS tool. The StateAMS tool opens.
5. Choose Help > Tutorials menu. There are four very
worthwhile tutorials available to teach how to model using the
StateAMS tool. It would be good to revisit these at a later
date.
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Lab 12
Modeling: StateAMS Lab 12-5 Synopsys SaberRD Electrical
Workshop
Task 2. Create the comparator model
Topology Editor
The top left pane represents the topology editor. This area
allows the user to add external connections to a model as one of
three types:
Branch terminals for conserved nets, including electrical,
mechanical, hydraulic, magnetic, and more.
Input ports, which can assume continuous behavior for
signal-flow inputs and state-based behavior for event-driven
inputs.
Output ports, which can assume continuous behavior for
signal-flow outputs and state-based behavior for event-driven
outputs.
The comparator model will have 3 nodes. The 2 input nodes will
be conserved analog and the output will be digital.
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Lab 12
Lab 12-6 Modeling: StateAMS Synopsys SaberRD Electrical
Workshop
1. Add branch terminal by selecting . Add the name inp to the
Add Branch Terminal form, then click OK. Notice that the Nature is
Electrical and the position is left. Both are correct.
The Topology Editor should now look as follows:
2. Add another branch terminal with name inm.
3. Add output port with name out by selecting and filling in the
Add Output Port form as follows:
a. Name = out1
b. Type = State
c. Unit = Digital Logic
Note: for Type and Unit, select the drop down arror to the right
to change.
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Lab 12
Modeling: StateAMS Lab 12-7 Synopsys SaberRD Electrical
Workshop
You should now have the pins defined and the symbol in the
Topology Editor should look as below.
Quantity Editor
The top right pane represents the quantity editor. This area
allows the user to define variables and quantities used in the
model. A quantity can be one of the following types:
Static Variables can either be constants, which do not change
during a simulation, or internal parameters, which are evaluated as
mathematical expressions when a simulation is initialized.
Continuous Variables are analog quantities that are evaluated at
each simulation time step.
State Variables are event-driven quantities that change at
discrete points during a simulation.
Functions are complex combinations of quantities that can be
used in continuous variable equations, action statements,
transition conditions, or transition time definitions.
You will now add 2 static variables (input parameters). These
variables will be for the threshold and hysteresis parameters.
4. Click on the and select Static Variable
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Lab 12
Lab 12-8 Modeling: StateAMS Synopsys SaberRD Electrical
Workshop
5. Fill in the following fields in the Add Static Variable form:
a. Name = hysteresis
b. Default = 1
6. Repeat step 1 and create another Static Variable with Name =
thresh and Default = 5.
Your model should now look as below.
State Diagram Editor
The bottom pane represents the state diagram editor. This area
is a canvas for defining state-dependent behavior of a model. A
state diagram may consist of the following elements:
States are used to define the regions of a models behavior.
Concurrent groups of states may exist on a single diagram, but an
initial state must be defined for each group.
Transitions define when a model should enter or leave a state,
depending on conditions met by model quantities.
Blocks allow a group of states to share transitions, thereby
simplifying the state diagram.
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Lab 12
Modeling: StateAMS Lab 12-9 Synopsys SaberRD Electrical
Workshop
Clocks can be used to define a periodic behavior that is not
state-dependent.
Its now time to add 2 states (LO, HI) and the transitons.
7. Select a initial state by clicking on . Drop it into the
State Diagram Editor with a Left Mouse Button (LMB) click. Deselect
with a Right Mouse Button (RMB) click.
8. Add a second state by clicking on . Drop it into the State
Diagram Editor with a LMB click. Deselect with the RMB.
9. Double click on the initial state and name it LO. 10. Double
click on the second state and name it HI.
11. Add transition from LO to HI by selecting the Add Transition
icon
. To start the transition, place your mouse over state LO and
LMB click. To finish, place your mouse over HI and LMB click. Do
not deselect (RMB)!
12. Now add a transition from HI to LO by first LMB clicking on
the HI state and then LMB clicking on the LO state. Now you can
deselect with a RMB.
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Lab 12
Lab 12-10 Modeling: StateAMS Synopsys SaberRD Electrical
Workshop
13. Add transition condition for LO to HI by double clicking
(LMB) on the ? above the LO to HI transition. Add vin >= (thresh
+ 0.5*hysteresis) as shown below.
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Lab 12
Modeling: StateAMS Lab 12-11 Synopsys SaberRD Electrical
Workshop
14. Repeat for the HI to LO transition using the condition
vin
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Lab 12
Lab 12-12 Modeling: StateAMS Synopsys SaberRD Electrical
Workshop
17. Click on pin inp then pin inm. The Add Continuous Variable
form will appear. Fill in the name vin. Click OK.
You will now define the input current to the comparator.
18. Click on the Add thru variable icon in the Topology
Editor.
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Lab 12
Modeling: StateAMS Lab 12-13 Synopsys SaberRD Electrical
Workshop
19. Click on pin inp then pin inm. The Add Continuous Variable
form will appear. Fill in the name iin. In the Analog Equations
section
select and then select ALL. Enter 0 in the Equation field (for
all states). The form should appear as below.
20. Click on OK
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Lab 12
Lab 12-14 Modeling: StateAMS Synopsys SaberRD Electrical
Workshop
The last addition to this model is to set the state variable
out1 to a logic 1 in the HI state and a logic 0 in the LO
state.
21. Double click on state LO and add out1=0 (include the single
quotes) in the Entry Action field as shown below, then click OK.
(Expand the window if needed to see OK.)
22. Double click on state HI and add out1=1 in the Entry Action
field. Then click OK. (Expand the window if needed to see OK.)
23. Click the Save button
24. The View HDL code button allows the user to view the model
(in openMAST) that is automatically generated by StateAMS.
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Lab 12
Modeling: StateAMS Lab 12-15 Synopsys SaberRD Electrical
Workshop
25. Notice that you can also select to output your StateAMS
model in VHDL-AMS. From the menu, select HDL > VHDL-AMS
You can now view the HDL code in VHDL-AMS with the button
.
26. Return the model to MAST mode with the menu HDL >
MAST
27. Press the View state diagram button to return to the State
Diagram Editor.
28. Move the StateAMS window so that you can see the design
schematic window.
29. Place the model that you just finished in the schematic by
pressing the place part button in the StateAMS window.
30. Close the StateAMS window.
31. Move your new model into place such that the