1 | Page Ryerson University Department of Electrical and Computer Engineering COE/BME 328 – Digital Systems Lab 5 - VHDL for Sequential Circuits: Implementing a customized State Machine 15 Marks ( 2 weeks) Due Date: Week 10 1 Objectives • To simulate and verify the operation of a sequential circuit. • To design a finite state machine (FSM) that cycles through the individual digits of your student ID using the assigned state diagrams. • To learn the difference between Mealy and Moore machines and express the FSMs with different state assignments. 2 Pre-Lab Preparation 1. You will be assigned one of the state machines described by the state diagrams shown in Figure 1. 2. Your implementation will either be a Mealy or Moore state machine as assigned by your lab instructor. Produce a state table and state-assigned table for your customized state machine. 3. Design the logic equations for each of the Flip-Flop inputs described in Figure 3. 4. Draw the logic diagram either as Mealy or Moore state machine for your circuit (depending on the assignment by your lab instructor.) 5. Create a file lab5.vhd to program the Cyclone- II EP2C35F672C6 FPGA (Hint: Use any of the methods represented in Figures 8.29, 8.33, or 8.35 of the text book). 3 Laboratory Work 1. Create the subdirectory lab5 in your work directory, and copy the file lab5.vhd to the subdirectory. 2. Consider the 9 digits of the student identifier D = {d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 , d 8 , d 9 } in its general representation. Then, as an example, a student with identifier: 500435429 will follow the sequence as in Table 1. 3. The corresponding Mealy/Moore machine state diagrams for representing student ID in Table 1 is depicted as in Figure 2. Your circuit design must handle non-valid states and non-valid student identifier cases by displaying an “E” in the seven segment display. 4. Modify and compile your design (Figures 4 and 5). 5. Assign all Input (Output) signals to any dedicated Input (Output) pins of the Cyclone- II EP2C35F672C6 FPGA on the prototype board (see Pin Assignment Tables in Lab3). Re- compile your design. NOTE: