R.S.F.Q 的應用與未來

Department of Electrical Engineering, National Taiwan University

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R.S.F.Q 的應用與未來

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簡介 　當今世界上最快的集成電路採用的是超導

金屬鈮，而非半導體化合物製造。該技術基於約瑟夫森結 (Josephson junction) 元件和超導連接間單個磁通量子的傳送。

這些工作在 10K 溫度下的超導 IC ，於 1980 年早期研究的超導 IC 大有不同。正是在那些項目快結束的時候，一些新發現導致第二代超導材料和電路製造工藝的出現 , 發展出一種基於單個磁通量子的儲存和傳輸，稱為快速單磁通量子 (RSFQ) 的邏輯電路結構。

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R.S.F.Q 基本原理

約瑟夫森效應於 1962 年由約瑟夫森提出， 1963 年由安德孫和夏皮羅實驗証實。現代約瑟夫森元件由兩層超導薄膜及中間的絕緣層構成，電子對因穿隧效應穿越絕緣層，在超導體內引起電流。

RSFQ 電路中代表信號位的不是靜態電壓，而是磁通量子的存在與否。

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R.S.F.Q 基本原理

RSFQ 電路不直接利用逃逸的量子，而是依靠磁通量子進入或離開環路時在 Junction 中產生的短電壓脈衝。如約瑟夫森結為 1um 邊長的方形，電壓脈衝持續時間約 1ps ，幅度 2mV 。隨結尺寸減小， SFQ 脈衝變窄，但幅度 - 時間乘積保持不變 2mV-ps {2x10-15 韋伯 } 。

電壓脈衝可通過微傳輸線或主動約瑟夫森傳輸線快速傳輸到其它們。所有傳輸都是超導的，損失極小，時鐘頻率高達 750GHz 。

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R.S.F.Q 的主要優點 RSFQ technology ,one of the superconductor Josephson-

junction digital technologies,has attracted significant attention because of-

(1)high speed

(2)low power operation

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R.S.F.Q 的主要優點

Extremely high operation speed

clock period :

(1) 10-20pS(100GHz) for fabricated Josephson junction while bit error is well below

(2) as small as 1-2pS if submicron niobium

technology were used----------Theoretical.

NbOAlNb //33 322

115103 bit

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R.S.F.Q 的主要優點

Power consumption Source :

(1) energy dissipation inside the Josephson junction :

----- 很小 (2)dissipation in dc current supply resistors : per

gate ----- 比較大

與矽元件之比較 : 0.8μm 100GHz 的 RSFQ 元件功率消耗約為普通矽元 件的十萬分之一。

bitjoule /10 18

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R.S.F.Q 的其它優點 精度高 : 交流約瑟夫森效應使得可用簡單的電壓測量導出輸出磁

通量子的頻率 .

電路密度高 : Josephson-junction 超導連接

信號傳輸幾乎無色散 : 可改善晶片中互連相關的延遲 ----- 進而增加時鐘 (clock) 速度

功率消耗～ 0 ∴ 可密集封裝而不會過熱

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用 R.S.F.Q 做成的邏輯 (1)

AND function F=(A+B) ×(C+D)

(a) equivalent circuit

AND circuit

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用 R.S.F.Q 做成的邏輯 (1)

(b) Dynamics for two set of data :

{A=B=1,C=D=0} and {A=C=1, B=D=0}

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用 R.S.F.Q 做成的邏輯 (1)

(1)A=B=1,C=D=0 : J3 “1” state

SFQ is applied to J5,J7 but Ic5<Ic7 no output pulse J4 “0” state

(2)A=C=1,B=D=0 : J3 “1” state

J3,J4 are switched simultaneously SFQ inject to J7 through L1,L2 J4 “0” state

Ic5+Ic6>Ic7 output pulse produce

Ic : critical current

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用 R.S.F.Q 做成的邏輯 (2)

XOR cell

(a) Equivalent circuit

Two storage Two storage interferometers:interferometers:

:J1, J3, L1, J5, J7 And J2, :J1, J3, L1, J5, J7 And J2, J4, L2, J5, J7 which are J4, L2, J5, J7 which are biased by Ib1 and Ib2 . biased by Ib1 and Ib2 .

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用 R.S.F.Q 做成的邏輯 (2)

(b)State transition diagram of XOR

Ic5<Ic3+Ic4 ; Ic5<Ic3+Ic4 ;

State “10” , AState “10” , A 輸入“輸入“ 11”, ”, J5 transit to initial J5 transit to initial “00” state“00” state

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用 R.S.F.Q 做成的邏輯 (3)

Template circuit of a subfamily of B flip-flop.

Q1 R1"1" Q2 R2"1"Q1 S1"0" Q2 S2"0"

AR1R2"1" AS1S2"0"

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用 R.S.F.Q 做成的邏輯 (3)

state transition diagram

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Dual –rail logic gate based on RSFQ cells

目的 : RSFQ 的靈敏度受限於電路參數和電源供應變異的影響 ,尤其在極高頻時 , 時鐘 (clock) 脈衝的分佈將更為複雜 . 為解決此一問題 ,我們可使用 dual-rail 資料型式的非同步資料驅動閘 .

缺點 : 硬體使用量大 for example :

44 Josephson junction for dual-rail gate

XOR gate :

only 9 junctions for classical RSFQ gate

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Dual –rail logic gate based on RSFQ cells

General structure of two-input data-driven dual-rail ligic gate

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Department of Electrical Engineering, National Taiwan University

Dual –rail logic gate based on RSFQ cells

Optimum solution :

Using the clock-driven logic for “local” computations in the blocks,and dual-rail logic to exchange the data betweem blocks

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On-chip and off-chip

Package 的重要性 :

RSFQ 技術可望解決現今 on-chip 的問題 , 使的 CPU 速度大為提昇

1000chipoffofeperformanc

chiponofeperformanc

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SFQ pulse 的傳輸 Josephson junction

impedance matching

Superconductor

allows ballistic transfer of SFQ pulses between them

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SFQ pulse 的傳輸

On-chip ballistic transfer of SFQ pulses

along superconductor microstrip lines

未來的用途 : SFQ pulse transfer between chip to chip + superconductor microstrip lines are used as chip interconnects

244 μSFor AIcurrentcritical C 125

2Z

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Chip-to-chip ballistic pulse transfer

Equivalent circuit of chip interconnects

Minimize the L effect :

adding ground capacitors on each side of L to match the Impedance between L and Z

L will distort and reflect the fast rise signal pulses

22/ ZLC

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Chip-to-chip ballistic pulse transfer

Limitation of L value :

ZLLCs /3233 :s time constant of incoming pulses

connectorthethroughtimedelay:

pHLZpsvaluesTypical s 325:

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Multiple Flux Quantum(MFQ) pulses

目的 :

為了提高 L 的最大容許值 ,必須使用具有高阻的傳輸線

------- 方法 : 使用由多個 Josephson junctions 堆疊而 成的驅動器以產生 MFQ 脈衝 .

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MFQ driver

equivalent circuit of MFQ driver

N nonlatching superconducting quantum interferometers connected in series

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MFQ driver

Output : sum of simultaneous SFQ pulses produced by N

superconducting quantum interferometers

Input : SFQ pulses

Interferometer : magnetically controled by the corresponding output

of an SFQ splitter

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MFQ driver

Result of using MFQ driver :

L can be as large as 20 ～ 30 pH

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Department of Electrical Engineering, National Taiwan University

R.S.F.Q 的主要應用

基於相位調制 /解調結構的 RSFQ 高精度 A/D轉換器　　

超導 A/D轉換器的性能已超過以往任何技術。

(1)包含了 2500多個約瑟夫森結

(2) 工作時鐘為 12.8GHz 。

(3)再結合超導 A/D 的量子級精度

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R.S.F.Q A/D 轉 換 器 的 特 性

寬頻動態可編程性能 : 用戶可以時時在位寬度和帶寬之間做平衡 ; 與此相比，半導體 A/D轉換器則很少針對幾種工作頻率設計

寬頻通信和雷達系統中，特別是全軟件無線電實現的無線通信

提高接收靈敏度和精度，可簡化手機和終端的配置要求。

應用

優點

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結 論

商業化前景 :

　　　　　　 (1) RSFQ 不需要昂貴的製造設備 , 在矽晶片製造中幾乎過時的 1μm級設備就夠了，而且 RSFQ 元件的製造本身比任何半導體製造都簡單，不需要包括外延生長、摻雜或離子注入在內的複雜步驟 ,僅需要在矽晶圓片上濺射超導薄膜和絕緣層，而晶圓可保持在接近室溫 ---------------------------- 製程便宜且容易。

速度是目前最快半導體 IC 的 100倍，所有技術都需要考慮到電磁信號的分布式本質。

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結 論

(2)市場對高頻寬應用的需求 ------促使超導 RSFQ 技術和當前已近極限的半導體製造技術結合。

(3) 最大的問題 :

為了做大尺寸的 RSFQ系統 , 封裝 (packaging) 是最大需克服的難題 , 而解決的方法就是使用 SFQ/MFQ drivers

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Reference

(1) Stas Polonsky. RSFQ: What we know and what we don’t . SUNY-Stony Brook Physics Department. Stony Brook,NY 11794-3800

(2) 《世界電子元器件》 2月號 (3) O.A.Mukhanov, S.V. Polonsky ,and V.K.Semenov.

New elements of the RSFQ logic famaily .

IEEE Trans. on Magnetics, vol. 27, NO. 2, March 1991.