RS-232 FPGA based transmitter and receiver using VHDL code

Slide 1

RS-232 TRANSMITTER AND RECEIVER USING FPGA WITH VHDL CODE

Internal Guide by:-Prof. Hardik .H .PatelAssistance professor,Department of EC,SRPEC, Unjha.External Guide by:-Mr. Elesh Patel

By:- Ankita Patel(090780111007)Kinjal Prajapati(100783111004)Vidhi Patel(090780111001)8th Semester, B.E (EC),SRPEC, Dabhi Unjha

CONTENTSAIMMOTIVATIONOVERVIEW OF PROJECTCOMPONENTSPECIFICATIONSTATE DIAGRAM SIMULATION /RESULTSWORK PLANCONCLUSIONFUTURE WORKREFERENCES

4/15/2013 RS-232 TX/RX USING FPGA WITH VHDL CODE2AIMAim of this project is to transfer data from PC to FPGA and FPGA to PC using serial communication. For this Serial communication we are using RS-232 for interfacing of PC and FPGA and Using Code of data transfer with VHDL language we Transfer data between FPGA and PC. Hyper terminal is used for transferring data and for giving input for receiver section and showing output on hyper terminal for transmitting section.4/15/20133RS-232 TX/RX USING FPGA WITH VHDL CODEMOTIVATIONMany more Data acquisition system are available in the market Based on DSP ,microcontroller and FPGA etcBut the Faster response, low Power Consumption, less time consuming of FPGA we are going though FPGA. Reason for Choosing FPGA based System:Faster Response.Low Power Consumption.Less Time Consuming.Data Security.Accuracy.

4/15/20134 RS-232 TX/RX USING FPGA WITH VHDL CODEOVERVIEW OF PROJECT4/15/2013RS-232 TX/RX USING FPGA WITH VHDL CODE5

Fig:1 general block diagram of our project4/15/20136

ALTERA MODEL[1] RS-232 TX/RX USING FPGA WITH VHDL CODEBLOCK DIAGRAM OF RECEIVER

RX RST CLK8 BIT DATA R (7 DOWN T0 0)RECEIVR DATA BLOCK4/15/20137 RECIVER DATA BLOCK RS-232 TX/RX USING FPGA WITH VHDL CODE Fig:2 BLOCK DIAGRAM OF RECEIVER

BLOCK DIAGRAM OF TRANSMITTER

8 BIT RST CLKTX DATA_TX (7 DOWN T0 0)TRANSMITTER DATA BLOCK4/15/2013 RS-232 TX/RX USING FPGA WITH VHDL CODE8Fig:3 BLOCK DIAGRAM OF TRANSMITTER

HYPER TERMINALThis is a built in interface in windows which sends and receives data through the serial port.it has the option of sending through port COM1 and COM2 and also has flexible baud rate.4/15/2013RS-232 TX/RX USING FPGA WITH VHDL CODE94/15/2013 RS-232 TX/RX USING FPGA WITH VHDL CODE10Fig:4 snap of hiper terminal

COMPONENTS

Altera kit(FPGA)RS-232 Power SupplyCyclone QUARTUS II softwarePC

4/15/2013 RS-232 TX/RX USING FPGA WITH VHDL CODE11SPECIFICATION OF ALTERA KIT5volt external supply.9600 baud rate.27 MHZ/25 MHZ frequency.

4/15/2013RS-232 TX/RX USING FPGA WITH VHDL CODE12DECIDING THE CLOCK AND BAUDRATEIn FPGA clock in not standard. That is ,in FPGA clock is use by 10MHZ,27MHZ,50MHZ etc.. Baud rate that we are using is 9600. Also there is miss match between clock and baudrate so calculate clock by:

Frequency/baud rate= new clock generetedthat is used in FPGA

4/15/2013 RS-232 TX/RX USING FPGA WITH VHDL CODE13DECIDING THE CLOCK AND BAUDRATEHere,27MHZ/9600=2812 cycleso,there is a 1406 clock cycle for upper cycle and similarly 1406 clock cycle for lower cycle.In this way clock and baud rate is decided

4/15/2013 RS-232 TX/RX USING FPGA WITH VHDL CODE14 STATE DIAGRAM4/15/2013 RS-232 TX/RX USING FPGA WITH VHDL CODE15S5 IDEAL S0 S1 S2 S3STATE DIGRAM OF RECEIVER S7S6S4S810101Data_r(0)