Robust Mixed-Signal Design-Methodologies for Smart Power ICs (ROBUSPIC)

CAMBRIDGE

UNIVERSITY

SIXTH FRAMEWORK PROGRAMME

Robust Mixed-Signal Design-Methodologies for Smart Power ICs (ROBUSPIC)

D1.5: LIGBT sub-circuit model

Editors: • Florin Udrea, Vasantha Pathirana, Ettore Napoli, • Gehan Amaratunea, Guillaume Bonnet and Tanya Trajkovic

Date: September 17th 2004

CONFIDENTIAL

Technical Report 1.5 – LIGBT sub-circuit model page 2

Technical Report 1.5

LIGBT sub-circuit model

Florin Udrea, Vasantha Pathirana, Ettore Napoli

&

Gehan Amaratunga, Guillaume Bonnet, Tanya Trajkovic

First Technical Report A Macro sub circuit SPICE model for LIGBTs............................................. 1

1.1 Aim of the project ................................................................................................................... 3

1.2 Introduction ............................................................................................................................ 4

1.3 Finite element analysis vs. experimental results....................................................................... 4

1.4 LIGBT device physics............................................................................................................. 6

1.4.1 Steady-state device analysis.............................................................................................. 7

1.4.2 Transient device analysis .................................................................................................10

1.5 The analytical model ..............................................................................................................14

1.5.1 Base width ......................................................................................................................15

1.5.2 Base Carrier Distribution.................................................................................................16

1.5.3 Current equations ............................................................................................................18

1.5.4 Voltage equations............................................................................................................21

1.5.5 Base charge model ..........................................................................................................23

1.5.6 Capacitances ...................................................................................................................23

1.6 Spice implementation.............................................................................................................25

1.7 Application of the model ........................................................................................................26

1.7.1 Device parameters and extraction procedures...................................................................26

1.7.2 Matching finite element simulations with PSpice simulations ..........................................29

1.8 Scalability and robustness of the model ..................................................................................35

1.8.1 Matching on transient curves when circuit conditions are varied ......................................35

1.8.2 Scalability of the Model with varying drift length ............................................................38

1.9 References .............................................................................................................................41

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1.1 General considerations

The current power electronics industry is facing a number of challenges. One of these challenges is to develop an accurate simulation tool for device design and analysis. This is because the verification of device behavior before fabrication greatly accelerates the design process. It is possible to carry out these simulations through finite element device simulators such as Medici [19] and Silvaco [1]. However with these simulators only a limited number of circuit elements and devices are allowed and simulation time can be very high.

For this reason it is useful to develop device models for low end simulation software’s such as PSpice and Saber. Currently such models are available for different devices such as vertical MOSFETs, diodes and vertical IGBTs. However, little effort has been devoted to the development of reliable device models for lateral devices that are widely used in the field of smart power and power integrated circuits (PIC’s). Important examples of these devices are the lateral MOSFET and the lateral IGBT. This work focuses on the development of a reliable device model for the Lateral IGBTs (LIGBT).

The aim of this project would be to develop a compact model for the LIGBT which works for both steady-state and transient simulations. The final goal is to embed the model into commercial simulators such as Saber, Spice or Spectre. The performance of the model in terms of accuracy, convergence, robustness and continuity needs to be assessed extensively in realistic circuits like pulsed-mode converters, half-bridge configurations, power supplies, etc. The model will be extended to cover dynamic self-heating effects.

There are two main technologies for LIGBT that are targeted in this project. The Junction-isolation based on RESURF concept is historically the first, but arguably the most difficult due to the presence of the parasitic pnp transistor in the substrate which makes the charge distribution in the bipolar base non-uniform both in x and y directions. Silicon on Insulator (SOI), today the preferred route for many manufacturers (e.g. Toshiba, Hitachi, Camsemi) features a buried oxide layer which prevents the charge build-up in the substrate. This result in a more uniform charge distribution in the base of the bipolar (i.e. drift region of the device) which in turn simplifies considerably the on-state and transient models. The combination of SOI and LIGBT is becoming increasingly popular in power conversion application (e.g. SMPS, high voltage drivers, lighting). There are two types of SOI technology in power devices: (i) the thin SOI technology (e.g. 1µm or below, used for example by Camsemi, Philips, Xfab) and (ii) thick SOI technology (e.g. 5 µm or thicker, used for example by Hitachi and Toshiba). Given that SOI is a considerably more advanced technology for Power ICs and highly suitable for LIGBTs, and the fact that Camsemi has developed a thin SOI technology, which allows us to have a large experimental data bank, we started our modeling work on thin SOI technology. A specific model for thin SOI technology will be developed followed by an extension to thick SOI and finish with a generic model that would allow its application to any technology including Junction-Isolation technology.

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1.2 Introduction

The IGBT is a power device structure that is designed to overcome high on-state loss of the power MOSFET while maintaining the simple gate drive requirements of a MOSFET. This novel device is introduced in the early 80’s [1][2] has proven to be a reliable and effective power device and it’s application field is still expanding. In its most elementary form the subcircuit model for the IGBT is a compound device made by a MOSFET and a pnp BJT. However this simple model even though is used in teaching basic device characteristic, is not suited for accurate modeling of both on-state and transient device characteristics.

State of the art IGBT models on Spice and Saber are mainly based on the work carried out by Hefner [3][4][5][7][8][9][11]and Kraus [6][12][15][16]. Their work is based only on vertical IGBTs. Hefner’s model has the most physical representation of the IGBT and well explained on literature. This model describes carrier dynamic in the drift region by solving ambipolar diffusion equation and ambipolar transport theory [3][5]. Unfortunately vertical device models are not well suited for the lateral IGBTs. Lateral IGBTs behave differently from vertical IGBTs due to the differences in horizontal carrier dynamics, terminal capacitances, substrate effects, parasitic series resistors, the parasitic JFET effect etc [10][13][17]. The lateral IGBT model on this work is based on Hefners vertical IGBT model with several notable differences applicable to lateral IGBTs. However certain circuit elements in the sub-circuit to model parasitic elements in the LIGBT are taken from Kraus approach to improve the convergence. Current implementation of this model is on PSpice using several SPICE-type elements assembled in a sub-circuit and we believe Saber or Spectra implementation of it to be straight forward.

Initial modeling work has been carried out to investigate the topologies which allow the best rendering of the behavior of the LIGBT according to TCAD simulation and measurement results from Camsemi LIGBT. Using results from the initial investigation, a charge-based compact model is developed. This model will compute static currents and charges at several key internal nodes in order to capture the specific transient effects which occur inside the LIGBT. The LIGBT model has taken into account the electron injection from the cathode side (completely and wrongly neglected by Heffner) and it accurately extract the parasitic capacitances. The transient model has also been changed to account for the fast extension of the depletion region in the drift region during the transient turn-off of the device.

It is able to match accurately the charge profile in the bipolar base and describe the MOS component using a standard SPICE library MOSFET. The on-state performance of the model is very good (with accuracy below 5% in the region of interest – below saturation) while the transient behavior is reasonably accurate within 15%.

1.3 Finite element analysis vs. experimental results

As a first step for the development of the model, the results from the two dimensional numerical simulator Medici [19] has been matched against the experimental data from the Camsemi LIGBT. The simulator has then been used as a tool to examine the internal device physics and to analyse device behavior under particular working conditions without the need for a dedicated experiment.

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Figure 1 shows the Medici matching against measurements in the on-state curves for the CamSemi LIGBT. The mobility models that had been used in the Medici simulations are Shirahata mobility (SHIRAMOB), field dependent mobility (FLDMOB), concentration dependent Shockley-Read-Hall mobility (CONSRH), Auger recombination model (AUGER) and Band Gap narrowing model (BGN). Note that in order to account for the 3D effects of the device in a 2D simulator, some modifications to the device structure have been made. As an example, in the Lateral IGBT N+ source that sinks the electron current and P+ body that sinks the hole current get connected in the direction of the z axis not available in a 2D simulator. This results in a non uniform current flow under the channel and effective channel length gets longer than the fabricated device channel length. The channel length of the fabricated device is 2µm and source N+/P+ ration is 1/1. Hence to get a better match, channel length for the structure used with the numerical simulator, has been extended to 3µm.

Figure 2 shows the Gate transfer characteristics for the same device matched against the Medici 2D-simulations. Both Figure 1 and Figure 2 show a good agreement between Medici numerical simulations and experimental data.

Figure 1 : On-State curves Medici vs measurements

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Figure 2 : Gate transfer curves Medici vs measurements

1.4 LIGBT device physics

Figure 3 shows the device structure and layout of a LIGBT on SOI technology.

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Figure 3 : Punch through LIGBT on SOI Technology

1.4.1 Steady-state device analysis

1.4.1.1 Carrier Concentration

Figure 4 depicts the carrier concentration inside the device at different horizontal cut-lines in steady state operation when the Gate is at 5V and the Anode is at 4V. In general carrier concentration drops drown from Anode end to the Gate end due to recombination in the base. High increase in the electron concentration and decrease in the holes concentration is observed on the top surface at the left edge of the drift region. This is due to the accumulation layer, created by the gate field plate. The slightly higher difference between electron and hole concentration on the right hand edge of the drift region is due to the presence of the buffer layer with high donor doping. Note that mostly throughout the device the high level injection condition (n≅p) is satisfied. Another important aspect that can be devised is that, due to the thin SOI technology, device carrier concentration behaves in an essentially one dimensional way. Hence 1D approximation will be used for the model which would allow significant simplification on model equations.

Substrate

P-well

Poly

Gate Cathode Anode

Top silicon

FieldOxide

N+ P+

N-drift

Buried Oxide

Nwell

P+

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Figure 4 : Carrier Concentration at Vg=5V and Va=4V

Carrier concentrations in the middle of the device at different Gate and Anode voltages are presented in Figure 6. As the Gate voltage is increased carrier concentration is increased due to the increased base current. Numerical simulations clearly show that carrier concentration is not equal to zero at the Base end of the drift region (left hand side). The vertical IGBT models developed by Hefner and Kraus [5][9][16], are based on the assumption that the carrier concentration at the Base end of the Drift region is zero. For the LIGBT it is instead more accurate to say the carrier concentration at the Base end is roughly 1/3 of the carrier concentration at the Anode side. The non-zero carrier distribution at the Gate end is defined as the PIN diode effect and can be easily explained as an accumulation-inversion Layer Injection effect [13]. The accumulation layer, due to the gate field plate, forms a N+ accumulation layer that extends from the channel inversion layer. The P+ anode/N- base/N+ accumulation-inversion layer forms a PIN diode with the N+ accumulation-inversion layer injecting carriers into the drift region. The result is that the carrier concentration at the base end of the drift region is not zero.

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Figure 6 : Hole concentration at different Gate and Anode voltages

1.4.1.2 Current Density

Figure 7 shows the current flow lines through the device and current density at different horizontal cut lines through the device. Current flow is uniform at different depths in the device with the exception of the Gate side. Due to the accumulation region and channel inversion region, electron current is directed toward device surface and electron current density at the top surface increases. However it is a reasonable assumption to assume a one dimensional current flow through the device.

In the drift region, where the current flow is uniform, the electron current is larger than the hole current. This can be explained by the higher mobility of the electrons compared to holes. In general the electron mobility is about 2 times the hole mobility. Hence the current density of electrons is roughly twice as the hole current density.

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Figure 7 : Current density at Vg=5V and Vd=4V through different horizontal cut-lines

1.4.2 Transient device analysis

Due to the short drift length and fast depletion region expansion, turn-off times for LIGBT is very fast as shown in Figure 8 where the complete turn-off lasts about 80ns. This figure illustrates the turn off current at the Anode for the inductive switching circuit shown next to it. In this circuit the LIGBT is operated at a current density of 25A/cm2, while supply voltage is 200V and gate resistance is 10Ω. More detailed pictures of the turnoff wave forms are shown in Figure 9.

As we would expect in an inductive switch, current drop occurs once the Anode voltage has at least ramped to the supply voltage. The electron current at the Cathode which is the MOSFET current goes down to zero before the Anode current starts to fall. However since Anode current can’t drop down until the Anode voltage has reached the supply voltage, hole current at the Cathode increases to compensate for the drop down in the electron current. When the Anode current starts to fall it closely follows the hole current at the Cathode. The first fast turn off of the Anode current is due to the MOSFET turning off. The following current tail is due to the removal of the stored charge in the drift region.

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Figure 8 : Turnoff circuit and turnoff Anode current

Figure 9 : Enlarged turn off wave forms

1.4.2.1 Carrier concentration

Figure 10 shows the electron and hole concentrations inside the LIGBT at different time points. As the LIGBT is turned off carrier concentration drops down due to the carrier recombination in the base and hole injection into the collector. Stepwise drop down in the carrier concentration at the Anode side is due to higher doping in the N-well which increases the recombination rate in that region. Also note that there is a slightly higher electron concentration compared to the hole concentration inside the base which is due to the background doping. Since this difference is small our high level injection approximation (n≅p) can still be used.

ANO0

GATE1

KA

T 2

1

2

L1100uH

V1

200Vdc

V2

TD = 0n

TF = 10nPW = 0.5uPER = 1u

V1 = 0

TR = 10n

V2 = 5

0

R1

10

I

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Figure 10 : Drift region carrier concentration at different time points during turn off (t=0.52, 0.53, 0.54, 0.56, 0.58, 0.6, 0.62, 0.64, 0.66, 0.68, 0.7, 0.75, 0.8 µs)

1.4.2.2 Depletion region expansion

Figure 11 depicts the expansion of the depletion region width of a P-N junction together with the Camsemi device for DC Anode biasing. Clearly the expansion of the depletion region in the Camsemi device is much faster than the P-N junction depletion. In the lateral device expansion of the depletion region is influence by substrates, field oxides, field plates etc. When the Anode voltage is low depletion region width in the Camsemi device is around 10µm. This is due to the depletion coming from the top field plate. The depletion region width of the Camsemi device can be approximated as 4.25 times the P-N junction depletion width. However if the depletion due to the field plate is removed (10µm) it would be around 3 times the p-n junction depletion. In the transient mode accurate analysis have also shown that, due to the high current density, the depletion region expansion is influenced by the hole current flowing through it.

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Figure 11 : Expansion of the depletion region width (Vg=0V)

1.4.2.3 Current density

Figure 12 shows the current density through the device at three different horizontal cut-lines during device turn-off. In the un-depleted area the current flow is uniform which implies that 1D approximation for the current flow is still valid even during the turn off transient.

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Figure 12 : Current density at different horizontal cut lines during device turn off

1.5 The analytical model

Figure 13 represents a lateral IGBT and the naming convention used for the derivation of the equations.

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Figure 13 : Steady state currents and carrier distribution

1.5.1 Base width

High level injection region is considered to be the un-depleted base width. It is necessary to get an expression for the expansion of the depletion region (Wdep) so that quasi-neutral base width can be expressed as:

depB-WWW =

Equation 1 : Quasi-neutral base width

In lateral devices the expansion of the depletion region is influenced by field plates, substrate, field oxide and other things. In the Camsemi device fast depletion occurs at the beginning of the anode voltage rising phase due to the gate field plate. The fast expansion stops when the depletion width is about 10µm wide (Widthfp_dep) and then a slower depletion width expansion similar to a p/n junction depletion width expansion takes place (Widthpn_dep). The depletion similar to the p/n junction depletion is influenced by the field oxide, buried oxide and substrate. The total depletion width of the Camsemi device is then taken as

Gate

Cathode/

Source/

Collector Anode/

Emitter

p+

n+

Pwell Ndrift p+

0 W Wb

Depletion

Region

IN(0)

Ip(0)

IN(W)

IP(W)

P0

Pw

Carrier

Distribution

Base/

Drain

Device area is A

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deppndepfpdep WWW __ +=

Equation 2 : Depletion width expansion in Camsemi device

The Field plate depletion width is observed in finite element simulations to be linearly increasing with drain to source voltage up until 10µm which is the length of the field plate (Widthfp) and then constant.

<<

<<=

Bdepfpfpfp

fpdepfpdsfp

depfp

WWWidthWidth

WidthWVWidth

W

_

__

;

0;10

Equation 3 : Field plate depletion in Camsemi device

The Camsemi device p/n junction depletion width is observed in Medici finite element simulations, to be three times the normal p/n junction depletion width. Hence this is given by Equation 4, where Nscl is the effective doping and Wpn_inc=3.

Bdeppnscl

bidssiincpndeppn WWqN

)V(VeWW <<+= ___ 0;2

Equation 4 : p/n junction depletion width as a function of anode in Camsemi LIGBT

The space charge concentration due to mobile carriers flowing through the base-collector depletion region at the saturation limited velocity has an effect on the depleted region expansion. This effect is mainly be due to the hole current flowing through the depleted region. There is barely any effect from the electron current in the lateral IGBT since it is mainly flowing in the inversion and accumulation layers and prevents it from spreading into the depletion region. Therefore the effective doping is expressed as:

)(W)/(qAvINN psatpBscl +=

Equation 5 : Effective background doping

1.5.2 Base Carrier Distribution

The steady-state carrier distribution in the base region under high level injection (n≅p) is determined by using the solution to ambipolar diffusion equation (Equation 6) in steady state.

=

∂∂

0tp

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tp

DLp

xp

∂∂

+=∂∂

.1

22

2

Equation 6 : Ambipolar diffusion equation

The boundary conditions on the charge distribution are shown in Figure 13. Emitter side carrier concentration is P0 and base side carrier concentration is Pw. Solving the ambipolar diffusion equation in steady-state with the boundary conditions shown yields the solution:

( )[ ] ( )( )LW

LxPLxWPp(x) w

sinhsinhsinh0 +−

=

Equation 7 : Steady-state carrier distribution

The total charge inside the base is then obtained by integrating Equation 7 across the un-depleted base region width W. After simplification the total charge Qb is determined as:

( ) ( )LWqALPPQ wb 2tanh0 +=

Equation 8 : Total base charge

By assuming Pw=αP0,where α is a constant, emitter edge carrier concentration P0, base edge carrier concentration Pw and average carrier concentration in the base Pavg, can be derived as:

qAWQb

P

L)(W/qALQ

aa

P

L)(W/qALQ

aP

avg

bw

b

=

+=

+=

2tanh1

2tanh11

0

Equation 9 : Boundary carrier concentrations

For the Camsemi device α=1/3. It was observed in finite element simulations carried out for turn off transient, that the carrier concentration at the base edge goes down to zero as the Gate voltage goes below the threshold voltage. The reason is the removal of the electron current and high electric field at the base edge that quickly removes the charge. Hence in the model Pw is zero if the Gate voltage is below the threshold voltage. Pw and P0 are used in the current, voltage and base resistance derivations. Pavg is used to model the dependency of mobility with the carrier concentration.

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1.5.3 Current equations

1.5.3.1 Steady-state current equations

Using the simple diode equation together with the quasi-equilibrium simplification and assuming the high-level injection of holes into the base, the electron current at the emitter junction can be derived as follows, where Isne is the electron reverse saturation current at the emitter junction:

2

20

200)0(

ii

B)E(E

kTq

sne

N

n

P~

n

)P(NPe

II fpfn +

==−

Equation 10 : Electron current at the emitter

An approximation for the electron reverse saturation current at the Anode P+/Nwell junction can be extracted using the simple diode equation.

n

n

a

isne

DN

qnJ τ

2

= with nn qkT

D µ=

Equation 11 : Electron reverse saturation current

The derivation of the Jsne is not straightforward. The intrinsic carrier (ni) is in fact influenced by Band Gap Narrowing effect while both lifetime and mobility depend on the doping.

By solving the ambipolar transport equations (Equation 12) using the steady state carrier distribution (Equation 7) and electron current at the emitter junction (Equation 10), the electron and hole currents in the quasi-neutral base can be derived. The solution is given in Equation 13.

xp

q.A.D..Ib

I

xp

q.A.D..Ib

bI

TP

TN

∂∂

−+

=

∂∂

++

=

11

1

Equation 12 : Ambipolar transport equations

( ) ( )[ ]

+−

+−+=

−−−−+=

(x/L)b

Pb(W/L)

x)/L)((WP(W/L)L

qADI

bnP

(x)I

(W/L)PPx)/L)((WP(x/L)P(W/L)L

qADI

nP

(x)I

wsnei

P

wwsnei

N

cosh1cosh

coshsinh

coshcoshcoshsinh

02

20

002

20

Equation 13 : Steady-state electron and hole currents inside the quasi-neutral base

The electron current at the cathode is the electron current at x=W and is equal to the MOSFET current. The hole current at the cathode is derived by substituting x=W in Equation 13.

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+−

++==

(W/L)b(W/L)P

(W/L)b(W/L)

PL

qADI

bn

P(W)II wsne

iPSSPC sinh

1coth

sinh1coth

02

20

_

Equation 14 : Steady-state hole current at the cathode

1.5.3.2 Transient current equations

Fig

ure 14 : Transient carrier distribution during turn off

The charge carrier distribution and current equations derived so far are for steady-state conditions. A transient term is needed in the cathode hole current expression (Equation 14) to account for the removal of charge due to the expansion of the depletion width with time. This term is derived by examining the charge distribution inside the device in transient turn off simulations for an inductive switch using Medici finite element software. The carrier distribution inside the device at different time points is depicted inFigure 14. What can be observed here is at the beginning, the depletion width expands quickly because the Anode voltage needs to get to the supply voltage before current starts to drop. In this region the carrier concentration towards the right hand side (emitter side) of the picture stays fairly constant. By assuming the transient current term is equal to the removal of charge due to the expansion of the depletion width, the following sets of equations can be derived.

Increasing Anode Voltage Stable Anode Voltage

P0

P

Wt Wt+dt Wt+2dt

Time is

increasing

0

CONFIDENTIAL


( )

),(

),(),(),(1

),(),(

0_

0_

_00

tWpt

Wdx

tp

I

dxtxpdxtxpttxpt

I

dtIdxttxpdxtxp

t

W

TRNPC

W

W

W

TRNPC

tt

tTRNPC

WW

tt

tt

t

tt

ttt

∂∂

−∂∂

−=

−++−=

=+−

∫

∫∫

∫∫∫

+

++

+ +

δ

δδ

δ

δδ

δδ

We assume first term to be very small. This is true in the initial transient since not much change in charge occurs on the right hand side. This assumption would make the transient hole current at the cathode to be equal to Equation 15. This can be considered as a capacitive current that depends on drain to source voltage.

tVds

VdsW

tWpt

WtWpI ttTRNPC ∂

∂

∂∂

−=∂

∂−= ),(),(_

Equation 15 : Transient hole current at the cathode

The carrier concentration at x=Wt is roughly the steady state carrier concentration at that point. At the start of the transient the carrier concentration at the emitter edge (P0) is not changing. In steady-state the collector edge carrier concentration is aP0 and quasi-neutral base width is very close to the base width of the device. The steady-state carrier distribution (Equation 7) can be used for this derivation and is given by:

+

−

=

LW

LW

PL

WWP

tWPB

ttB

t

sinh

sinhsinh),(

00 α

Equation 16 : Carrier distribution for transient current

The total hole current at the cathode for the turn off transient then would be the sum of steady-state current and transient current (Equation 17).

TRNPCSSPCPC III __ +=

Equation 17 : Total hole current at the cathode

The transient term is only valid when the anode voltage is rising (e.g. turn off). When anode voltage is falling (device is turning on), time derivative of W is positive and the total hole current derived by Equation 17 will be smaller than the steady state current and may even become negative.

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This is unphysical and hence in the model transient term in the hole current at the cathode is added to the steady-state current if only the derivative of the quasi-neutral base width W is negative.

1.5.4 Voltage equations

Figure 15 : The band diagram from the emitter to base contacts

Shown in Figure 15 is the band diagram including quasi-fermi potentials from the emitter to base contacts. The applied emitter contact to base contact potential is given by Equation 18.

)()( nbnejnejpejebV φφφφ −+−=

Equation 18 : Emitter base potential drop

First term is on-state diode voltage drop at the P+ emitter and n-base junction which is roughly 0.7V. The second term of Equation 18 is the electron quasi-fermi potential drop across the quasi-neutral base. The electron quasi-fermi potential gradient is related to the electron current and the electron concentration by Boltzman transport theory:

xx

xnqAxI nnn ∂

∂−=

)()()(

φµ

Equation 19 : Boltzman transport equation for electron current

The electron quasi-fermi potential drop across the quasi-neutral base is determined by integrating this equation between the emitter and the base edges of the quasi-neutral base with In(x) given by Equation 12 and n(x)=NB+p(x) where p(x) is given by Equation 7.

Efn

Efp

Ec

Ev

Base

-F nb

-F pb

-F nej

-F pej

Quasi-neutral base width 0 W

Em

itter Contact

CONFIDENTIAL


∫ +=

++

−

+

=−=

W

Beff

Bw

B

neffn

Tnbnejbase

xpNdx

Wn

NPNP

LogD

Aqnb

WIV

0

0

)(11

11 µµ

φφ

Equation 20 : Base voltage drop

The first term on the right side of Equation 20 can be identified as the as the resistive voltage drop across the conductivity modulated base where neff is the effective carrier concentration that depends on P0, and the second term can be identified as the high-level injection diffusion potential due to the difference in carrier concentration across the base. Using the carrier distribution given by Equation 7, an analytical expression for neff is derived. Since PSpice cannot handle complex numbers two separate solutions are needed in order to have positive values inside square root terms. The equations are:

( )

( )W/L)(w

wwBW/L)(w

W/L)(w

B

(W/L)

eff

wwBBW/L)(w

wwBBW/L)(w

W/L

W/L

W/L)(weff

wwB

ePP(W/L)L

?

(W/L)PPPP(W/L)N)eP(P

ß

ePP(W/L)N

a

ßß

aß

ae

ßW?

n

Else

(W/L)PPPP(W/L)N(W/L)N)eP(P

ß

(W/L)PPPP(W/L)N(W/L)N)eP(P

a

a)ß)((eß)a)((e

ß)(a)ePW(P(W/L)L

n

(W/L)PPPP(W/L)NIf

−

−

−

−−

−

−

−

−=

+−−−−

=

−=

+−

+

=

−++−−

−=

−+++−

−=

−−−−

−−=

≥−++

0

022

022

0

0

11

022

022

0

022

022

0

0

022

022

sinh2

sinh2sinh1

sinh

1tantan

1

sinh2sinhsinh1

sinh2sinhsinh1

11

log1sinh21

0sinh2sinh

Equation 21 : Effective base carrier concentration for base resistance

Now the on-state Anode-Cathode voltage drop of the LIGBT is given by the sum of p+/n junction built in potential, base voltage drop and voltage drop across the MOSFET channel.

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mosbasebiA VVVV ++=

Equation 22 : Anode voltage drop

1.5.5 Base charge model

Using the charge conservation equation, the base charge of the LIGBT can be expressed by the following equation.

τQ

IIWItQ

TRNPCNN −−−=∂∂

_)0()(

Here IN(W)is the electron current at the cathode and this is equal to the MOSFET current. IN(0) is the emitter edge electron current and is given by Equation 10. IPC_TR is the removal of the charge due to the transient current and is given by Equation 15. The last term accounts for the recombination in the base.

1.5.6 Capacitances

1.5.6.1 Gate to Source Capacitance

This is taken as the gate channel oxide capacitance (Cchnl) which can be expressed by

Gate to Drain Capacitance

The gate to drain equivalent capacitance is modeled by the series combination of oxide capacitance (Cacc) due to the gate field plate and depletion region capacitance (Cdep) respectively. The oxide capacitance is constant while depletion region capacitance depends on depletion width. From basic junction analysis and using for the Camsemi device the depletion width as 4.25 (Winc) times the p/n junction depletion width (accounting for both field plate depletion and p/n junction depletion), the capacitance associated with the p-well/n-base depletion region can be derived as:

dg

siB

incdep V

qNW

AC

2ε

=

Here A is the device cross sectional area perpendicular to the current flow. Then calculating the equivalent capacitance and simplifying yields

2

22

12

acc

siBincn

n

dg

acc

depacc

depacceqv

CAqN

WVwhere

V

VC

CC

CCC

ε=

+

=+

=

CONFIDENTIAL


Implementing this equivalent capacitance in PSpice can be achieved through the series combination of a voltage source and a Cacc capacitor, as shown by Figure 16.

Figure 16 : Gate variable capacitor equivalent circuit

The equation controlling the voltage source must be Vdep=f(Vdg) such that

[ ]

0,0)(,0

21log

2)(

12

11)(

)(

12

11

)()(

12

)(

12

)(

12

0

0

===

+

++−==

∂

+

−=

∂

∂=

+

−∂

∂

∂

−∂=

∂

+

=

∂

+

=

∂

∂+

∂+

=∂

∂=

∫

CVfVWhen

CV

VV

V

VVVVfV

V

V

VVf

t

Vf

V

Vt

V

t

VfVC

t

Vdf

V

V

CI

t

Vdf

V

V

Ct

VCt

Vdf

V

V

Ct

VCI

dgdg

n

dgn

n

dgndgdgdep

dg

n

dg

dg

dg

n

dg

dg

dgdgacc

dg

n

accdg

dg

n

dg

accaccdg

n

dg

accdgeqvdg

dg

Equation 23 : Gate variable capacitor model

This then determines the function controlling the variable voltage source Vdep such that the series combination of Vdep and Cacc represent the variable gate to drain overlap capacitance.

1.5.6.2 Drain to Source Capacitance

Drain to Source capacitance is represented by a reverse bias diode connected between the Drain and Source. The zero bias junction capacitance for the diode model is calculated using the Equation 24.

+-

Cacc

Gate Drain

Vdep +-

Vdg

CONFIDENTIAL


To the normal p/n junction capacitance term Winc (this is 4.25 accounting for both field plate depletion and p/n junction depletion) is included to represent the fast expansion of the depletion region width in the Camsemi device. The parameters for this equation are P-well (Na) and N-drift (Nd) doping levels and device cross sectional area perpendicular to the current flow (A).

20

2/1

0

ln

)(2

i

da

ad

ad

sisi

incjo

n

NNq

kTVwhere

NNNN

Vq

WA

C

=

+

=ε

ε

Equation 24 : Zero bias junction capacitance

1.6 Spice implementation

Implementing a model in low-end circuit simulators such as PSpice is not a straightforward task since it introduces practical issues such as convergence, robustness, and the speed-complexity tradeoff. Figure 17 shows the basic PSpice circuit for the new model. Two diodes are used to represent emitter/base (Deb) and drain/source (Dbc) junctions. Voltage drop inside the base is represented by a voltage dependent voltage source. The hole current at the collector is represented by a voltage control current source (IP(W)). Electron current at the collector is due to the MOSFET and it is represented by a PSpice Level 1 MOSFET. The voltage dependent gate to drain capacitance is represented by a voltage control voltage source (Vdep) in series with the accumulation layer oxide capacitance (Cacc). Gate to source capacitance is fixed and equals to the channel oxide capacitance (Cchnl).

The base charge sub-circuit models the accumulation or removal of carriers in the base through an RC circuit using the difference between Cathode (IN(W)) and Anode (IN(0)) electron currents and transient current (Ipc_TRN(W)). The values of the resistance and capacitance are chosen so that the time constant of the sub-circuit RC is equal to the ambipolar base lifetime tb. The instantaneous charge Qb stored is the base region is then the product of the capacitance with the voltage at the base sub-circuit node.

CONFIDENTIAL


Cchnl

In(W) Ip(W)

Vbase

taub/1u

Anode/Emitter

Cathode/Collector/Source

Gate

It

1u In(0) In(W)

0

Base Charge Subcircuit

Ipc_TRNDbc

Deb

Drain/Base

Cacc

Vdep

Vb

Qb=Vb*1u

+

-

Figure 17 : New LIGBT PSpice circuit

1.7 Application of the model

1.7.1 Device parameters and extraction procedures

1.7.1.1 Carrier concentration at the base end

By looking at the Medici simulations this has been adjusted as 1/3 times the carrier concentration at the emitter side.

1.7.1.2 Mobility

Mobility on the device is significantly influenced by the carrier concentration. In the Medici simulations low field mobility is modeled by Shirahata mobility. This is a variation of Phillips mobility model that include the mobility dependence of perpendicular electric fields. It accounts for distinct acceptor and donor scattering, Carrier-carrier scattering and screening. However the expression for mobility in Shirahata mobility model is too complicated to be implemented in Spice code. A simpler expression to model the carrier-carrier scattering based mobility is given by Equation 25. Here the dp is the carrier concentration and µn and µp are the electron and hole lattice scattering based nobilities which depend on the background doping. For this device µn and µp are taken as 1350cm2/Vs and 450cm2/Vs respectively.

CONFIDENTIAL


[ ]

cppc

cnnc

c pp

µµµµµµ

αδαδµ

/1/1/1/1/1/1

/)(1ln(/1 23/2

2

+=+=+= −

Equation 25 : Mobility model

The constants a1 and a2 are adjusted to match the Shirahata mobility model (ignoring the effects from perpendicular electric fields) at different carrier concentrations. The two constants are found to be a1=3e20cm-1V-1s-1 and a2=4.54e11cm-2.

Figure 18 represents the variation of the mobility according to carrier concentration on Shirahata mobility and the much simpler mobility model.

Figure 18 : Mobility model parameters

1.7.1.3 Ambipolar Lifetime

The formula to extract the carrier concentration dependent Shockley-Read-Hall lifetime is given by Equation 26. The parameters t 0 and N are the SRH lifetime and background doping respectively. For a SRH lifetime of 0.2µs and background doping level of 4.5e15cm-3 the carrier concentration dependent SRH lifetime becomes 0.185µs.

CONFIDENTIAL


16510

/

eNpn

+=

ττ

Equation 26 : Concentration dependent life time

The ambipolar lifetime for high level injection is given by Equation 27 where t n and t p are the electron and hole carrier concentration dependent SRH lifetimes respectively and in this case they are equal. Hence the ambipolar lifetime for this device is equal to 0.37µs

pna τττ +=

Equation 27 : Ambipolar lifetime

1.7.1.4 Electron Reverse Saturation Current

An approximation for the electron reverse saturation current at the Anode P+/Nwell junction can be extracted using the diode Equation 11. Accounting the band gap narrowing and the doping dependence on both lifetime and mobility the extracted parameters are:

3

3

195

102

2185

107

−=

−==

=

cmeN

µset

/Vscmµ

cmen

a

n

n

-i

Substituting the above values in Equation 11, Electron reverse saturation current density Jsne was found to be 2.427e-12A/cm2. However this becomes a fitting parameter and needs to be adjusted to match the measurement/simulation data. For the final matching this parameter is taken as 1.4e-12A/cm2.

1.7.1.5 Mosfet Threshold Voltage

An estimation for the threshold voltage can be made by using the Gate transfer curves in Figure 2. The estimated value is 1.62V.

1.7.1.6 Mosfet Transconductance

The transconductance for the MOSFET in the LIGBT is extracted by looking at the saturation current levels. The ratio between electron current and hole current is estimated by looking at the turn-off curve of the LIGBT. In the current turn off curve of the Anode current the initial fast turn off is due to the MOSFET turning off. The current tail afterwards is due to the removal of the holes. Hence the ratio between electron and total current is

CONFIDENTIAL


( ) 7204016003671

03671.

...

=+

=α

Using the equation for simple MOSFET current in saturation with threshold voltage VT as 1.62V

VAeKIVV

VAeKIVV

VAeKIVV

VAeKIVV

)-V(VI

K

psatgs

psatgs

psatgs

psatgs

Tgs

satp

/249.11188.05

/242.10558.04

/233.10176.03

/230.10013.02

22

−===

−===

−===

−===

=α

The value used for the MOSFET transconductance in the spice model is 1.36e-2A/V.

1.7.2 Matching finite element simulations with PSpice simulations

1.7.2.1 Steady-state curves

Figure 19 represents the on-state matching between Medici and PSpice. Very good matching is observed in the linear region. Since we are using a level 1 MOSFET matching on the saturation region is not very good. Also due to the hole current flowing under the gate, the effective potential drop across the gate to source will not be the gate voltage. Also mobility degradation due to the perpendicular electric field at the gate is not included. Figure 20 represents the matching between Medici and PSpice for the gate transfer curve. This also looks very close.

CONFIDENTIAL


Figure 19 : On-state matching between Medici and PSpice

CONFIDENTIAL


Figure 20 : Gate transfer curve matching between Medici and PSpice

Comparison of the carrier concentration inside the base between Medici and PSpice simulations is shown in Figure 21. Matching is fairly reasonable. Spice having a higher carrier concentration at the Anode side and lower carrier concentration at the Cathode side compared to Medici can be explained by the varying mobility in Medici and constant mobility in Spice.

On most literature on IGBT modeling they do not look into matching the carrier concentration even though it gives an accurate model for the device status. It has been observed that by adjusting the model parameters we can even get more matches (e.g.: carrier concentration at the base zero with a different Isne), however if the carrier concentration is wrongly matched and Isne is specified incorrectly there will be a huge difference on transient simulations.

CONFIDENTIAL


Figure 21 : Comparison of carrier concentration at Vg=5V and Vd=4V

1.7.2.2 Transient Curves

First set of simulations were carrier out for an inductive switch. For the Camsemi device maximum current density was set around 25A/cm2 based on the total device length which is 73.4µm. For the circuit on Figure 22 device width was set at 54495µm.

AN

O0

GATE1

KA

T2

U1JIGBT020

V1

200Vdc

V2

TD = 0n

TF = 10nPW = 0.5uPER = 2u

V1 = 0

TR = 10n

V2 = 5

0

R1

10

1

2

L1100uH

VI

Figure 22 : Inductive switching circuit

CONFIDENTIAL


Figure 23 depicts the turn off curves for the above circuit. It represents anode voltage, anode current and power loss. Matching on all voltage, current and power loss wave forms are very good. In the new model current tail seem to be underestimated from the Medici simulations slightly. However in this region since current levels are fairly low power losses would be minimal. Hence it would not have a significant impact on the total energy loss at turn off.

Figure 23 : Medici vs PSpice (Current/Voltage/Energy loss turn off curves)

Figure 24 depicts some wave forms to show what is happening inside the PSpice simulations. I(VINC) is the mosfet current and I(VIPC) is the hole current at the collector. When the MOSFET gate voltage goes below threshold voltage, electron current falls down to zero. In this region hole current is increasing to keep the current without dropping until the anode voltage reaches the supply voltage. Base edge carrier concentration (V(Pw)) goes down to zero as soon as the MOSFET current turns off. Also note the ratio between the electron current and total current which is around 0.7 and it is not far from what we extracted from Medici simulations.

CONFIDENTIAL


Time

0s 100ns 200ns 300ns 400ns 500ns 600ns 700ns 800nsI(U1:ANO) V(U1:ANO)/200 I(X_U1.GINC) I(X_U1.GIPC) V(X_U1.p0) V(X_U1.pw)

0

0.2

0.4

0.6

0.8

1.0

1.2

Figure 24 : PSpice circuit output variables

Figure 25 shows the matching against the Anode and Gate voltages and currents for a complete period of a cycle. Matching on these wave forms looks very good for both turn on and turn off. With these devices turn on losses are less significant so in the next sections we will be focusing on turn off losses.

CONFIDENTIAL


Figure 25 : Anode and Gate wave forms for an inductive switch (Ia=1A, Va=200V)

1.8 Scalability and robustness of the model

1.8.1 Matching on transient curves when circuit conditions are varied

Figure 26 shows the matching between Medici and PSpice model for the inductive switch when the period of the transient signal is made twice to make the current to be twice. Figure 27 shows the same curves when the supply voltage is at 400V. Same as we observed in other wave forms Spice seems to under estimate the current tail. Also note that at around 6µs Spice starts to over estimate the current wave form when the drain voltage is at 400V. The reason for this is at 400V depletion region hits the n-well buffer and when this happens there is a fast drop down in current. This is seen in the Medici simulations. In our model this effect is not yet included.

CONFIDENTIAL


Figure 26 : Inductive switch with Ia=2A and Va=200V

Figure 27 : Inductive switch with Ia=2A and Va=400V

CONFIDENTIAL


Figure 28 shows the turn off curves when current source is used instead of an inductor.

Figure 28 : Current source with Ia=1A and Va=200V

Figure 29 depicts the Medici and Spice wave forms for a resistive switch. This also has a very good match between Medici and Spice simulations.

CONFIDENTIAL


Figure 29 : Resistive switch with Ia=1A and Va=200V

1.8.2 Scalability of the Model with varying drift length

Figure 30 and Figure 31 show the on-state and transient results respectively when the length of the drift region is increased from 51µm to 61µm (effective drift length 35µm to 45µm). Again the matching is looking very good between Medici simulations and PSpice simulations.

CONFIDENTIAL


Figure 30 : On-state matching results when drift region is increased by 10µm

CONFIDENTIAL


Figure 31 : Turn off wave forms when the drift length is increased by 10µm

CONFIDENTIAL


1.9 References

[1] J.P. Russel, A.M. Goodmann, L.A. Goodman, J.M. Nielson “The COMFET: a new high conductance MOS gated device” IEEE Int. Electron Devices Meeting Digest, Abs 10.6, pp. 264-267, 1982

[2] B.J. Baliga, M.S. Adler, R.P. Love, P.V. Gray, N. Zommer “The insulated gate transistor: a new three terminal MOS controlled bipolar device” IEEE Transaction on Electron Devices, Vol. EDL-6, pp.74-77, 1985.

[3] A.R. Hefner, D Blackburn, “An analytical model for the steady-state and transient characteristics of the power insulated-gate bipolar transistor”, Solid State Electronics, Volume: 31 , No 10, 1988, Pages:1513-1532

[4] A.R. Hefner “An improved understanding for the transient operation of the power insulated gate bipolar transistor (IGBT)” IEEE Transactions on Power Electronics , Volume: 5 , Issue: 4 , Oct. 1990, Pages:459-468

[5] A.R. Hefner “Analytical modeling of device-circuit interactions for the power insulated gate bipolar transistor (IGBT)” IEEE Transactions on Industry Applications, Volume: 26 , Issue: 6 , Nov.-Dec. 1990, Pages:995-1005

[6] R. Kraus; K. Hoffmann”, An analytical model of IGBTs with low emitter efficiency” Proceedings of the 5th International Symposium Power Semiconductor Devices and ICs, 1993. ISPSD '93, 18-20 May 1993, Pages:30-34.

[7] C.S.Mitter; A.R. Hefner, D.Y. Chen, F.C. Lee; “Insulated gate bipolar transistor (IGBT) modeling using IG-SPICE” IEEE Transactions on Industry Applications, Volume: 30 , Issue: 1 , Jan.-Feb. 1994

[8] A.R. Hefner, “A dynamic electro-thermal model for the IGBT” IEEE Transactions on Industry Applications, Volume: 30 , Issue: 2 , March-April 1994, Pages:394-405

[9] A.R. Hefner, D.M. Diebolt, “An experimentally verified IGBT model implemented in the Saber circuit simulator” IEEE Transactions on Power Electronics , Volume: 9 , Issue: 5 , Sept. 1994, Pages:532-542

[10] F. Udrea, G. A. J. Amaratunga, Q. Huang, “The effect of the hole current on the channel inversion in Trench Insulated Gate Bipolar Transistor”, Solid State Electronics, Vol 37, 1994, Page 507

[11] A.R. Hefner “Modeling buffer layer IGBTs for circuit simulation” IEEE Transactions on Power Electronics, Volume: 10 , Issue: 2 , March 1995, Pages:111-123

[12] R. Kraus, K. Hoffman, P. Turkes, “Analysis and modeling of the technology dependent electro-thermal IGBT characteristics”, IPEC-Yokohama, 1995, Page 1128.

[13] F. Udrea, G.A.J. Amaratunga, J. Humphrey, J. Clark, A.G.R. Evans, “The MOS inversion layer as a minority carrier injector”; IEEE Electron Device Letters, Volume: 17 , Issue: 9 , Sept. 1996, Pages:425-427

CONFIDENTIAL


[14] B.J. Baliga Modern Power Devices, PWS, Boston ,1996

[15] J. Sigg, P. Turkes, R. Kraus, “Parameter extraction methodology and validation for an electro-thermal physics-based NPT IGBT model”, IEEE industry applications society annual meeting, Oct 5-9 1997, Pages 1166-1173.

[16] R. Kraus; P. Turkes, J. Sigg, “Physics based models of power semiconductor devices for the circuit simulator Spice”, Proceedings of the 29th Annual IEEE Power Electronics Specialists Conference, Vol 2, 1998, Pages 1726-1731

[17] D. M. Garner, F. Udrea, H. T. Lim, W. I. Milne, “An analytical model for turn off in the silicon-on-insulator LIGBT”, Solid State Electronics, Mar 1999, Pages 1855-1868

[18] A.R. Hefner; S. Bouche, “Automated parameter extraction software for advanced IGBT modeling” The 7th Workshop on Computers in Power Electronics, 2000. COMPEL 2000., 16-18 July 2000 Pages:10-18

[19] Medici user guide, Fremont CA, Avant Corporation, 2000.

[20] Atlas User guide, Silvaco corp, 2000

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