Robert Reese, Microprocessors: From TKT-3500 Assembly to C … · · 2008-09-22Microcontroller systems Lec 3b – Reset and interrupts ... Designing Embedded Systems with PIC Microcontrollers

Erno Salminen - Sep. 2008

TKTTKT--3500 3500 Microcontroller Microcontroller systemssystemsLec Lec 3b3b –– Reset and interruptsReset and interrupts

Erno SalminenErno Salminen

Department of ComputerDepartment of Computer SystemsSystemsTampere University of TechnologyTampere University of Technology

Fall 2008Fall 2008

Erno Salminen - Sep. 2008#2/54

SourcesSourcesRobert Reese, Microprocessors: From Assembly to C with the PIC18Fxx2, Charles River Media, 2005Tim Wilmshurst, Designing Embedded Systems with PIC Microcontrollers –Principles and applications, Elsevier, 2007.Wikipedia


ContentsContentsReset

PurposeSources, power-on reset circuitsTiming

InterruptsConcept of program flowBasicsSources and control registers in PICInterrupt service routinesTiming


ResetResetReset forces the CPU into known state

a) When the system is powered upb) When things have gone horribly wrongProgram counter gets certain value, e.g. 0x0, and program execution restartsMany possible sources, e.g.

external: pin connected to buttoninternal: brown-out detection or watchdoginternal: stack overflow or underflow

Reset behavior can be vectorizedVector tells what to do next (where to jump)


Reset vectorReset vectorLocated into default memory location (address) where the CPU starts execution after resetThat address contains a pointer (address) of where to continue

e.g. it points to the first instruction of main(argc, argv)

main: mov r1,0program counter (PC)

2. 0x0

0x70

GOTO 0x70

0x72 mov r2,5...

3.

4.

(program) memory

1. External reset pin driven low2. After reset, PC ← 0x0003. PC ← mem[0x000]

1. i.e. PC ← 0x704. PC ← mem0x72

XMCLR#

1.


BrownBrown--out and watchdog as reset sourcesout and watchdog as reset sources

Brown-out detection (BOD)Detects partial loss of electricity, Vdd drops below certain threshold

compare to black-out = total loss of electricityResets the CPU to avoid corrupting the memory contents

WatchdogHW timer that triggers a system reset if the main program, due to some fault condition neglects to regularly service the watchdog

Writing a service pulse to it, aka “petting the dog” or “kicking the dog"

E.g. when main is stuck into infinite loop, communication caused deadlock (circular wait condition)Can wakeup the CPU from low-power sleep mode


Reset sources in PIC18Reset sources in PIC18

Oscillator start-up timer delays the release of reset so that oscillator stabilizes

Schmitt trigger-hysteresis provides

noise immunity

Watchdog timer – the dog must be kept happy regularly

Power-up timer waits that power source is stabilized

master clear – ext. reset pin

Supply voltage is also monitored


Reset circuitry Reset circuitry –– 3 basic choices3 basic choicesi. Power-on reset (POR)

rises accroding to RC constant of the circuitii. POR+ discharge diode

fast switching of Vdd could leave capacitor charged and PIC would not be resetRs protects CPU by limiting current into pin MCLR

iii. User reset buttonmandatory in prototypesR limits short-circuit current, R [10, 100k] Ω

PICPIC

MCLR

PICPIC

MCLR

PICPIC

MCLR

Vdd

GND

R

C

R

C

Rs

i) power-on reset ii) power-on reset + discharge diode

iii) user reset button

R


Schmitt trigger at reset input Schmitt trigger at reset input Special buffer for inputsDoes not change state when input changes only a little

Phenomenon is called hysteresisAlso transforms slowly changing signals into sharp ones (fast rise/fall times)

input output

Vin

Vout

Vin

Vin

Vout

Vout

TTL input

Schmitt trigger

1.0 V 4.0 V

Vdd=5 V

0.8 V 2.0 V

thresholdLH

t

t

thresholdHL

1. Schematic symbol 2. Vout output changes only when Vin goes beyond threshold voltage

3. Voltage transfer curves for basic TTL and Scmitt

Vdd=5 V


PowerPower--onon--reset (POR) timingreset (POR) timingPower-up timer has own clock – time-out TPWRT occurs usually after 72 msOscillator timer’s time-out TOST occurs after 1024 (master) clk cycles

Vdd

MCLR

internal POR

PWRT time-out

OST time-out

internal reset

TPWRT

TOST


Finding out the reset source from SWFinding out the reset source from SWRCON register contains status bits that indicate the reset typeNext actions can be selected accordinglyC language has special type qualifier persistent

prevents variable from being initialized by start-up code prior to main()can be used for logging reset sources and to count them

persistent char reset_cnt; /* global variable*/void main () ...

Erno Salminen - Sep. 2008

InterruptsInterrupts


Program flowProgram flowThe order in which the individual statements, instructions or function calls of an imperative or functional program are executed or evaluatedA control flow statement decides which control flow is takenControl flow statements can be categorized by their effect:

continuation at a different statement (jump),executing a set of statements only if some condition is met (choice),repeating a set of statements until some condition is met (loop),executing a set of distant statements, after which the flow of control may possibly return (subroutines, coroutines, and continuations),stopping the program, preventing any further execution (halt)


Program flow (2)Program flow (2)In machine or assembly language, control flow instructions usually work by altering the program counter

For example, conditional or unconditional branchesInterrupts and signals are low-level mechanisms

can alter the flow of control in a way similar to a subroutineusually occur as a response to some external stimulus or eventinterrupts can be though as “HW-initiated function calls”


InterruptsInterruptsInterrupts are used to change the normal flow of a program so that it can perform another (specified) functionAllow external events to change (interrupt) the normal flow of the software and then executing code specifically designed as a responseThe interrupted part of the code does not know what hit it

In theory, it may notice it from the RTC (real-time clock) (as if abducted by UFO)


Interrupts (2)Interrupts (2)Allow processors to automatically respond to specified events and concentrate processing power on executing a main programProcessors without in-built interrupt support require programs which regularly inspect selected input lines.

This is called ‘polling’ or ‘busy wait’ Polling is very expensive in terms of processingSee e.g. previous examples with USART

while (something_happened ==0) process_data();


Interrupts (2)Interrupts (2)When an interrupt occurs

1. the instruction currently being executed is completed

2. PC jumps to address 0x08 or 0x18 in program memory and executes the instruction stored there, practically GOTO

ORG 0X00GOTO START

;ORG 0X08GOTO INT_SRVC_HI ; INT VECTOR contaisn just jumpsORG 0X18GOTO INT_SRVC_LO ; INT VECTOR contaisn just jumps

INT_SRVC_HI ; ACTUAL HI-PRIOR ISR HERE………………RETFIE ; RETURN FROM INTERRUPT

;START ; MAIN PROGRAM GOES HERE

…………………END


Interrupt systemInterrupt systemInterrupts can be enabled or disabled (masked)

individually per-sourceglobally (all disabled regardless of source)

Interrupts enabled by INTCON-register’s GIE-bitAll interrupts have a priority

PIC18 has 2 priorities: high or lowBefore using interrupts corresponding interrupt source has to be enabled and priority chosen


Interrupt flagsInterrupt flagsInterrupt flag bits are set

when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit

User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt

This feature allows for software polling.Of course, flag must be cleared also after servicing the interrupt


Interrupt sourcesInterrupt sourcesInterrupts may be triggered based on

signal edge: rising, falling, eithersignal level: high, low

having both levels doesn’t make much sense

Each source can be configured first1. edge or level –sensitive, active value2. reset the flag (if set by default)3. enable the sourceSources may

have separate interrupt pins, orshare one interrupt pin


SensivitySensivity

INT0

1. pos.edge

2. neg.edge

4. high level

5. low level

Inte

rrup

ts s

ensi

tivity

Sometimes certain input pins allow only subset of these choices

3. either edge (change)

Example usage: external device keeps interrupt asserted until serviced. ISR envoked perhaps only once (high in example) or twice (low)

timeflag is set


Interrupt sources (2)Interrupt sources (2)29 separate sources4 external input pins INT0...INT3

multiplexed with PORTB[3:0]4 other pins GPIO port BTimersPeripherals

parallel slave portAD-converterEUSART rx, txMSSPcapture-compare-PWM module (CCP/ECCP)


Interrupt sources(3)Interrupt sources(3)

Note that occurrence of interrupt request always sets the corresponding flagInterrupt disable prevents the jump to interrupt vectorOnce enabled again, the previously set flag will cause the interrupt


Control registers for interruptsControl registers for interrupts10 registers are used to control interruptsreset control RCONinterupt control INTCON, INTCON2,INTCON3peripheral interrupt flags PIR1, PIR2, PIR3peripheral interrupt enable PIE1, PIE2, PIE3interrupt priority IPR1, IPR2, IPR3


Interrupt service routine (ISR)Interrupt service routine (ISR)Function to perform the necessary actionsCalled automatically after interrupt request

Calls (GOTOs) are placed into interrupt vector

Accepts no parametersDoes not return any values

May modify global variables, thoughRemember to use volatile qualifier

Must ensure not to mess up the CPU stateTwo ISRs in PIC: high and low priorities

High prior. interrupt may pre-empt lower priority but not vice versa


Entering Interrupt service routineEntering Interrupt service routineWhen entering ISR

1. registers BSR, W, STATUS are saved automatically to shadow registers

In general, all CPU’s registers must be savedShadow registers allow fast save/restore but increase area

2. Return address is pushed automatically on the stack

3. Usually, all interrupts are disabled a) usually implicitlyb) sometimes by the programmer

at least those with lower priority


Entering Interrupt service routine (2)Entering Interrupt service routine (2)4. Programmer may store other context

information manuallyIn PIC, e.g. multiplier register MULH+ MULLAny special function registers utilized in ISR

5. In PIC, the source of interrupt has to be checked manually in ISR

Since interrupts are shared by multiple sourcesOther CPUs may have a) separate interrupt pins and ISRsb) register denoting the source

which simplify ISR code


Exiting ISRExiting ISRActions during exit are reversed from those during entering

Restoring context requires special attention as certain instructions affect STATUS register

Does not use the same machine-code for return as regular functions

RETFIE instead of RETURNNo values returnedContext may restored from shadow regs instead of stackInterrupts must be enabled again


ISR in ASMISR in ASMas

. Location defined by linker

because shadow registers may be taken by higher prior ISR

. Note the order! STATUS is restored last because previous restorations

W is stored first with movwf which does not affect STATUS flags.

affect the flags. Parameter 0 for retfie tells not to restore from shadow registers.


Interrupts vs. trapsInterrupts vs. trapsA trap is a special non-maskable interruptNot supported by all CPUsHigher priority than any regular interruptHard trap : some type of HW failureSoft trap: triggered by some instructionExamples:

divide-by-zeroinvalid memory addressuser SW calls OS function that must be executed in privileged (supervisor) mode

On this course, we will not consider traps


Program flow exampleProgram flow example1. CPU is reset2. Reset vector points to initialization

function (usually compiler-generated)

3. Execution jumps to main()4. Main() calls other functions5. Function foo() is interrupted, PC

points to interrupt vector6. ISR is executed7. Execution returns to foo() to the

instruction following the last executed one

8. Function foo may call other functions

9. Execution returns from bar to foo10. Execution returns from foo to main11. Main remains in infinite loop unless

other interrupts occur

init() ... GOTO main

main() ... foo() ... while(1)

foo() ... bar() ... return

bar() ... return

isr() ....

retfie

0x0rst vecisr vec

1

2

3

4

5

6

7

8

9

10

11

Program memory


Polled IO vs. interruptPolled IO vs. interrupt--drivendrivenPolled IO

CPU checks continuouly the status of the transferWastes time for checking, cannot do anythign elseTrade-off between

Check often – excess overheadCheck seldom – small overhead, events may be missed

Interrupt-driven IOCPU can perofrm other tasks while transfers is being completed by special HWCPU can sleep while waiting for incoming dataModern computers use interrupt-driven IO


Polled/IntPolled/Int--drv IO example (1)drv IO example (1)Polled – mobile phone without ring indicator

Check mobile phone every now and thenTake it from your pocket, purse what ever...”Hello, is someone calling?”How often should you check?How long will the callers wait on line for you perhaps answering? Ain’t this the coolest gadget or what...


Polled/IntPolled/Int--drv IO example (2)drv IO example (2)Interrpt-driven – regular mobile phone

You’ll be noticed (interrupted) when a call or SMS arrivesCall/SMS may arrive asynchronouslyYou may disable interrupts but can check the ’flags’ laterSeems more convenient and efficientInterrupts may be nested – you’ll can put the current call on hold when some VIP calls

Important persons have higher priorityYou may accept only certain calls (e.g. during night time)


Polled IO examplePolled IO exampleunsigned char getch (void) while (RCIF==0);return (RCREG);

unsigned char getche (void) /* called by library function scanf */

unsigned char c;c = getch()putch (c); /* echo */return c;

void main (void) char param =0;serial_init (95,1) /* etc. */

printf (”Starting.”);

printf (”Feed the input values.”);

while (1) scanf(”%i”, &c); transmogrify

(param);printf (”Result is

%i”, param);


Polled IO example (2)Polled IO example (2)Example works well, when input comes at low rateHowever, transmogrify and printf may take quite a whileNo values are accepted when those functions are being processedWhen values come in bursts, some may be lostIf USART overrun occurs, scanf gets stuck

Aargh.

ok

timeparam arrives

ok ok ok

overrun! Voi poltetun poltettu!


Handling bursts with bufferingHandling bursts with bufferingData may be buffered before processingBuffer must be larger enough accomodate the largest possible burstIn the long run, the processing rate must be larger than incoming data rate

Otherwise, every buffer will overflow at some pointBurst are followed by period of less activity when the buffered params can be handled

ok

timeparam arrives

ok ok ok

1. Params handled at the same as they arrive

2. Burst is stored temporarily into buffer

3. Params from buffer are handled


Handling bursts with buffering (2)Handling bursts with buffering (2)Buffer works with FIFO principle

Firstin, first outThe buffer may be implemented

on HW – fixed sizee.g. USART RX has two-word buffer

on SW – flexible sizeThe appropriate size depends on data rate and burstiness of trafficObviously, fixed size buffer does not work always


SW FIFO bufferSW FIFO bufferSW buffer is an array with two pointers

head – where the new data is storedtail – from where the data is read

Data is not copied from location to another but the pointers are updated


SW FIFO buffer (2)SW FIFO buffer (2)Pointers wrap to the beginning when incremented enough

so called circular bufferHead equals tail when FIFO is empty

If head catches the tail, overrun occurs (fig c)There are different policies for pointers, e.g.

increment head and then write, head++; buf[head] = new_data;

write and then increment headbuf[head] = new_data; head++;

Be sure to document properly!

Aargh.

At most n-1 words stored:

8-slot FIFO can hold 7 data words.


Buffered interruptBuffered interrupt--driven IO exampledriven IO exampleLet’s modify previous exampleUse circular buffer (a SW FIFO)Interrupt service routine will place incoming data into buffer

Example does not check overrun, thoughgetch() function will read from the buffer

It waits until there is some datamain() is the same, except that interrupts are enabled


Buffered interruptBuffered interrupt--driven IO example (2)driven IO example (2)#define BUF_MAX 32volatile unsigned char

ibuf[bUF_MAX], head, tail;unsigned char getch ()

/* this is called by scanf*/while (head==tail);tail++tail %=BUF_MAX;return ibuf[tail]

void interrupt pic_isr(void) if (RCIF)

head++;/* no check for overrrun */head %= BUF_MAX;ibuf[head] = RCREG;

void main (void) char param =0;serial_init (95,1) /* etc.

*/IPEN=0; RCIE=1; PEIE=1;

GIE=1;printf (”Starting.”);printf (”Feed the input

values.”);while (1)

scanf(”%i”, &c);transmogrify (param);printf (”Result is %i”,

param);

/* getche() unchanged */


State machine State machine State changes when user presses button connected to RB0

Initally, led is offStart when user presses button

LED starts blinkingIt keeps blinking until

user presses button andswitch connected RB7 goes low

Keep LED lighted until button is pressed again

turn off the ledreturn to start state


State machineState machine’’s ISRs ISRGlobal semaphore variables

ISR updates these, main just reads (except int_flag)

Remove bounce from button inputClear flag bitNotify main via global var that int occurred Go to next state

Check switch position first when blinking

Update the led’s statusblink/on/off


State machineState machine’’s main functions main functionAfter initialization, loop foreverRead semaphores updated by the ISR

Control the led (RB4)Print also state information for debug purposes


State machineState machine’’s behaviors behavior

7. 8. 9.

onoff


Interrupt latency and overheadInterrupt latency and overheadInterrupt latency denotes the time between

1. occurrence of interrupting event2. entering the ISRInterrupt overhead means the CPU time taken by the ISRBoth are critical in real-time systems

CPU must react to external events within bounded time (small/bounded latency)ISR prevents the main from running and may hence distract its timing (small/bounded overhead)


Interrupt latency and overhead (2)Interrupt latency and overhead (2)Disabling interrupts increases latency!

Disabled when processing critical section, such as data structure shared/accessed by multiple entities (functions, SW/HW)All/Lower priority interrupts are automatically disabled when entering ISR

Flags must be checked when exiting ISR

The disable duration must be minimizedThe duration of ISR must be minimized

no printf()Debug info must be placed into trace buffer variable and print them in main code

no wait statements


Interrupt latency and overhead (3)Interrupt latency and overhead (3)Interrupts arrive asynchronously!

One cannot predict their occurrenceMust prepare for their arrival at any point

Even within another ISRAs much as possible of the work must be done in main code whereas ISR handles the time-critical partsOperating system may enlongen the ISR latency


ISR enter latencyISR enter latencyCurrent instruction is finished first

Note that interrupt disable causes indefinite delaySave PC and jump to interrupt vectorJump to ISR Note that figure is for PIC24 but the principle is the same.


ISR exit latencyISR exit latencyPerform retfie instructionRetrieve contextJump back to main code


ISR overheadISR overheadIEntry - #instr cycles when entering ISRIBody - #instr cycles within ISRIExit - #instr cycles when exiting ISRfISR = 1 / tISR

frequency of interrupt triggering is reciprocal of triggering period

OverheadISR = ((IEntry + IBody + Iexit) * fISR) / fCPU

Example, IEntry =4, IBody=50, IExit=3, fCPU=40 MHZtISR = 10 ms means 0.01 % overheadtISR = 1 ms means 0.14% overheadtISR = 0.1 ms = 100 us means 1.43 % overheadtISR = 0.01 ms = 10 us means 14.3 % overhead


C syntax for ISR with PICC syntax for ISR with PIC# pragma interrupt function-name [tmp-section-name][save=save-list][nosave=nosave-list]Pragmas are preprocessor commands

This associates the user defined function-name with interrupt vectorThat function becomes the ISR

[tmp-section-name]

[save-list]List of variables or data sections to save in ISR

[nosave-list]List of variables or data sections not to save in ISR


ConclusionsConclusionsInterrupts allow handling of asynchronous external events

Parallel execution, caution required!May happen any time – come like a fax to prime minister

Interrupt service routines are very time-sensitiveMust react fastMust not interfere with main code timingDo as much as work as possible in main code

Compared to polled IO Increase the performanceAchieve the same performance with lower enegy (wake from sleep with interrupt)

Robert Reese, Microprocessors: From TKT-3500 Assembly to C … · · 2008-09-22Microcontroller systems Lec 3b – Reset and interrupts ... Designing Embedded Systems with PIC Microcontrollers

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