RISC-V BOOM Microarchitecture Design Space Exploration ...

BOOM-Explorer: RISC-V BOOM MicroarchitectureDesign Space Exploration Framework

Chen Bai1, Qi Sun1, Jianwang Zhai2, Yuzhe Ma1, Bei Yu1, Martin D.F. Wong11The Chinese University of Hong Kong 2Tsinghua University

Abstract—The microarchitecture design of a processor hasbeen increasingly difficult due to the large design space and time-consuming verification flow. Previously, researchers rely on priorknowledge and cycle-accurate simulators to analyze the perfor-mance of different microarchitecture designs but lack sufficientdiscussions on methodologies to strike a good balance betweenpower and performance. This work proposes an automaticframework to explore microarchitecture designs of the RISC-V Berkeley Out-of-Order Machine (BOOM), termed as BOOM-Explorer, achieving a good trade-off on power and performance.Firstly, the framework utilizes an advanced microarchitecture-aware active learning (MicroAL) algorithm to generate a diverseand representative initial design set. Secondly, a Gaussian processmodel with deep kernel learning functions (DKL-GP) is built tocharacterize the design space. Thirdly, correlated multi-objectiveBayesian optimization is leveraged to explore Pareto-optimaldesigns. Experimental results show that BOOM-Explorer cansearch for designs that dominate previous arts and designs de-veloped by senior engineers in terms of power and performancewithin a much shorter time.

I. INTRODUCTION

Recently, RISC-V, an open-source instruction set archi-tecture (ISA) gains much attention and also receives strongsupport from academia and industry. Berkeley Out-of-OrderMachine (BOOM) [1], [2], a RISC-V design fully in com-pliance with RV64GC instructions, is competitive in powerand performance against low-power, embedded out-of-ordercores in academia. By adopting Chisel hardware constructionlanguage [3], BOOM can be parametric, providing greatopportunities to explore a series of microarchitecture designsthat have a better balance on power and performance fordifferent purposes of use.

Microarchitecture defines the implementation of an ISAin a processor. Due to different organizations and combi-nations of components inside a processor, microarchitecturedesigns under a specific technology process can affect powerdissipation, performance, die area, etc. of a core [4], [5].Finding a good microarchitecture that can accommodate agood balance between power and performance is a notoriousproblem because of two restrictions. On the one hand, thedesign space is extremely large and the size of it can beexponential with more components to be considered, e.g., spe-cial queues, buffers, branch predictors, vector execution unit,external co-processors, etc. Thus, we cannot traverse andevaluate each microarchitecture to retrieve the best one. On theother hand, it costs a lot of time to acquire metrics, e.g., power,performance, etc. when we verify one microarchitecture withdiverse benchmarks.

In industry, the traditional solution is based on prior en-gineering experience from computer architects. However, itlacks scalability for newly emerged processors. In academia,to overcome these two obstacles, researchers proposed variousarts, which can be categorized as two kinds of methodologies.First, in view of the difficulty in constructing an analyticalmodel, researchers can otherwise characterize a microarchi-tecture design space with fewer samples as much as possibleby leveraging statistical sampling and predictive black-boxmodels. Li et al. [6] proposed AdaBoost Learning with novelsampling algorithms to explore the design space. Second,to search for more designs within a limited time budget,researchers often rely on coarse-grained simulation infrastruc-ture rather than a register-transfer level (RTL) verification flowto accelerate the process [7]–[10]. Moreover, by decreasingredundant overhead, the simulation can be further speed up[11]–[14].

Unfortunately, both of these academic solutions containseveral limitations. In the first place, despite the fact thatstatistical analysis performs well when highly reliable mod-els can be constructed, it fails to embed prior knowledgeon microarchitectures to further improve design space ex-ploration. For another, to accelerate the simulation, coarse-grained simulation infrastructure is used widely. Nevertheless,most of them lose sufficient accuracy, especially for distinctprocessors. The low quality of results is generated often dueto the misalignment between simulation and real running be-haviors of processors. More importantly, because it is difficultto model the power dissipation of modern processors at thearchitecture level [15], some infrastructure cannot providepower value, e.g., [8], [10]. In general, because of the afore-mentioned limitations, academia lacks sufficient discussionson methodologies that can explore microarchitecture designsachieving a good trade-off between power and performance.

In this paper, following the first strategy, we proposeBOOM-Explorer address these issues. In BOOM-Explorer,without sacrificing the accuracy of a predictive model, we em-bed prior knowledge of BOOM to form a microarchitecture-aware active learning (MicroAL) algorithm based on trans-ductive experimental design [16] by utilizing BOOM RTLsamples among the entire design space as few as possible.Secondly, a novel Gaussian process model with deep kernellearning functions (DKL-GP) initialized through MicroAL, isproposed to characterize the features of different microarchi-tectures. The design space is then explored via correlatedmulti-objective Bayesian optimization flow [17] based on

DKL-GP. Our framework can not only take advantage of fewermicroarchitecture designs as much as possible but also helpsus to find superior designs that have a better balance betweenpower and performance.

Our contributions are summarized as follows:• A microarchitecture-aware active learning methodology

based on transductive experimental design is introducedfor the first time to attain the most representative designsfrom an enormous RISC-V BOOM design space.

• A novel Gaussian process model with deep kernel learn-ing and correlated multi-objective Bayesian optimizationare leveraged to characterize the microarchitecture designspace. With the help of DKL-GP, Pareto optimality isexplored between power and performance.

• We verify our framework with BOOM under advanced 7-nm technology. The experimental results demonstrate theoutstanding performance of BOOM-Explorer on variousBOOM microarchitectures.

The remainder of this paper is organized as follows. Sec-tion II introduces the RISC-V BOOM core and the problemformulation. Section III provides detailed explanations onthe framework. Section IV conducts several experiments onBOOM core to confirm the outstanding performance of theproposed framework. Finally, Section V concludes this paper.

II. PRELIMINARIES

A. RISC-V BOOM CoreBOOM is an open-source superscalar out-of-order RISC-

V processor in academia and it is proved to be industry-competitive in low-power, embedded application scenarios[1], [2].

Fig. 1 demonstrates the organization of BOOM. Consist offour main parametric modules, i.e., FrontEnd, IDU, EU, andLSU, BOOM can execute benchmarks in distinct behaviorsvia choosing different candidate values for each componentinside these modules. FrontEnd fetches instructions fromL2 Cache, packs these instructions as a sequence of fetchpackages, and sends them to IDU. IDU decodes instructionsas micro-ops and dispatches these micro-ops w.r.t. their cat-egories to issue queues in EU, the latter of which, triggeredby corresponding micro-ops and related logics, is responsiblefor manipulating operands in an out-of-order manner. Finally,some memory-related operations, i.e., loading data and storingdata, interact with LSU after EU calculates the results. Inaddition, BOOM also integrates branch predictors, floating-point execution units, vector execution units, etc.

Thanks to the parameterized modules provided by BOOM,various BOOM microarchitectures can be acquired by con-figuring the core with different parameters. Thus, divergenttrade-offs between power dissipation and performance tomeet various design requirements can be achieved, e.g., low-power, and embedded applications. However, a satisfyingmicroarchitecture design is non-trivial to be found.

Across all parametric modules, a microarchitecture designspace of BOOM is constructed and shown in TABLE I. Eachrow of TABLE I defines structures of a component inside

L2 Cache

I-CacheI-TLB

Fetch Buffer

Decoder Decoder

RASBTB

BP

Decoder

Re-Order Buffer

FPIssue Queue

INTIssue Queue

MEMIssue Queue

INT RF

FP RF

……

Rename Logic Retire LogicAllocate Logic

MemCalc

FPDiv

FPInt

FMA

iMul

iDiv

ALU RoCC

CSRs

ALU

ALU

D-Cache D-TLBMSHR

STQ LDQ

FrontEnd IDU EU LSU

Fig. 1 BOOM implements a ten-stage pipeline, i.e., Fetch,Decode, Register Rename, Dispatch, Issue, Register Read,Execute, Memory, Writeback and Commit.

the module. RasEntry and BranchCount in FrontEnd areconsidered since they have great impacts on the behaviorsof branch predictions, and thus incur different power andperformance. Because caches, e.g., D-Cache in LSU, oftenruns at a lower frequency compared to other modules, thecomponent might be hotspots when many memory-relatedrequests occur in the instructions pipeline. A suitable struc-ture of D-Cache can alleviate the burden, therefore differentorganizations of D-Cache (i.e., associativity, block width, TLBsize, etc.) are also included for exploration. Besides, I-Cacheis also considered in the design space.

Different BOOM microarchitecture designs can be con-structed with various combinations of candidate values. How-ever, some combinations do not observe constraints of BOOMdesign specifications as shown in TABLE II. Thus they areillegal and cannot be compiled to Verilog. For example, eachentry of the reorder buffer traces status of every in-flightbut decoded instruction in the pipeline. If a microarchitecturedoes not obey rule 2, reorder buffer may not reserve enoughentries for each decoded instruction or may contain redundantentries that cannot be fully used at all. The last three rulesin TABLE II are added to simplify the design space. Theyrequire the same number of entries or registers in respectivecomponents and their additions will not affect the performanceof BOOM-Explorer. After we prune the design space w.r.t.rules in TABLE II, the size of the legal microarchitecturedesign space is approximately 1.6× 108.

TABLE I Microarchitecture Design Space of BOOM

Module Component Descriptions Candidate values

FrontEnd

FetchWidth Number of instructions the fetch unit can retrieve once 4, 8FetchBufferEntry Entries of the fetch buffer register 8, 16, 24, 32, 35, 40

RasEntry Entries of the Return Address Stack (RAS) 16, 24, 32BranchCount Entries of the Branch Target Buffer (BTB) 8, 12, 16, 20ICacheWay Associate sets of L1 I-Cache 2, 4, 8ICacheTLB Entries of Table Look-aside Buffer (TLB) in L1 I-Cache 8, 16, 32

ICacheFetchBytes Unit of line capacity that L1 I-Cache supports 2, 4

IDU

DecodeWidth Number of instructions the decoding unit can decode once 1, 2, 3, 4, 5RobEntry Entries of the reorder buffer 32, 64, 96, 128, 130

IntPhyRegister Number of physical integer registers 48, 64, 80, 96, 112FpPhyRegister Number of physical floating-point registers 48, 64, 80, 96, 112

EUMemIssueWidth Number of memory-related instructions that can issue once 1, 2

IntIssueWidth Number of integer-related instructions that can issue once 1, 2, 3, 4, 5FpIssueWidth Number of floating-point-related instructions that can issue once 1, 2

LSU

LDQEntry Entries of the Loading Queue (LDQ) 8, 16, 24, 32STQEntry Entries of the Store Queue (STQ) 8, 16, 24, 32

DCacheWay Associate sets of L1 D-Cache 2, 4, 8DCacheMSHR Entries of Miss Status Handling Register (MSHR) 2, 4, 8DCacheTLB Entries of Table Look-aside Buffer (TLB) in L1 D-Cache 8, 16, 32

TABLE II Constraints of BOOM design specifications

Rule Descriptions

1 FetchWdith ≥ DecodeWidth2 RobEntry | DecodeWidth +

3 FetchBufferEntry > FetchWidth4 FetchBufferEntry | DecodeWidth5 fetchWidth = 2× ICacheFetchBytes6 IntPhyRegister = FpPhyRegister7 LDQEntry = STQEntry8 MemIssueWidth = FpIssueWidth

+ “|” means RobEntry should be divisible byDecodeWidth.

B. Problem FormulationDefinition 1 (Microarchitecture Design). Microarchitecturedesign is to define a combination of candidate values givenin TABLE I. A microarchitecture design is legal if it satisfiesall constraints as referred to in TABLE II. Every legalmicroarchitecture design to be determined is encoded as afeature vector among the entire design space D. The featurevector is denoted as x. For convenience, microarchitectureand microarchitecture design in the following sections are thesame.

Definition 2 (Power). The power is to be defined as thesummation of dynamic power dissipation, short-circuit powerdissipation, and leakage power dissipation.

Definition 3 (Clock Cycle). The clock cycle is to be defined asthe clock cycles consumed when a BOOM microarchitecturedesign runs a specific benchmark.

Provided with the same benchmark, power and clock cycleare a pair of trade-off metrics since the lower cycles are,the more power will be dissipated when a design integratesmore hardware resources to accelerate instructions execution.Together, They reflect whether a microarchitecture design isgood or not. Power and clock cycle are denoted as y.

Definition 4 (Pareto Optimality). For a n-dimensional min-imization problem, an objective vector f(x) is said to bedominated by f(x′) if

∀i ∈ [1, n], fi(x) ≤ fi(x′);∃j ∈ [1, n], fj(x) < fj(x

′).(1)

In this way, we denote x′ < x. In the entire design space, aset of designs that are not dominated by any other is calledthe Pareto-optimal set and they form the Pareto optimality inthis space.

In this paper, our objective is to explore Pareto optimalitydefined in Definition 4 w.r.t. power and clock cycle for variousBOOM microarchitectures. Due to the power and clock cycleare a pair of negatively correlated metrics, a microarchitec-ture belonged to the Pareto-optimal set cannot improve onemetric without sacrificing another metric. To guarantee highquality of results, rather than use coarse-grained simulationinfrastructure introduced in Section I, we evaluate power andperformance using commercial electronic automation (EDA)tools and they are referred to as the VLSI flow. Based on theabove definitions, our problem can be formulated.

Problem 1 (BOOM Microarchitecture Design Space Ex-ploration). Given a search space D, each microarchitecturedesign inside D is regarded as a feature vector x. Power andclock cycle form the power-performance space Y. ThroughVLSI flow, the power and cycles y ∈ Y can be obtainedaccording to x. BOOM microarchitecture design space explo-ration is to be defined as to find a series of features X thatform the Pareto optimality among the corresponding Y ⊂ Y.Hence, Y = y|y′ y,∀y′ ∈ Y, X = x|f(x) ∈ Y ,∀x ∈D.

III. BOOM-EXPLORER

A. Overview of BOOM-ExplorerFig. 2 shows an overview of BOOM-Explorer. Firstly, the

active learning algorithm MicroAL is adopted to sample aset of initial microarchitectures from the large design space.In this step, domain-specific knowledge is used as the priorinformation to guide the sampling of the initial designs. Then,a Gaussian process model with deep kernel learning functions(DKL-GP) is built on the initial set. To explore the optimalmicroarchitecture, the multi-objective Bayesian optimizationalgorithm is used, with the Expected Improvement of ParetoHypervolume as the acquisition function, and the DKL-GPmodel as the surrogate model. During this process, BOOM-Explorer interacts with the VLSI flow to get the accurate per-formance and power values of designs according to differentbenchmarks. Finally, The outputs of BOOM-Explorer are theset of explored microarchitectures in the iterative optimizationprocess, and the Pareto optimality is gained from the set.

BOOM Design Space

Initial Set

Sampled Set

MicroAL

…

Figure 1: (Left): Deep Gaussian Process illustration1. (Middle): Histograms of a random selection ofinducing outputs. The best-fit Gaussian distribution is denoted with a dashed line. Some of themexhibit a clear multimodal behaviour. (Right): P-values for 100 randomly selected inducing outputsper dataset. The null hypotheses are that their distributions are Gaussian.

resulting in a Bayesian ‘self-tuning’ covariance function that fits the data without any human input[Damianou, 2015].

The deep hierarchical generalization of GPs is done in a fully connected, feed-forward manner. Theoutputs of the previous layer serve as an input to the next. However, a significant difference fromneural networks is that the layer outputs are probabilistic rather than exact values so the uncertainty ispropagated through the network. The left part of Figure 1 illustrates the concept with a single hiddenlayer. The input to the hidden layer is the input data x and the output of the hidden layer f1 serves asthe input data to the output layer, which itself is formed by GPs.

Exact inference is infeasible in GPs for large datasets due to the high computational cost of workingwith the inverse covariance matrix. Instead, the posterior is approximated using a small set of pseudodatapoints (100) also referred to as inducing points [Snelson and Ghahramani, 2006, Titsias, 2009,Quinonero-Candela and Rasmussen, 2005]. We assume this inducing point framework throughoutthe paper. Predictions are made using the inducing points to avoid computing the covariance matrixof the whole dataset. Both in GPs and DGPs, the inducing outputs are treated as latent variables thatneed to be marginalized.

The current state-of-the-art inference method in DGPs is Doubly Stochastic Variation Inference(DSVI) [Salimbeni and Deisenroth, 2017] which has been shown to outperform Expectation Prop-agation [Minka, 2001, Bui et al., 2016] and it also has better performance than Bayesian NeuralNetworks with Probabilistic Backpropagation [Hernandez-Lobato and Adams, 2015] and BayesianNeural Networks with earlier inference methods such as Variation Inference [Graves, 2011], Stochas-tic Gradient Langevin Dynamics [Welling and Teh, 2011] and Hybrid Monte Carlo [Neal, 1993].However, a drawback of DSVI is that it approximates the posterior distribution with a Gaussian. Weshow, with high confidence, that the posterior distribution is non-Gaussian for every dataset thatwe examine in this work. This finding motivates the use of inference methods with a more flexibleposterior approximations.

In this work, we apply an inference method new to DGPs, Stochastic Gradient Hamiltonian MonteCarlo (SGHMC), a sampling method that accurately and efficiently captures the posterior distribution.In order to apply a sampling-based inference method to DGPs, we have to tackle the problem ofoptimizing the large number of hyperparameters. To address this problem, we propose MovingWindow Monte Carlo Expectation Maximization, a novel method for obtaining the MaximumLikelihood (ML) estimate of the hyperparameters. This method is fast, efficient and generallyapplicable to any probabilistic model and MCMC sampler.

One might expect a sampling method such as SGHMC to be more computationally intensive than avariational method such as DSVI. However, in DGPs, sampling from the posterior is inexpensive,since it does not require the recomputation of the inverse covariance matrix, which only depends on

1Image source: Daniel Hernandez-Lobato

2

Figure 1: (Left): Deep Gaussian Process illustration1. (Middle): Histograms of a random selection ofinducing outputs. The best-fit Gaussian distribution is denoted with a dashed line. Some of themexhibit a clear multimodal behaviour. (Right): P-values for 100 randomly selected inducing outputsper dataset. The null hypotheses are that their distributions are Gaussian.

resulting in a Bayesian ‘self-tuning’ covariance function that fits the data without any human input[Damianou, 2015].

The deep hierarchical generalization of GPs is done in a fully connected, feed-forward manner. Theoutputs of the previous layer serve as an input to the next. However, a significant difference fromneural networks is that the layer outputs are probabilistic rather than exact values so the uncertainty ispropagated through the network. The left part of Figure 1 illustrates the concept with a single hiddenlayer. The input to the hidden layer is the input data x and the output of the hidden layer f1 serves asthe input data to the output layer, which itself is formed by GPs.

Exact inference is infeasible in GPs for large datasets due to the high computational cost of workingwith the inverse covariance matrix. Instead, the posterior is approximated using a small set of pseudodatapoints (100) also referred to as inducing points [Snelson and Ghahramani, 2006, Titsias, 2009,Quinonero-Candela and Rasmussen, 2005]. We assume this inducing point framework throughoutthe paper. Predictions are made using the inducing points to avoid computing the covariance matrixof the whole dataset. Both in GPs and DGPs, the inducing outputs are treated as latent variables thatneed to be marginalized.

The current state-of-the-art inference method in DGPs is Doubly Stochastic Variation Inference(DSVI) [Salimbeni and Deisenroth, 2017] which has been shown to outperform Expectation Prop-agation [Minka, 2001, Bui et al., 2016] and it also has better performance than Bayesian NeuralNetworks with Probabilistic Backpropagation [Hernandez-Lobato and Adams, 2015] and BayesianNeural Networks with earlier inference methods such as Variation Inference [Graves, 2011], Stochas-tic Gradient Langevin Dynamics [Welling and Teh, 2011] and Hybrid Monte Carlo [Neal, 1993].However, a drawback of DSVI is that it approximates the posterior distribution with a Gaussian. Weshow, with high confidence, that the posterior distribution is non-Gaussian for every dataset thatwe examine in this work. This finding motivates the use of inference methods with a more flexibleposterior approximations.

In this work, we apply an inference method new to DGPs, Stochastic Gradient Hamiltonian MonteCarlo (SGHMC), a sampling method that accurately and efficiently captures the posterior distribution.In order to apply a sampling-based inference method to DGPs, we have to tackle the problem ofoptimizing the large number of hyperparameters. To address this problem, we propose MovingWindow Monte Carlo Expectation Maximization, a novel method for obtaining the MaximumLikelihood (ML) estimate of the hyperparameters. This method is fast, efficient and generallyapplicable to any probabilistic model and MCMC sampler.

One might expect a sampling method such as SGHMC to be more computationally intensive than avariational method such as DSVI. However, in DGPs, sampling from the posterior is inexpensive,since it does not require the recomputation of the inverse covariance matrix, which only depends on

1Image source: Daniel Hernandez-Lobato

2

…

EIPV & DKL-GP VLSI Flow

Bayesian Opt.

Fig. 2 Overview of the proposed BOOM-Explorer.

B. Microarchitecture-aware Active Learning AlgorithmDue to the time-consuming VLSI flow, to save time, only

a limited number of designs will be synthesized practically toobtain power and performance. To guarantee that adequateinformation is covered in the data set, two principles areconsidered during the initialization. First, feature vectorsshould cover the entire design space uniformly. Second, theirdiversity should fully represent the characteristics of thedesign space. Within a limited time budget, only push themost representative microarchitecture to VLSI flow can wealleviate the burden to get power and performance.

A naive solution is to sample microarchitectures randomly.In literature, most previous works [18], [19] choose thissimple method directly for convenience. In addition, by ap-praising the importance of each feature vector with suitabledistance measurement, greedy sampling [20] can be facilitatedto select representative microarchitecture designs.

To further improve the sampling, orthogonal design [6],[21] is also utilized to pick up dissimilar microarchitecturesthat are distributed orthogonally across the design space.

Algorithm 1 TED(U, µ, b)

Require: U is the unsampled microarchitecture design space,µ is a normalization coefficient, and b is the number ofsamples to draw.

Ensure: X: the sampled set with |X| = b.1: X← ∅, Kuu′ ← f(u, u′), ∀u, u′ ∈ U;2: for i = 1→ b do3: x∗ ← arg max

x∈UTr[KUx(Kxx + µI)−1KxU]; . KUx,

Kxx and KxU are calculated via f w.r.t. correspondingcolumns in K

4: X← X ∪ x∗, U← U \ x∗;5: K← K−KUx∗(Kx∗x∗ + µI)−1Kx∗U;6: end for7: return The sampled set X;

Nevertheless, the aforementioned methodologies are failedto capture the key components of different microarchitec-tures that bring great impacts to the trade-off in the power-performance space.

Recently, witnessing the great performance improvementattained by transductive experimental design (TED) in thedesign space exploration of high-level synthesis [22], [23],compilation and deployment of deep neural networks [24],and etc., we introduce this method into the exploration ofmicroarchitectures for the first time.

TED tends to choose microarchitecture that can spreadacross the feature space to retain most of the informationamong the whole design space [16]. A pool of representativefeature vectors can be acquired with high mutual divergences,by iteratively maximizing the trace of the distance matrixconstructed on a newly sampled design and unsampled ones.Algorithm 1 shows the backbone of TED, where f representsthe distance function used in computing the distance matrixK. Note that any suitable distance functions can be appliedwithout restrictions.

Unfortunately, TED cannot fully guarantee to generate agood initial data set owing to a lack of prior knowledge ofmicroarchitecture designs. We are motivated to embed thedomain knowledge to improve its performance.

DecodeWidth as referred to in TABLE I decides the max-imal number of instructions to be decoded as correspondingmicro-ops simultaneously. In consequence, it can affect theexecution bandwidth of EU and LSU (i.e., instructions exe-cuted per clock cycle). Assigning a larger candidate value toDecodeWidth and allocating a balanced amount of hardwareresources, on the one hand, can lead to greater performanceimprovement. On the other hand, power dissipation will alsoincrease significantly. By clustering w.r.t. DecodeWidth, thepower-performance space can be separated along the poten-tial Pareto optimality, as shown in Fig. 3. Each cluster inFig. 3 represents a group of microarchitectures with differentcandidate values for DecodeWidth in the power-performancespace. The entire design space is discrete and non-smoothbut nonetheless a large number of microarchitectures withthe same DecodeWidth achieve similar power-performance

6 7 8 9

·104

0.04

0.08

0.12

Average Clock Cycles

Ave

rage

Pow

er(u

nit:

wat

ts) DecodeWidth = 1

DecodeWidth = 2DecodeWidth = 3DecodeWidth = 4DecodeWidth = 5

Fig. 3 Clustering w.r.t. DecodeWidth

characteristics within their sub-regions respectively. It inspiresus that we can select microarchitectures on the possiblesub-area from the initial design space, to better cover theentire design space at the same time improve the diversityof samples.

Inside each cluster, Algorithm 1 can be applied insteadof choosing the centroid to enlarge the initial data set. Theclustering w.r.t. DecodeWidth, together with TED, formsMicroAL and the pseudo code is detailed in Algorithm 2.

First, we cluster the entire design space according to Φ,which is the distance function with a higher penalty alongthe dimension of DecodeWidth. One possible alternative canbe Φ = (xi − cj)TΛ(xi − cj), with i ∈ 1, · · · , |U| andj ∈ 1, · · · , k, where Λ is a pre-defined diagonal weightmatrix. Next, we apply TED for each cluster to sample themost representative feature vectors, i.e., line 9 in Algorithm 2.Finally, containing all of the sampled microarchitectures, theinitial data set is formed.

C. Gaussian Process with Deep Kernel Learning

Given the initial data set, it is hard to build a reliable modelto fully capture the characteristics of the design space yet.

However, thanks to robustness and non-parametric approxi-mation features reside in Gaussian process (GP) models, theyhave been applied in various domains [24]–[26]. In view ofthe success, BOOM-Explorer adopts GP as well.

Assume that we have feature vectors X = x1,x2, ...xnand they index a set of corresponding power or clock cyclesy = y1, y2, ..., yn. GP provides a prior over the valuefunction f as f(x) ∼ GP(µ, kθ), where µ is the meanvalue and the kernel function k is parameterized by θ. Then,Gaussian distributions can be constructed with any collectionof value functions f according to Equation (2)

f = [f(x1), f(x2), ...f(xn)]T ∼ N(µ,KXX|θ), (2)

where KXX|θ is the intra-covariance matrix among all featurevectors and calculated via

[KXX|θ

]ij

= kθ(xi,xj). A Gaus-sian noise N(f(x), σ2

e) is necessary to model uncertainties ofpower or clock cycles generated by different microarchitecturedesigns. Thus, given a newly sampled feature vector x∗, thepredictive joint distribution f∗ that depends on y can be

Algorithm 2 MicroAL(U, µ, b)

Require: U is the unsampled microarchitecture design space,µ is a normalization coefficient, b is the number ofsamples that to draw.

Ensure: X: the sampled set with |X| = b.1: X← ∅;2: initialize k clusters randomly with the centroids set C =c1, c2, ..., ck from U;

3: while not converged do4: ci = arg min

j∈1,2,...,kΦ (xi − cj), ∀xi ∈ U; . Φ is the

distance function considering DecodeWidth

5: cj =

|U|∑i=1

1ci=jxi

|U|∑i=1

1ci=j, ∀j ∈ 1, 2, ..., k;

6: end while7: C← neighborhood of ci ∈ C, ∀i ∈ 1, 2, ..., k;8: for K in C do9: X = TED(K, µ, b bk c); . Algorithm 1

10: X = X ∪ X;11: end for12: return The sampled set X;

calculated according to Equation (3)

f∗|y ∼ N(

[µµ∗

],

[KXX|θ + σ2

eI KXx∗|θKx∗X|θ kx∗x∗|θ

]). (3)

By maximizing the marginal likelihood of GP, θ is opti-mized to sense the entire design space. Nevertheless, theperformance of GP normally depends on the expressivenessand hyper-parameters of kernel functions kθ, e.g., radial biasfunctions, and etc. Therefore, a suitable kernel function isnecessary to the performance of GP.

In the recent years, deep neural networks (DNN) haveshown great potential in various applications and tasks as theblack-box model to extract useful features [27]–[29]. Thus,with the help of DNN as a meta-learner for kernel func-tions, we can relieve workloads in tuning hyper-parametersof kernel functions. By leveraging multi-layer non-lineartransformations and weights to calibrate kernel functions withEquation (4) [30], deep kernel functions can provide betterperformance.

kθ(xi,xj)→ kw,θ(ϕ(xi,w), ϕ(xj ,w)) (4)

ϕ in Equation (4) denotes non-linear transformation layersstacked by DNN and w denotes weights in DNN. Enhancedwith the expressive power of DNN, DKL-GP is constructedand then plugged into Bayesian optimization as the surrogatemodel.

D. Correlated Multi-Objective Design Exploration

Notwithstanding DKL-GP can be used to evaluate a singleobject (i.e., power or clock cycles) well, to find the Pareto-optimal set still remains an issue, especially for such nega-tively correlated objectives.

Clock Cycles

Power

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(a)

Clock Cycles

Power

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(b)

Fig. 4 An example of Pareto hypervolume is shown in thepower-performance space. (a) The region covered in orangeis dominated by the currently explored Pareto-optimal setdenoted as circles in blue. Circles in red denote dominatedmicroarchitecture designs. (b) The circle in green denotes anexplored potential candidates of the Pareto-optimal set amongthe entire design space. EIPV is represented as the area ofsub-region colored in light green.

A traditional methodology usually integrates different ac-quisition functions to solve it. Lyu et al. [31] combinesExpectation Improvement (EI), Probability Improvement (PI)and Confidence Bound (i.e., UCB and LCB) to form a multi-objective optimization framework in analog circuit design. Itstill leads to sub-optimal results except that we can selecta good composite of acquisition functions for specific prob-lems. To solve the problem more efficiently, we introduceExpected Improvement of Pareto Hypervolume (EIPV) [32]and demonstrate its usability to characterize the trade-off inthe power-performance space of different microarchitecturedesigns.

In our problem, a better microarchitecture can not onlyrun faster (i.e., it gets fewer average clock cycles among allbenchmarks) but also dissipate less power. Given a referencepoint vref ∈ Y, Pareto hypervolume bounded above fromvref is the Lebesgue measure of the space dominated by thePareto optimality as shown in Fig. 4(a) [33]. The shaded areain orange, indicating Pareto hypervolume w.r.t. the currentPareto-optimal set P(Y) is calculated by Equation (5)

PVolvref(P(Y)) =

∫Y

1[y < vref][1−∏

y∗∈P(Y)

1[y∗ y]]dy,

(5)where 1(·) is the indicator function, which outputs 1 if itsargument is true and 0 otherwise.

vref is carefully chosen for convenience of calculation.Ideally, a feature vector x′ that can increase the likelihoodof DKL-GP maximally should be picked up from the de-sign space D in every iteration. Thus, a better predictivePareto-optimal set, enveloping the previous one by improvingPVolvref(P(Y)) is the direct solution according to Equation (6)where f : x→ y ∈ Y is denoted as DKL-GP. Then the featurevector x∗ = arg max

x′∈DEIPV(x′|D) can be sampled as a new

candidate for the predictive Pareto optimality.

Algorithm 3 BOOM Explorer(D, T, µ, b)

Require: D is the microarchitecture design space, T is themaximal iteration number, µ is a normalization coefficientand b is the number of samples to draw.

Ensure: Pareto-optimal set X that forms Pareto optimalityamong D.

1: X0 ←MicroAL(D, µ, b); . Algorithm 22: Push X0 to VLSI flow to obtan corresonding power and

clock cycles Y ;3: L←X0;4: U← D \ L;5: for i = 1← T do6: Establish and train DKL-GP on L with Y ;7: x∗ ← arg max

x∈UEIPV(x|U); . Equation (7)

8: Push x∗ to VLSI flow to obtain corresponding powerand clock cycles and add to Y ;

9: L← L ∪ x∗, U← U \ x∗;10: end for11: Construct Pareto-optimal set X from L;12: return Pareto-optimal set X;

EIPV(x′|D) = Ep(f(x′)|D)[PVolvref(P(Y) ∪ f(x′))

− PVolvref(P(Y))].(6)

By decomposing the power-performance space as grid cellsshown in Fig. 4, Equation (6) can be further simplified asEquation (7)

EIPV(x′|D) =∑C∈Cnd

∫C

PVolvC (y)p(y, |D)dy, (7)

where Cnd denotes non-dominated cells. Region colored ingreen as referred to Fig. 4(b) shows the improvement ofPareto hypervolume. In Equation (7), p(y|D) is modeled asa multi-objective GP for power and clock cycles where thekernel function in Equation (4) parameterized by DNN canbe Matern 5/2 kernel.

Equipped with all aforementioned methodologies, Algo-rithm 3 provides the end-to-end flow of BOOM-Explorer. Wefirst leverage Algorithm 2 to sample representative microar-chitectures (e.g., different branch prediction capability, cacheorganization, various structures of issue unit, etc.). DKL-GPis then built to characterize the design space. Finally, withBayesian optimization, the Pareto-optimal set is explored viathe maximization of EIPV.

IV. EXPERIMENTS

We conduct comprehensive experiments to evaluate the pro-posed BOOM-Explorer. Chipyard framework [34] is leveragedto compile various BOOM RTL designs. We utilize 7-nmASAP7 PDK [35] for the VLSI flow. Cadence Genus 18.12-e012 1 is used to synthesize every sampled RTL design, andSynopsys VCS M-2017.03 is used to simulate the designrunning at 2GHz with different benchmarks. PrimeTime PXR-2020.09-SP1 is finally used to get power value for allbenchmarks.

6 7 8 9

·104

0.04

0.08

0.12

Average Clock Cycles

Ave

rage

Pow

er(u

nit:

wat

ts) Design Space

Real ParetoSVRXGBoostRandom ForestDAC’19 [36]DAC’16 [6]HPCA’07 [19]ASPLOS’06 [18]BOOM-Explorer

Fig. 5 Learned Pareto optimal set of BOOM microarchitec-tures.

A. Benchmarks and BaselinesSince it is time-consuming to verify every sampled mi-

croarchitecture design online, we construct an offline data set.Consisting of 994 legal microarchitectures, the offline data setis sampled randomly and uniformly from the BOOM designspace as referred to in TABLE I. Each design is fed to theVLSI flow to get power and clock cycles with high fidelityfor all benchmarks and the corresponding time to conductthe flow is also recorded. The VLSI flow for each designtakes approximately from 6 hours to more than 14 hoursto finish. All of experiments are conducted on this data set.Several benchmarks are selected to test the performance ofmicroarchitectures, i.e., median, mt-vvadd, whetstone,and mm from commonly used CPU benchmark suites. Thesefour benchmarks are complete to all RISC-V instructions,e.g., instructions that transfer data between registers and mem-ory, floating-point manipulations, multi-threading executions,vector instructions, etc. The average clock cycles and poweron the four benchmarks are denoted as the performance andpower value for each design respectively.

Several representative baselines are compared with BOOM-Explorer. The ANN-based method [18] (shorted as ASP-LOS’06), stacks ANN to predict the performance of designs,including a complicated chip multiprocessor. The regression-based method [19] (termed HPCA’07), leverages regressionmodels with non-linear transformations to explore the power-performance Pareto curve on POWER4/POWER5 designs.The AdaBoost-RT-based method [6] (abbreviated as DAC’16),utilizes OA sampling and active learning-based AdaBoost re-gression tree models to explore microarchitectures w.r.t. theirperformance. The aforementioned arts are proved effective intheir works of the exploration of microarchitectures respec-tively. Therefore, it is requisite to compare these method-ologies with BOOM-Explorer. The HLS predictive model-based method [36] (named DAC’19), exploring the high-levelsynthesis design is also chosen as our baseline. Although thestarting point is different, their method is proved to be robustand transferable. Moreover, we also compare BOOM-Explorerwith traditional machine learning models, i.e., support vectorregression (SVR), random forest, and XGBoost [37]. For faircomparisons, experimental settings of the baselines are the

TABLE III Normalized Experimental Results

Methodologies Normalized ADRS Normalized ORT +

SVR 0.2399 1.0000Random Forest 0.2263 0.9763

XGBoost 0.2171 1.010ASPLOS’06 [18] 0.1948 0.9437

HPCA’07 [19] 0.1907 0.8544DAC’16 [6] 0.1473 3.0102DAC’19 [36] 0.1884 0.8973

BOOM-Explorer w/o MicroAL 0.1441 0.3307BOOM-Explorer 0.1145 0.3556

+ ORT: Overall Running Time

same as those mentioned in their papers. Simulated anneal-ing is leveraged for traditional machine learning algorithms,e.g., SVR, Random Forest, and XGBoost.

B. Experiments SettingsIn the settings of BOOM-Explorer, DKL-GP is stacked

with three hidden layers, each of which has 1000, 500, and50 hidden neurons respectively, and it adopts ReLU as thenon-linear transformation for deep kernel learning. The Adamoptimizer [38] is used, with an initial learning rate equalsto 0.001. DKL-GP is initialized with 5 microarchitecturessampled according to MicroAL and then BOOM-Explorerperforms Bayesian exploration with 9 rounds sequentially. Allexperiments together with baselines are repeated 10 times andwe report corresponding average results.

Average distance to reference set (ADRS) and overallrunning time (ORT) are two metrics for performance com-parisons. ADRS, as shown in Equation (8), is widely usedin design space exploration problems to measure how closea learned Pareto-optimal set to the real Pareto-optimal set ofthe design space.

ADRS(Γ,Ω) =1

|Γ|∑γ∈Γ

minω∈Ω

f(γ, ω), (8)

where f is the Euclidean distance function. Γ is the realPareto-optimal set and Ω is the learned Pareto-optimal set.ORT measures the total time of algorithms including initial-ization and exploring.

C. Results AnalysisFig. 5 shows the learned Pareto-optimal sets obtained by

the baselines and BOOM-Explorer. The results show that thePareto-optimal set learned by BOOM-Explorer is much closerto the real Pareto-optimal set and thus outperforming baselinesremarkably.

The normalized results of ADRS and ORT are listedin TABLE III. BOOM-Explorer outperforms ASPLOS’06,HPCA’07, DAC’16, and DAC’19 by 70%, 66%, 29%, and64% in ADRS, respectively. Meanwhile, it accelerates theexploring by more than 88% compared with DAC’16. Sincethe prior knowledge of BOOM microarchitecture designs isembedded in our method, DKL-GP can outperform baselinesby a large margin in ADRS and ORT. The effectivenessof the proposed MicroAL is demonstrated by conductingcomparative experiments of BOOM-Explorer with randomsampling instead of MicroAL. The corresponding results are

TABLE IV Comparison with two-wide BOOM

Micro-architecture Design Design Parameters + Average Power (unit: watts) Average Clock Cycles

Two-wide BOOM [4, 16, 32, 12, 4, 8, 2, 2, 64, 80, 64, 1, 2, 1, 16, 16, 4, 2, 8] 6.0700× 10−2 74915.2963

Pareto Design * [4, 16, 16, 8, 2, 8, 2, 2, 32, 64, 64, 1, 3, 1, 24, 24, 8, 4, 8] 5.8600× 10−2 73333.7407+ The parameters are in the same order as TABLE I* Pareto Design is found by BOOM-Explorer

mm

median

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Two-wide BOOM Pareto Design

mm

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Fig. 6 Comparisons of power and performance between the Pareto design found by BOOM-Explorer and the two-wide BOOM.

listed as BOOM-Explorer w/o MicroAL. The results showthat without MicroAL, the performance of BOOM-Explorerwould be close to DAC’16.

If a larger initialization set is sampled via MicroAL,BOOM-Explorer will be able to gain a better predictivePareto-optimal set. Finally, we can achieve different designsto strike good balances between power and performance.

D. The Optimal BOOM Microarchitecture DesignOur Pareto design is chosen from the Pareto-optimal set

found by BOOM-Explorer and it is compared with a two-wide BOOM developed by senior engineers [1].

The aforementioned two microarchitectures of BOOM arelisted in TABLE IV. Indicated by “Design Parameters” inTABLE IV, our Pareto design has the same DecodeWidthcompared with the two-wide BOOM. However, the Paretodesign reduces hardware components on the branch predictor(i.e., RasEntry, BranchCount, etc.), entries of the reorderbuffer, etc., but enlarges instructions issue width, LDQ, STQ,etc. Moreover, it has different cache organizations, e.g., dif-ferent associate sets. Because LSU introduced in Section II-Atends to become a bottleneck, the Pareto design increaseshardware resources for LDQ, STQ, and meanwhile increasesassociate sets and MSHR entries for D-Cache to overcomemore data conflicts. Furthermore, the Pareto design reducesresources of RAS and BTB since there are not many branchesor jump instructions in these benchmarks. Via reducing redun-dant hardware resources while increasing necessary compo-

nents, our Pareto design achieves a better trade-off on powerand performance.

To demonstrate the superiority of the Pareto design com-pared with the two-wide BOOM, both of them are evaluatedon more benchmarks, and TABLE IV shows the averagepower and clock cycles of all these benchmarks. Thesebenchmarks are chosen from different application scenarios,e.g., add-int, add-fp, etc. are from ISA basic instructions, iir,firdim, etc. are from DSP-oriented algorithms [39], compress,duff, etc. are from real-time computing applications [40],etc. Fig. 6 shows the comparison of power and performancebetween them. For all of these benchmarks, our Pareto de-sign runs approximately 2.11% faster and at the same timedissipates 3.45% less power than the two-wide BOOM.

V. CONCLUSIONS

In this paper, BOOM-Explorer is proposed to search forPareto optimality among the microarchitecture design spacewithin a short time. To the best of our knowledge, this isthe first work introducing automatic design space explorationsolution to the RISC-V community. We expect to see a lot ofresearches in our community to further improve microarchi-tecture design space explorations of processors.

ACKNOWLEDGMENT

This work is partially supported by HiSilicon and The Re-search Grants Council of Hong Kong SAR CUHK14209420,CUHK14208021.

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