1 RF Wireless Receivers in CMOS a prospective from the University of Pavia Rinaldo Castello Professor and Scientific Director of the University of Pavia-STMicroelectronics Joint Research Laboratory
1
RF Wireless Receivers in CMOSa prospective from the
University of Pavia
Rinaldo CastelloProfessor and Scientific Director of the University of Pavia-STMicroelectronics
Joint Research Laboratory
2
Presentation Outline
• Evolution of CMOS technology
• A CMOS Direct Conversion Receiver front-end for UMTS
• UMTS Receiver with on-chip LO
• A 2.5 dB NF Differential CMOS LNA with no External Components
• A CMOS Receiver Front-End with Current Mode Passive Mixer
• Conclusions
3
Wireless Terminals Evolution Multi-Mode (WAN, LAN, PAN, GPS etc.) Multi-standard (GSM, DCS1800, WCDMA etc)
Requires Terminals with: Different programmable characteristics e.g. Carrier frequency, Linearity, Bandwidth,
Sensitivity, Accuracy and matching etc. Reduced Power consumption, Area and Cost
Higher Integration/Riconfigurabilty in the Cheapest Technology i.e: CMOS
4
Higher Integration in CMOS Requires
• New system concepts e.g. self-calibration, adaptivity
• New architectures e.g. direct conversion, wide-band conversion
• New circuits techniques e.g. fully differential • Better (i. e. scaled) technologies e.g. higher fT
and fMax
• Better passive components e.g. varactors, inductors and transformers
7
Measured ft and fMaxvs. Channel LengthWoerlee et al. Trans. on E.D. August 2001
8
Simulated ft and 50 W NFvs. Channel Length
Woerlee et al. Trans. on E.D. August 2001
9
1/f noise vs. TechnologyMeasurements and Simulations
Woerlee et al. Trans. on E.D. August 2001
10
Active DevicesBipolar - CMOS Comparison
For the same level of technology scaling compare: fT, fMax, gm/I, gm x fT, noise (White and 1/f)
fT a bit lower in MOS, fMax lower in MOSgm/I lower in MOS gm x fT much lower in MOSNF similar but Rn higher in MOS 1/f noise much worse in MOS
Evolution of MOS with scalinggm x fT improves fast, 1/f & white noise degradefT increase faster than fMax
11
Bipolar vs Scaled CMOS DevicesThe difference in most parameters is reduced by
CMOS scalingBipolars are still superior in these respects-High fT and simultaneously high gm but CMOS is improving very fast-1/f noise and white noise (which becomes evenmore troublesome with scaling)Scaled CMOS becomes superior in this respectComplementary device is improving with scaling
In RF design the chioce cannot be made a priori
12
Passive DevicesMOS Varactors
L
VG
VS
0.7 mm channel length in a 0.35 mm ProcessTuning range : 2.2:1 in 2V, 3.1:1 in 3 V Minimum Q at 1.9 GHz : 23
14
Passive DevicesIntegrated Inductors
w ≅ 15µmS ≅ 2µmLs ≅ 200µm
Spiral Inductor on Silicon Substrate Polysilicon Shield under the Inductor
GaAs Subs.: Q > 20 @ 2GHzSi Low Doped Subs.: Q >10 Al Interconnect
Q >15 Cu InterconnectSi Highly doped Subs.: Q ≅ 4
15
Miniature 3D InductorsTang et al. JSSC April 2002
16
Future Evolution
• Easier standards e.g. WLAN, Blue tooth, DECT will soon evolve to a single chip in CMOS
• Difficult standard e.g. GSM, UMTS may go to single chip solutions in very deeply scaled technologies (0.18 mm or below)
Need to improve in the following areas• CAD for substrate noise and couplings • Better passives• New circuit topologies for very low voltage
17
Presentation Outline
• Evolution of CMOS technology
• A CMOS Direct Conversion Receiver front-end for UMTS
• UMTS Receiver with on-chip LO
• A 2.5 dB NF Differential CMOS LNA with no External Components
• A CMOS Receiver Front-End with Current Mode Passive Mixer
• Conclusions
18
UMTS Terrestrial Radio Access
TX RX
Direct Sequence Spread Spectrum
f
chip rate
f
bit rate
tCode
Spreading
tCode
De-spreading
f
Processinggain
f
• Chip Rate: 3.84Mcps• Variable Bit Rate: 8 / 384 kbps• Duplexing: FDD (full duplex)
Uplink: 1920-1980MHzDownlink: 2110-2170MHz
• Modulation: QPSK
19
Noise FigureTests conditions Processing Gain
dBBitRate
ChipRateGP 25==• Bit Rate 12.2kbps• Chip Rate (B) 3.84MHz• BER 10-3
• Minimum Signal -117dBm
Eb / N0 = 7dB
Noise Figure Derivation
SNRANALOG = Eb/N0 - GP = -18dB
Noise Floor = Min. Signal – SNRANALOG = -99dBm
NF = Noise Floor + 174dBm – 10 log(B) = 9dB
20
Out-of-band Blocking
f
Out-of-bandblockers
Received Signal
-114dBm(-117dBm)
-44dBm
-15dBm-30dBm-30dBm
-44dBm
-15dBm
TX Signal(+28dBm at peak)
2025MHz 2095MHz2050MHz
2185MHz 2255MHz2230MHz Duplexer
TX leakage
LNA
PA
-52dBm-55dBm
-50dBm
-27dBm Blockers atLNA input
Transmitter leakage (-27dBm) dominates out-of-band blockers and determines out-of-band IIP3 and IIP2 requirements.
21
Out-of band IIP3 Requirements
PATX signal
1920-1980MHz
28dBm(-27dBm)
LNA
Duplexer
1985 to2045MHz
2110 to2170MHz
RX signal-114dBm
blocker-30dBm
(-45dBm)
IIP3=-9dBm
-99dBm=2(-45dBm)-27dBm-2IIP3
IM3 = 2Pblocker + PTX - 2 IIP3
22
Desensitization due to TX leakage
Noise + IM2 < -99dBm
IM2 ≅ 2PTX - IIP2 –3
IIP2 ~ 48dBm Required
Received signal -117dBm
f
TX 2nd Order Intermodulation
Noise floor
3.84MHzTX leakage PTX = -27dBm
f
23
•10 bit A/D converter •6° order Butterworth LP filter
8dBm3.5nV/√Hz12dBMixer-1dBm2.5dB NF16dBLNA
IIP3NoiseGain
I
QLNA
VGA1 ADCVGA2LowPass
VGA1 VGA2
LOI
LOQ
ADCLowPass
ff0 f0+5MHzf0-5MHz
-52dBm
AdjacentChannels
-103dBm
ff0
-44dBm -44dBmReceived Signal
-52dBm
5MHz
-114dBm
-52dBm
Adjacent Channel Low-IF Architecture
RF section
Image Rejection 36dB
24
Direct Conversion
5
6
7
8
9
46 48 50 52IIP2 (dBm)
Requ
ired
NF(1
) (dB)
RF section
•6 bit A/D converter •4° order Butterworth LP filter
Quadrature Accuracy 23dB
8dBm5nV/√Hz10dBMixer-1dBm2.5dB NF18dBLNA
IIP3NoiseGain
(1) With peak TX power
I
QLNA
VGA1 ADCVGA2LowPass
VGA1 VGA2
LOI
LOQ
ADCLowPass
25
Direct Conversion
-130-110-90-70-50-30-101030
Antenn
aDup
lexer
Balun
LNA
Mixer
VGA
Filter
VGAIIADC
Pow
er [d
Bm]
Min Signal
Noise
Tx Leak.
Adj. Ch.
Blocker
A/D DRfading
TX leakage requires high linearity in the RF section. The adjacent channel set base-band and A/D dynamic range requirements.
26
Architectures Comparison Conclusions
• Adjacent Channel Low-IF and Direct Conversion: low image rejection requirements, suffer from second order intermodulation
• Adjacent Channel Low-IF: high dynamic range requirements in IF circuitry and ADC
• Direct conversion is the most suitable architecture for a UMTS receiver
27
CMOS Direct Conversion Front-end •Differential Topology
•DC offset cancellation loop
•0.18µm CMOS Technology
Servo-loop around the VGA implements a 3kHz high pass filter, removing DC offset and low frequency noise.
LO 0°
I
Q
LNA
VGA
VGA
Mixer I
Mixer Q
LO 90°Servo-loop
28
Low Noise Amplifier
Simulated CMRR = 44dB
Primary gain
control
•AC coupling filters out second order intermodulation products
•9dB gain variation with 1dB NF degradation
•IDISS = 4.5mA
•NF = 2.5dB
OUT+
VGAIN
2nH
2.8nH
Secondary gain
control
2nH
OUT-
IIP3(LC) > Fully Differential (-8dBm)
29
Direct down-conversion mixer
R
LO+ LO+LO-
R
RF+RF-
2mA IIP3 enhancement filter
w/o filterwith filter
200/0.34
IMIXER = 4mA
Shunted pMOS-nMOS transconductor for high IIP3 / noise
IIP3 limited by switching pairs
5nH
30
OUT
IN+ IN-
IFB
Offset-cancellation loop
C is realized on-chip with poly-well + metal-insulator-metal + lateral flux capacitors and occupies 0.1mm2
A
OUTVGA
Mixer load resistors
Mixer
R
C=450pFIFB
20/10
( )ARC
Gf LOOPHP π2
0=
GLOOP
Transfer function
31
Variable Gain Amplifier
M1 M2
1mA
IN-IN+
GainControl
Rs
Rout
1dBm4nV/√Hz0-16dBIIP3NoiseGain
• M1/2 operate in weak inversion to maximize gm.
• Rout/Rs sets minimum gain (0dB)
Design targets
32
Die Microphotograph
LNALNA I&Q I&Q MixerMixer
I&Q I&Q VGAVGA
Total chip area = 16mm2
4.7mm3.
4mm
33
Receiver Gain Measurements
5101520253035404550
1.7 1.8 1.9 2.0 2.1 2.2 2.3fRF [GHz]
Gai
n [d
B]
MAX GAINLNA min GAINMin GAIN
9.3dB
19.8dB
20304050
IF [Hz]
Gain
[dB]
100 1k 10k 100k
Lower frequency of peak gain due to LNA LC load variation.
Peak gain at TX frequency.
2.6kHz high pass frequency
34
-50-30-10103050
-70 -50 -30 -10Pin [dBm]
Pout
[dBm
]
IIP3 = -2dBm
Out-of-band 3rd order intermodulation
Received signal
2.11GHz
Blocker
TX leakage
3rd Order Intermodulation
1.98GHz 2.11GHz f
IM3 = 2Pblocker + PTX - 2 IIP3
IIP3 = -2dBm-112.8dBm = 2(-45dBm)-27dBm-2IIP3
35
4045505560
1 2 3 4 5 6 7Sample
IIP2
(dB
m)
Out-of-band 2nd order intermodulation
TX leakage
1.98GHz
Pin
f
Received signalPin
2.1005GHz f
-60
-20
20
60
100
-90 -70 -50 -30 -10 10 30 50Pin [dBm]
Pout
[dBm
] IIP2 = 48.8dBm
IM2 = 2PTX - IIP2
-102.8dBm = 2(-27dBm) - IIP2
IIP2 = 48.8dBm
36
-50-30-10103050
-70 -50 -30 -10
Pin [dBm]
Pout
[dB
m]
In-band 3rd order intermodulation
Received signal
2.11GHz
Pin
3rd Order Intermodulation
2.08GHz 2.11GHz f
2.09GHz
Pin
IIP3 = -6dBm
In-band IIP3 requirement = -18dBm
37
Measurements: noise
-172-170-168-166-164-162-160-158-156-154-152
f [Hz]
Inpu
t Ref
erre
d N
oise
PSD
[dB
m/H
z]
246810121416182022
Spot
Noi
se F
igur
e [d
B]
500k 1M 1.5M0 2M
DSB-NF 6.2dB (10kHz-1.92MHz)
DSB-NF 4.8dB (200kHz-1.92MHz)
38
Noise Contributions
0
20
40
60
80
Measurements Simulations
Con
trib
utio
n (%
)
LNA
Mixer
VGA VGA
MixerLNA
DSB-NF = 6.2dB DSB-NF = 4.5dB
Lower LNA gain LNA has increased noise contributions from following stages.
39
Performance Summary
LNA33%
Mixer54%
VGA13%
44dBGain
64dBLO-RF isolation
0.18µm 6M CMOSTechnology
16mm2Active Area
27mWPower
+48.8dBmIIP2
-2dBmIIP3
4.8dB * 6.2dB **NF
Power consumption breakdown
* Integrated between 200 kHz and 1.92 MHz** Integrated between 10 kHz and 1.92 MHz
40
Conclusion
• A 0.18µm CMOS Receiver Front-End with 6.2dB NF, IIP3 = -2dBm, IIP2 = 48dBm, for UMTS has been demonstrated
• The Duplexer performances determine linearity requirements
• A solution comprising the local oscillator on the same chip will have to address self mixing to preserve the IIP2 performance.
41
Presentation Outline
• Evolution of CMOS technology
• A CMOS Direct Conversion Receiver front-end for UMTS
• UMTS Receiver with on-chip LO
• A 2.5 dB NF Differential CMOS LNA with no External Components
• A CMOS Receiver Front-End with Current Mode Passive Mixer
• Conclusions
42
Front-end Block Diagram
0°
90°
: 2 VCOLNA
QVGA
IVGA
43
VCO and I&Q Dividers
Vc
2mA
AmplitudeReference
Mixer LO inputcap.
M1Q
Mixer LO inputcap.
M1I
VCOI DIVIDER Q DIVIDER
40u/0.25u 40u/0.25u
5nH 5nH 5nH 5nH2.1nH 2.1nH
300fF300fF
21u/0.2u80u/0.2u
n-well
p-substrate
Vc
VddLO
21u/0.2u80u/0.2u 80u/0.2u 80u/0.2u
Cbypass
n+ n+
600Ω 600Ω
300fF300fF
600Ω 600Ω
44
Die Microphotograph
LNAI&Q
Mixer and
dividersVCO
VGA + servo loop
45
VCO PN 130 MHz from Carrier
PN130MHz= NRM[dBm] –10log(BW) – Tleak[dBm] = -156.8 dBc/Hz
-170
-169
-168
-167
-166
-165
-27 -22 -17 -12
Input Power [dBm]
Nois
e Po
wer
Spe
ctra
l Den
sity
[d
Bm/H
z]
+3 dB
TX=-13dBm
Input referred noise power spectral density at 2MHz vs. the power of a tone, 132 MHz away from receiver
46
Dividers Oscillation Frequency vs. Varactor Control Voltage
1,75
1,8
1,85
1,9
1,95
2
0 0,3 0,6 0,9 1,2 1,5 1,8Varactor control voltage [V]
Div
ider
s O
scil.
Fre
q. [G
Hz]
47
Performance Summary
0.18µm CMOS0.18µm CMOSTechnology
16mm216mm2Active area
37.8mW27mWPower
47dB44dBGain
+48dBm+48.8dBmIIP2
-2dBm-2dBmIIP3
4.4dB* 5.6dB**4.8dB* 6.2dB**NF
Front-end with on-chip LO
Front-end
* Integrated between 200KHz and 1.92 MHz
** Integrated between 10KHz and 1.92 MHz
48
Presentation Outline
• Evolution of CMOS technology
• A CMOS Direct Conversion Receiver front-end for UMTS
• UMTS Receiver with on-chip LO
• A 2.5 dB NF Differential CMOS LNA with no External Components
• A CMOS Receiver Front-End with Current Mode Passive Mixer
• Conclusions
RF NoiseModel
(stronginversion)
mg Vgs SS idig
GSC
GSR
V V
V
g V
g d
s
Inductively degeneratedinput stage:for typical currentlevelstheMOSdevicesarenot in stronginversion (
! " " #
)
ModerateInversion $ shotnoiseappears(MM9)
%& ' ()*+ ,).- /10 )32 4
56 %& ' ()7* + ,)- / 0 )32 4 8 9;: < >= 55 6 %& ' ( )7*+ ,)- /10 )32 4
@? A = % BDC E FG HJI GK L FNM I EO H LG.P L Q
49
Input StageNoisePerformances
R? SUT V = WX
Y[Z - \ ]
(At resonance)
RSW/L
LG
CGSSig
LS
Sid
IBIAS
Z in
RF source
Inductive degeneratedinput stage:goodcompromisebetweeninputmatchingandnoisefigure
^`_ a bc de
fhgfjib k lnmpo q r@s e t ud v bc w l tmpo x c yo zm|y~ g c k e s
dyo zm| uy~ g
(1)
where and ? 5\ ]
.
50
Fixed Power NF Optimization
In mostcaseswearein moderateinversion!
Neglectingtheshotnoiseleadsto adifferentoptimumnoisebiasing.
100 200 300 400 500 600 700 800 900 1000 1100 1200 1300Width [um]
0.5
1
1.5
2
2.5
NF [dB]
Model valid in the entire region of operationStrong Iinversion model
MODERATE INVERSION
I=4 mARs=50 f=900 MHz
Ω
51
NoiseOptimization Summary
For a given
WX andassumingmatchingconditions,thereis an
optimumgatewidth which producesaminimumin NF;
If theMOSis in moderateinversion,shotnoisecontribution is
not neglectible andit hasto betakeninto accountin the
determinationof theoptimum gatewidth;
Oncetheoptimumgatewidth hasbeenchoosen, theonly way
to reducetheNF is to increasethebiasingcurrent,which
increasesthedevice transition frequency ( Sp );
Theabsoluteminimumachievablenoisefigurecorrespondstothedevicesworking at their peaktransition frequency ( S Z & ).
52
PMOS–NMOS Input Stage
Hypothesis: S ' = S ?2L*S 2L*S
2L*S
2L*S
b)
LG
2I
W,
a)
LG
I
W,
L S L*S
c)
LG W/2 W/2
I I
d)
LGW/2
W/2
I
I
ω∗TωT
DecreasingNF Currentreuse
pMOS–nMOSinput stageachievesthesameNF, linearityand
transconductancegain of thenMOSone,using half thecurrent;
Technologyscalingmakesthehypothesis ( S ' = S ? ) more
andmorerealistic.
53
PMOS–NMOS Advantages
LGWp
Wn
I
I
L Sp
L Sn
Higher S $ MOS lessnoisy;
Higher
$ MOSmorelinear;
pMOS
higher thannMOS
$ pMOSlesssensitive to shortchanneleffects;
pMOSshotnoiselowerthannMOSone( ' !
? ).
54
Schematic
Pseudo–differential topology;
p–n cascodestage;
Lx Cx
LxCx
IN+ IN−OUT− OUT+Lg Lg
Lsp Lsp
Ll Ll
Cl Cl
MRFn MRFn
MRFpMRFp
MCn
MCpMCp
MCn
Lsn Lsn
Ibias
CASCPGATEP+
GATEP−
CMGATEN+
CASCNGATEN−
BIASINGNETWORK
55
Layout
Layoutassymmetricaspossible;
Octagonalspiral inductorswith poly shield.
56
61
Presentation Outline
• Evolution of CMOS technology
• A CMOS Direct Conversion Receiver front-end for UMTS
• UMTS Receiver with on-chip LO
• A 2.5 dB NF Differential CMOS LNA with no External Components
• A CMOS Receiver Front-End with Current Mode Passive Mixer
• Conclusions
Receiver Description
Mandrake is anLNA + Mixer + First Filtering Stagebasedon acurrentdrivenpassive mixeranddesignedfor UMTS applications.
MAIN FEATURES
Pseudodifferentialarchitecture;
Fully integration in
RF–CMOStechnology;
No externalinput matchingnetwork;
Low power consumption: 8 mA from 1.8V voltagesupply.
62
Mandrake Block Diagram
RF ANTENNA
LNA MIXER
− +
+ − + −
− +
BALUN
BALUN
IF AMPLIFIER
CF
25 Ω
25 Ω
VIF
I
RFI
IIF
IIF
50 Ω
VLO
VRF
RF
RF
RF
63
CF
Passive Mixers vs Active Mixers
Classic passive mixer;No staticcurrentdissipation;High NF andlessthan0dB gain;High linearity;LargeLO driver required.
Active mixer;Staticcurrentdissipation;High conversiongain andlow NF;Morenoisesources(Flicker noise);Cleardesigntrade–off betweengain,noise,linearity andpower consumption.
65
72
Presentation Outline
• Evolution of CMOS technology
• A CMOS Direct Conversion Receiver front-end for UMTS
• UMTS Receiver with on-chip LO
• A 2.5 dB NF Differential CMOS LNA with no External Components
• A CMOS Receiver Front-End with Current Mode Passive Mixer
• Conclusions
73
Acknowledgements
The results reported in this presentation is due to the work of many people both at
the Univ of Pavia and at the Studio di Microelettronica:
for this I am very grateful
Here is a list of them:I.Bietti, M. Brandolini, S. Erba, F. Gatta, D. Manstretta,
P. Rossi, E. Sacchi, F. Svelto, P. Vilmercati,