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byReza Ghaffarian, Ph.D.
JPL-Caltech(818) 354-2059
[email protected]
NASA Electronic Parts and Packaging Program (NEPP )2nd Annual Electronics Technology Program (ETW)
June 28-30, 2011
Copyright 2011 California Institute of Technology
Government sponsorship acknowledged
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
Outline Package
Definition Trend
Hierarchy of req & reliability testing Mission/2nd level Package/Part
Advanced AAP reliability FCBGA Chip capacitor LGA/CGA assembly
Summary/Future Activities
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
• Norm Pitch for PWB• 0.4-1.27 mm
• Die Tight Pitch• Al Pad- Non Reflow
• Interposer• Polymer, Ceramic, Flex• Cu:Ni:Au Pad
• Wafer• Pitch limitation
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
PWBPWB
90Pb/10SnHigh melt 63Sn/37Pb
Eutectic 90Pb/10SnHigh Melt
Flip ChipFlip Chip
PWB
63Sn/37PbLead free
Wire Bond
Plastic BGA (PBGA)
Ceramic BGA (CBGA)
PWB
63Sn/37PbLead free
Flip Chip
Flip Chip BGA (FCBGA)
Column CGA (CCGA)
90Pb/10SnHigh Melt
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Reza Ghaffarian/JPL/CaltechRaytheon Workshop 4/27/2011- Internalhttp://america2.renesas.com/docs/files/FCBGA_brochure.pdf
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
Incr
easi
ng T
echn
ical
Cap
abili
ty
Wafer Level Packaging
FCBGA
Wire bondFlip chip in-pkg oron board (organic)
High I/O Flip chip BGAHigh I/O CCGA Wafer Level
Current Far Term
CBGA
PBGA
Chip Scale Packaging
(CSP)
Chip Scale
1-Development4- Hi Volume 3- Low Vol 2-Sample
D. Gerke/R. Ghaffarian, NASA NEPP Workshop, June 2010
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
Hierarchy of Reliability Testing
Assembly2nd Level
System/BoxMissions
Benign/ShortBenign/Long
Extreme/ShortExtreme/Long
TC/Mech Package
Board
Radiation/othersInterconnects
Part1st Level
DieInterposer
SMTPTH/HDI
InterconnectsUnderfill
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
System/Pkg Reliability Testing
Assembly2nd Level
AdvancedArea Array
SMT
Area arraySingle/Stack
PCBPTH/HDI
InterconnectsCBGA/CGAStake/Coat
Hermetic/NonCGA Class Y
>1000 I/O, 1mm pitch
Hermetic<1,000 I/O
InterposerInterconnectsLead & Lead-free
Part/Pkg1st Level
Chip CapUnderfillFC Balls
Interposer
LGA
FCBGA
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
Reliab Testing of Advanced AAP
FCBGA
• Assembled lead & lead-free • Completed thermal cycles/Drop Test• X-ray & X-sectional evaluation
LGA
• Column attach/pull test/age-pull test• CGA (two types) assembly onto PCB• LGA version
CGA
• Package/capacitors reliability evaluation• Successful Assembly• Environmental tests
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
PBGA to FCBGA
Limitation of PBGAs Wire bonds only periphery
Solution: Tier wire bonding, still limit for higher I/Os
Higher speed need No solution
FCBGA advantages Use area of die, larger I/Os than periphery Higher speed
Short electrical path: Low capacitance, inductance, resistance Accommodate higher I/Os >1000
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
PBGA to FCBGA FCBGA advantages Heat dissipation Die backside is exposed & good for heat spreader Heat spreader as hermetic seal
Additional cost due to underfill/heat spreader No standard for high-reliability applications
FCBGA drawbacks Heat spreader Underfill/hermeticity Another AAP/integrity verification
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
FCBGA1704
PBGA676 FCBGA1704
FCBGA1704
PBGA676PBGA676
PBGA676
FPBGA432
FPBGA432
FPBGA432
FPBGA432
FPBGA432
FPBGA432
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
Flip Chip BGA FCBGA 1704 I/O 1.0 mm pitch
Tin-lead
PWB
63Sn/37PbSAC 405/305
SAC105/SnAg
Wire Bond
Plastic BGA (PBGA)
PWB
63Sn/37PbSAC 405
Flip Chip
Flip Chip BGA (FCBGA)
Tin-lead
BGA- Wire bond: PBGA 676 I/O 1.0 mm /control FPBGA 432 I/O 0.4 mm/state-of-the-art
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Reza Ghaffarian/JPL/CaltechRaytheon Workshop 4/27/2011- Internal
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
LGA Reliability Testing Methods• Column attach: Two types
• Pull test/Age-pull test• CGA versions assemble onto PCB• LGA version
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CGA Reliability Testing• Package/chip capacitor reliability evaluation• Assemble onto PCB• Environmental testing
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
Two CGAs/Two Column Types
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
CGA with 31 Chip Capacitors
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
Chip Capacitor Solder JointsReceived Dec 2010
18/248 Joints
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SEM of a Capcitor
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
Solder Joint Composition
90 Pb10 Sn
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SEM of Capacitor Solder Joint
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SEM of Capacitor Solder Joint
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
Capacitor Joint after 200TCs
-55/130C, 10/10 min
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
Capacitor Solder JointsReceived May 2011, 0805 (6)/0603 (25)
7/248 Joints
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CGA Solder Joint Assembly
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
CGA Corner Solder Joints
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Failure of LCC Solder Joint
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
Summary FCBGA High assembly yield (Vapor/Rework Station) No failure to 200 cycles of
-55/100°C , -55/125°C -125/125°C -55/100°C TS Damage low by X-section/SEM Low segregation of tin-lead and lead-free balls after cycles
Failed after only one drop with 485g level
Advanced CGA No failure of chip capacitor to 200 TCs One solder joint separation
Successfuly Assembled onto PCB
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
Future Activites FCBGA
Released NEPP Report
Advanced LGA, CGA, HDI Reliability testing of CGA assemblies Complete column attachment on LGAs
Two column types & LGA, pull test verification Assemble onto standard PCB
Design boards with HDI (microvia) Assemble onto HDI board/optimize process Reliability testing
Active die, HDI, Reliability Use lessons learned for efficient resource utilization Release final report
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Reza Ghaffarian/JPL/CaltechNEPP ETW 6/29/2011 @ GSFC
The research described in this publication is being conducted at the Jet Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration.
Copyright 2011 California Institute of Technology. Government sponsorship acknowledged.
The author would like to acknowledge industry/university partners. Special thanks to the JPL fabrication and failure analysis lab personnel including Atul Mehta and Ronald Ruiz for their supports. The author also extends his appreciation to program managers of NASA Electronic Parts and Packaging Program (NEPP) including co-managers Michael Sampson and Kenneth LaBel at GSFC and Dr. Charles Barnes, and Phillip Zulueta at JPL for their continuous support and encouragement.