Review OTIS 1 - Physikalisches Institutuwer/Otis/TDC-Core.pdfTest chips for DLL,DLL with MUX and MEMORY : OTISDLL1.0 (Sept. 2000) OTISMEM1.0 (Feb. 2001) ¾1st DLL prototype, contains:

1Harald Deppe, Uwe Stange,

Ulrich Trunk, Ulrich Uwer Heidelberg University

Status of OTIS 1.0

OTIS Review2003, June 5

OTIS GROUP, Heidelberg University

2Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Heidelberg University

OTIS TDC Chip

Components:

32 maskable channels (LVDS Input)

DLL, HitRegister, PrePipeline:6 bit drift time encoding: 1 bit ↔ 0.39 ns (req. resolut. < 1ns)playback mode for testdata feed-in

Pipeline, Derandomizing Buffer:buffer length: 160 evts ↔ 4.0 µs

Control Algorithm:Memory and trigger management,2 read-out modes: 1, 2, 3 BX/evt

I2C Slow Control Interface:Programming, ASD bias setting

DAC: ASD-Chip bias

3Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Heidelberg University

OTIS TDC

3.250 OTIS-TDCs with 32 channels each4 OTIS TDCs are connected to one GOL(fast serializer chip) one fibre per 128 channelsRadiation hard layout 0.25 µm CMOSDLL fine time resolution 6 bitDual Ported Memory with 1.2 Gb/s,240 bit width (low power design)Synchronous clock driven readout

4Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Heidelberg University

Delay Locked Loop

Test chips for DLL,DLL with MUX and MEMORY :OTISDLL1.0 (Sept. 2000) OTISMEM1.0 (Feb. 2001)

1st DLL prototype, contains:Delay chain with 32 stages 1 taps eachMean delay per tap 25ns/32 = 780 psHit Register for only one channel

2nd DLL prototype, contains:Delay chain with 32 stages 2 taps eachMean delay per tap 25ns/64 = 390 psHit Register for only one channelwith 64 bit multiplexed to 4 pads

5Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Heidelberg University

DLL Lock Time (2nd prototype)

Lock Time is below 1µs

DLL Out

Clock In

Phase Difference

Control Voltage DLL

6Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Heidelberg University

DLL Temperature Range (2nd prototype)

Measurement of Temperature Range Control Voltage inside Dynamic Range for all tested Temperatures at 40 MHz

Vctrl vs Temp

0

200

400

600

800

1000

1200

1400

1600

1800

0 10 20 30 40 50 60 70 80 90 100T/°C

Tested with cooling spray

Vctrl

/mV Dynamit Range

7Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Heidelberg University

Measurements on OTIS 1.0

DLL Lock Range DLL Lock –TimeFineTime MeasurementsDifferential Non-Linearity

ALL limitations on the functionality of OTIS 1.0 concerning Finetime and HitBit encoding are due to parasitics.

8Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Heidelberg University

DLL Lock Time (OTIS 1.0)

Lock Time is below 1µs

DLL Out

notReset

Control Voltage

9Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Heidelberg University

DLL Lock Range (OTIS 1.0)

Lock Range = 25…60MHz at 300KSpec is 30…50MHz at 300K OK !!!

Dynamic Range of Control Voltage 1.4V

Vctrl vs. Frequenz

0,00

0,50

1,00

1,50

2,00

2,50

25 30 35 40 45 50 55 60

Frequenz in MHz

Vctr

l in

V

Dyn

amic

Ran

ge

10Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Heidelberg University

Fimetime Measurements (1)

Finetime Measurements for OTIS 1.0

Finetime vs Hitposition

0

10

20

30

40

50

60

70

0,0 5,0 10,0 15,0 20,0 25,0

Delay [ns]

Fine

time

[bin

]

Kanal 15

Kanal 16

11Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Heidelberg University

Finetime Measurements (2)

Finetime Measurements for an FIB patched OTIS 1.0

Finetime vs. HitpositionKanal 28 und 30 bei Clk_II-Delay = 13.0ns

StoreClk-Delay = 5.0ns

0

20

40

60

80

100

120

140

160

180

200

5,0 7,0 9,0 11,0 13,0 15,0 17,0 19,0 21,0 23,0 25,0 27,0 29,0 31,0

Hitdelay/ns

Fine

time

#

Kanal 30

Kanal 28

12Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Heidelberg University

Differential Non Linearity (1)

Differential Non-Linearity OTIS 1.0 (preliminary):DNL = 1.39 bin (= 0.54ns)

Histogram - Channel 28(64 bins; bin size corrected)

0

10000

20000

30000

40000

50000

60000

70000

80000

90000

100000

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63

Bin Number

Coun

ts

DNL OTIS 1.0 - Channel 28(64 bins; normalized; bin size corrected)

-1,0

-0,8

-0,6

-0,4

-0,2

0,0

0,2

0,4

0,6

0,8

1,0

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63

Bin Number

DN

L [B

in]

13Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Heidelberg University

Differential Non Linearity (2)

Differential Non-Linearity (corrected with Simulation results):DNL = 0.634 bin (= 247.3 ps)

Histogram Channel28

0

10000

20000

30000

40000

50000

60000

70000

80000

90000

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63

Bin Number

Coun

ts

(64 Bins, Bin size corrected) DNL(corrected) OTIS 1.0 Channel 28(64 Bins, bin size corrected)

-1,00

-0,80

-0,60

-0,40

-0,20

0,00

0,20

0,40

0,60

0,80

1,00

0 10 20 30 40 50 60

Bin Number

DN

L [b

in]

Max= 0.374 bins

Min= -0.260 bins

DNL= 0.634 bins = 247.3 ps

14Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Heidelberg University

Summary

OTIS 1.0 (TDC core)

Clock, Hit Signals differential

Lock Range 25...60 MHz

Lock Time < 1us

DNL 1.39 Bins (preliminary measurements),0.64 Bins (corrected by simulation results),further investigation necessary!!

Chan. To Chan. Variation < 1LSB(measured for 1st BX half)

Known Bugs: Drift time encoding for 2nd BX half andloss of HitBit information!Well understood!!! Signal routing and driver strength have to be improved. A more relaxed timing will be chosen for PrePipe-Components.

Status of OTIS 1.0OTIS TDC ChipOTIS TDCDelay Locked LoopDLL Lock Time (2nd prototype)DLL Temperature Range (2nd prototype)Measurements on OTIS 1.0DLL Lock Time (OTIS 1.0)DLL Lock Range (OTIS 1.0)Fimetime Measurements (1)Finetime Measurements (2)Differential Non Linearity (1)Differential Non Linearity (2)Summary