Review of 6T SRAM Cell

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 1

Review of 6T SRAM CellReview of 6T SRAM Cell

Ding-Ming KwaiIntellectual Property Library Company

June 3, 2005

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 2

Why 6T SRAM CellWhy 6T SRAM CellEmbedded memory

Easy to implement in generic CMOS processEasy to design as logic circuitEasy to test by finite-state machine

Compilable designFixed cell size to allow us dedicating in peripheral circuit designSynchronous interface since 0.35µm generation simplifies the designA larger number of instances required

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 3

OutlineOutline6T cell and its variants – First we generalize and then we derivePeripheral circuits – Utilization is the keyCell layout – To be symmetric or to be asymmetric: that is the questionPerformance indices – To judge is humanConcluding remarks – It does not end here

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 4

8T SRAM Cell8T SRAM CellMaking it completely complementaryMaking it completely complementary

Regenerative circuit for storing a single bit: two equal-sizedinvertersAccess device to transfer the bit: two equal-sizedtransmission gates

pass transistors

WL

WL

WLBLBL

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 5

Intel, 1975NEC, 1969

What Have Been InventedWhat Have Been Invented

NEC, 1995

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 6

IBM, 1970GE, 1985

IBM, 1976MOSTEK, 1981

What Have Been InventedWhat Have Been Invented(Continued)(Continued)

NEC, 1998

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 7

““The WorldThe World’’s Smallests Smallest”” MythMyth

0

2

4

6

8

10

12

14

16

0.35 0.25 0.18 0.15 0.13 0.09

Technology Node (µm)

SR

AM

Cel

l Siz

e (µ

m2 ) TSMC

UMC

10.95

7.56

5.6

4.02.432.14

4.173.15

Cell size as a competitiveCell size as a competitive edgeedge

C.-H. Hsiao and D.-M. Kwai, “Measurement and characterization of 6T SRAM cell,” Int. Workshop Memory Technology, Design, and Testing (MTDT), Taipei, Taiwan, Aug. 2005.

0.99

Reach a consensus at last!

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 8

Tradeoffs to Be MadeTradeoffs to Be Made

Small but slow large but fast: area vs. speed (read current and write voltage)Small but hot large but cold: area vs. leakage power (standby current)Small but unstable large but stable: area vs. stability (static noise margin) Small but low-yield large but high-yield: area vs. manufacturabilitySmall but expensive large but cheap: area vs. cost (masking and process steps)

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 9

OutlineOutline6T cell and its variants – First we generalize and then we derivePeripheral circuits – Utilization is the keyCell layout – To be symmetric or to be asymmetric: that is the questionPerformance indices – To judge is humanConcluding remarks – It does not end here

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 10

Utilization Is the KeyUtilization Is the Key0.180.18µµm singlem single--port compiler generated instances port compiler generated instances with peripheral circuits minimized for layout areawith peripheral circuits minimized for layout area

Capacity (log2N )

Are

a S

avin

g (%

)

ExtraColumnMux

Divided Bit-Line Drive50

7 9 11 13 15 17 190

10

20

30

40

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 11

What Is Column Mux and What Is Column Mux and Why It Is ImportantWhy It Is Important

C = nR · nC = wW · wD

nR

nC

wW

wD

M

nR = wD/M, nC = wW · M

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 12

P&R Can Easily Destroy ItP&R Can Easily Destroy It0.180.18µµm singlem single--port compiler generated instances port compiler generated instances added with redundant power/ground ringsadded with redundant power/ground rings

10µm

25µm

40µm

0µm SRAM

10

20

30

40

50

60

70

80

10 11 12 13 14 15 16 17 18 19

Capacity (log2N )

Uti

lizat

ion

(%)

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 13

OutlineOutline6T cell and its variants – First we generalize and then we derivePeripheral circuits – Utilization is the keyCell layout – To be symmetric or to be asymmetric: that is the questionPerformance indices – To judge is humanConcluding remarks – It does not end here

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 14

M1

M2

V1

CO

OD

PO

How They Are DrawnHow They Are Drawn

D.-M. Kwai et al., “Detection of SRAM cell stability by lowering array supply voltage,” Proc. Asian Test Symp., Taipei, Taiwan, Dec. 2000, pp. 268-273.

(TSMC 0.18(TSMC 0.18µµm Symmetric Example)m Symmetric Example)

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 15

1.28µm

1.77

µm

CO

OD

PO

M1

M3

V2

V1

M2

How They Are DrawnHow They Are Drawn(TSMC 0.13(TSMC 0.13µµm Asymmetric Example)m Asymmetric Example)

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 16

Asymmetry in cross-coupled inverters can degrade cell stability by 100X [may be exaggerated]

How They Are DrawnHow They Are Drawn

G. E. Sery, “Approaching the one billion transistor logic product: process and design challenges,” Proc SPIE, vol. 4692, Design, Process Integration, and Characterization for Microelectronics, pp. 254-261, July 2002.

(Intel 0.18(Intel 0.18µµm Symmetric Example)m Symmetric Example)

PO

NOD

CO

POD

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 17

S. S. Iyer et al., “Embedded DRAM: technology platform for the Blue Gene/L chip,” IBM J. Research & Development, vol. 49, no. 2/3, pp. 333-350, Mar./May 2005.

How They Are on SiliconHow They Are on Silicon

Poly and Diffusion for DevicesPoly and Diffusion for Devices

S. Thompson et al., “130nm logic technology featuring 60nm transistors, low-k dielectrics, and Cu interconnects,” Intel Tech. J., vol. 6, iss. 2, pp. 5-12, May 2002.

Symmetric and Asymmetric ExamplesSymmetric and Asymmetric Examples

Intel 1.22 × 1.64 µm20.130.13µµmm

Fujitsu 0.9 × 1.1 µm290nm90nm

IBM 1.2 × 1.7 µm20.130.13µµmm

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 18

How They Are on SiliconHow They Are on Silicon

MetalMetal--1 as Local Interconnect1 as Local Interconnect

Symmetric and Asymmetric ExamplesSymmetric and Asymmetric Examples

S. Nakai, T. Hosoda, and Y. Takao, “Integration of high-performance transistors, high-density SRAMs, and 10-level copper interconnects into a 90nm CMOS technology,”Fujitsu Sci. Tech. J., vol. 39, no. 1, pp. 23-31, June 2003.

Intel 1.22 × 1.64 µm20.130.13µµmm

Fujitsu 0.9 × 1.1 µm290nm90nm

IBM 1.2 × 1.7 µm20.130.13µµmm

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 19

How They Are DrawnHow They Are DrawnIBM 0.13IBM 0.13µµm Example for ULP SRAMm Example for ULP SRAM

1.3µm

R. W. Mann, “Ultralow-power SRAM technology,” IBM J. Research & Development, vol. 47, no. 5/6, pp. 553-566, Sep./Nov. 2003.

Split Word LineSplit Word Line

1.8µ

m

NPG

NPD

PPU

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 20

Disadvantages Related toDisadvantages Related to

Complicated irregular patterns involving corner roundingSimplified rectangular patternDifferent orientation for access NMOS transistorsSame orientation for all transistorsPushed spacing rules for metal routing Nominal spacing rules for metal routing

Conventional Cell LayoutConventional Cell Layout

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 21

Variations by Inverter Layout Variations by Inverter Layout

M. Ishida et al., “A novel 6T-SRAM cell technology designed with rectangular patterns scalable beyond 0.18µm generation and desirable for ultra high speed operation,” Int. Electron Device Meeting Tech. Digest, 1998, pp. 201-204.

A Reveal Close to SuccessA Reveal Close to Success

It turns out to be veryuseful in 90nm and below process technologies

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 22

Can We Draw the PolygonsCan We Draw the Polygonsin Another Way?in Another Way?

M3M3M2VSS (V)

M3M3M2BL (V)

M2M2M3WL (H)

SymmetricAsymmetricSymmetric

Vertical VSS lines parallel to bit lines are required in the memVertical VSS lines parallel to bit lines are required in the memory array.ory array.

MetalMetal--Layer Assignment for RoutingLayer Assignment for Routing

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 23

Can We Draw the PolygonsCan We Draw the Polygonsin Another Way?in Another Way?

SRAM Cell Aspect RatioSRAM Cell Aspect Ratio

> 1.2

< 0.5

0

0.4

0.8

1.2

1.6

0.25µm 0.18µm 0.13µm 90nm 65nm

Technology Node

SR

AM

Cel

l Asp

ect

Rat

io

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 24

Extend Poly and Form Shared ContactAdjust Active AreaMove Half Cell to Align PolyMirror Half CellSeparate VDD/VSS ContactsRotate Access TransistorsSplit Word LineOriginal Symmetric Layout

An Animation to Show LayoutAn Animation to Show LayoutChanges to Rectangular PatternsChanges to Rectangular Patterns

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 25

P. Bai et al., “A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57µm2 SRAM cell,” Int. Electron Device Meeting Tech. Digest, San Francisco, CA, Dec. 2004.Z. Luo et al., “High performance and low power transistors integrated in 65nm bulk CMOS technology,” Int. Electron Device Meeting Tech. Digest, San Francisco, CA, Dec. 2004.

TI 0.46 × 1.06 µm2

0.49 µm2

A. Chatterjee et al., “A 65nm CMOS technology for mobile and digital signal processing applications,” Int. Electron Device Meeting Tech. Digest, San Francisco, CA, Dec. 2004.

Photo DemonstrationsPhoto Demonstrationsat 65nm Technology Nodeat 65nm Technology Node

Intel 0.46 × 1.24 µm2

0.57 µm2IBM 0.41 × 1.25 µm2

0.51 µm2

It seems that the layout style will pervade! It seems that the layout style will pervade!

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 26

Disadvantages Related toDisadvantages Related to

Longer and narrower wellsinduce forward body biasreduce static noise marginrequire higher strapping frequencylower array utilization

More irredundant contacts and via holes10 contacts/cell 8.5 contacts/cell3.5 via-1 holes/cell 2 via-1 holes/cell2.5 via-2 holes/cell 0 via-2 holes/cell

Regular Pattern Cell LayoutRegular Pattern Cell Layout

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 27

OutlineOutline6T cell and its variants – First we generalize and then we derivePeripheral circuits – Utilization is the keyCell layout – To be symmetric or to be asymmetric: that is the questionPerformance indices – To judge is humanConcluding remarks – It does not end here

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 28

Cell (Read) CurrentCell (Read) Current

A B

Icell0

VDDBL BL

WL WL

VSS

BA

Icell1

VDDBL BL

WL WL

VSS

BitBit--Line Discharge CurrentLine Discharge CurrentA = ‘0’ and B = ‘1’ A = ‘1’ and B = ‘0’

∆VBL = Icell · ∆t/CBL

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 29

Bounds on Cell CurrentBounds on Cell Currentwhere Cell Ratio where Cell Ratio γγ comes incomes in

Icell >ISD

γ + 1Icell >

ISA · ISD

ISA + ISD

γ · ISA

γ + 1=

Icell < ISA Icell <ISD

γ

Icell

VDD

VDD

VDD

VSS

ISA

VDD

VDD

VDD

VSS

VDDVSS

ISD

γ = =ISD

ISA

WD · LA

LD · WA

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 30

Saturation Current MonitorSaturation Current Monitor

ISA

γ · ISA

γ + 1

ISD

γ

ISD

γ + 1

Is Not Good EnoughIs Not Good Enough0.18µm SRAM Cell

0

25

50

75

100

125

150

1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0

VDD (V)

Cel

l Cu

rren

t (µ

A)

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 31

OnOn--Chip MeasurementChip Measurementof Cell Currentof Cell Current

Cell Current (µA)

64

64

16 16 16 16

84 86 88 90 92 94 96 980

200

400

600

800

1000

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 32

Location DependenceLocation Dependence

Cells are divided into two groups by their discharge paths (half cells) being next to a strap of a sub-array or notBoundary cells tend to have a smaller mean and a larger standard deviation

BoundaryMedian = 90.68 µAAverage = 90.75 µAStd Dev = 1.77 µA

InteriorMedian = 91.11 µAAverage = 91.17 µAStd Dev = 1.68 µA

Cell Current (µA)

of Cell Currentof Cell Current

84 86 88 90 92 94 96 984

3

2

1

0

1

2

3

4

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 33

Static Noise Margin (SNM)Static Noise Margin (SNM)

Static noise is the DC disturbance present in logic gatesThe worst case occurs when the static noise is adversely present inall logic gates in the same wayIt is the most important parameter of an SRAM cell

f

g

+−

+− vngvnf

‘0’

‘1’

+ −‘0’‘1’

− +‘0’

f gvnf vng

Every cell has to demonstrateEvery cell has to demonstrate

E. Seevinck, F. J. List, and J. Lohstroh “Static noise margin analysis of MOS SRAM cells,” IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 748-754, Oct. 1987.

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 34

f(VA - vn)

g(VB + vn)

VA

VB

VA

VB

VLA VHA

VLB

VHB f(VA)

g(VB)

VA

VB

VLA VHA

VLB

VHB f(VA)

g(VB)

f(VA + vn)

g(VB - vn)

VA

VB

Shift of MetaShift of Meta--stable Pointstable PointMaximum Squares in Butterfly CurvesMaximum Squares in Butterfly Curves

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 35

Static Noise MarginStatic Noise Marginas a Function of Supply Voltagesas a Function of Supply Voltages

SNM (V)

CVDD

WL WL

CVSS

+ −+ −

WLWL = = BL = BLBL = BL = = PVDDPVDD

BL BL

D.-M. Kwai et al., “Detection of SRAM cell stability by lowering array supply voltage,” Proc. Asian Test Symp., Taipei, Taiwan, Dec. 2000, pp. 268-273.

PVDD

CVDD (× VDD) PVDD (×VDD)

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 36

VBL (×VDD)

Static Noise MarginStatic Noise Marginas a Function of Precharge Voltagesas a Function of Precharge Voltages

SNM (V)

CVDD (× VDD)

CVDDBL BL

CVSS

+ −+ −

WLWL = = VDDVDD, , BL = BLBL = BL

WL WL

K. W. Mai et al., ”Low-power SRAM design using half-swing pulse-mode techniques,” IEEE J. Solid-State Circuits, vol. 33, pp. 1659-1671, Nov. 1998

VBL

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 37

SNM (V)

Static Noise MarginStatic Noise Marginas a Function of Bitas a Function of Bit--Line VoltagesLine Voltages

WLWL = = CVDDCVDD = = VDDVDD

VBLT (× VDD)

CVDD

CVSS

+ −+ −

WL WL

BL BL

VBLB (×VDD)

VBLT VBLB

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 38

Static Noise MarginStatic Noise Marginas a Function of Source Voltagesas a Function of Source Voltages

K. Osada et al., “16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray induced multierrors,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1952-1957, Nov. 2003.

CVDD

CVSS

+ −+ −

WL WL

BL BL

WLWL = = VSSVSS, , BL = BL = BLBL = = VDDVDD

SNM (V)

VSS VSSCVDD (× VDD) CVSS (×

VDD)

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 39

OutlineOutline6T cell and its variants – First we generalize and then we derivePeripheral circuits – Utilization is the keyCell layout – To be symmetric or to be asymmetric: that is the questionPerformance indices – To judge is humanConcluding remarks – It does not end here

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 40

What Revive 6T SRAM CellWhat Revive 6T SRAM Cell

Panel display driver/controllerLarge wafer quantity that foundries cannot refuseShrinking pad pitch that cell size becomes an issueLag behind the most advanced process at least three generationsPower, either static or dynamic, is the concern

National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 41

Challenges in the FutureChallenges in the Future

To many simulation works, too few measurement resultsNot only to show it functional, but also to prove it manufacturableTo invent a new cell is costly, it will be a pity to serve only one purposeThere are still some things we do not know well (e.g., substrate noise)

M.-F. Chang, K.-A. Wen and D.-M. Kwai, “Supply and substrate noise tolerance using dynamic tracking clusters in configurable memory designs,” Proc. IEEE Int’l Symp. Quality Electronic Design, pp. 225-230, Mar. 2004.