REVIEW - EXAM 1 - ece.uprm.eduece.uprm.edu/~mtoledo/web/4207/S2014/review-ex1.pdfFigure 15.5 Conceptual pass-transistor logic gates.(a) Two switches, controlled by the input variables

REVIEW - EXAM 1 INEL4207 - Spring 2014

INFO

• Thursday february 20

• during class time, in classroom assigned for class

• must come to your registered section

• a non-programmable calculator can be used

• formula sheets (bates) are not allowed

• Basic definitions & circuits with switches/idealized transistors

• Inverters: R-load, Saturated-load, CMOS

• Noise margins & static response, propagation time

• Complex gates that implement logic functions, transistor scaling

• Pass-transistor Logic / Transmission gates

• Dynamic / Domino Logic

MAIN TOPICS

SOURCES• Textbook’s 5th ed.:

◦ NMOS, CMOS: 1.7, 4.10, 10.1, 10.2, 10.3 ◦ PTL: 10.5 ◦ Dynamic/Domino Logic: 10.6

• 6th Ed.: chapters 14,15 (int’l) - 13, 14 (USA)

• Slides and examples on courses’ web page

• Your lecture notes

• Practice problems: see syllabus (6th ed, int’l)

Use transistor equations to determine:

• VOL, VOH, VIL, VIH, NMH, NML

• Dynamic and static power

• Use avg. current method (using transistor’s equations) to find tPLH, tPHL, tTLH, tTHL

• Transistor scaling

FOR ALL INVERTERS

• Find iD, VOL

• Variations (given one thing find others)

• VOL = VDD - IDRD

• Static power: PS=fraction × VDDID

• Dynamic power: PD=fCVDD2

R-LOAD

SATURATED LOAD

• VOH = VDD - Vt

• Vt = Vt0 + γ{ √(2ΦF +VSB) - √(2ΦF) }

• iD,Driver = iD,Load

• Q2 (load) is always saturated (or cutoff)

• Driver is usually on triode mode when vO = VOL

• quadratic equation

VSB=vO =VOH

CMOS• Complex gates

• Transistor scaling: given reference inverter

• find (W/L)’s based on (W/L)ref, (to have same tPHL, tPLH)

• find new tPHL, tPLH if (W/L)’s are given

• Noise margins

• Propagation and transition times using average current

COMPLEX GATES W/L SCALING

• Identify path with max. no. of transistors in series (ex.: n trans.)

• ∑∀i Ri = Rref ; split Rref equally so that Ri = Rref / n

• For remaining transistors, repeat steps 1 and 2 assigning the resistance not already assigned

• (W/L)i ratios are m(W/L)ref if Ri = Rref / m

Figure 15.5 Conceptual pass-transistor logic gates. (a) Two switches, controlled by the input variables B and C, when connected in series in the path between the input node to which an input variable A is applied and the output node (with an implied load to ground) realize the function Y = ABC.

(b) When the two switches are connected in parallel, the function realized is Y = A(B + C).

Pass-Transistor Logic

Figure 15.6 Two possible implementations of a voltage-controlled switch connecting nodes A and Y: (a) single NMOS transistor and (b) CMOS transmission gate.

Figure 15.7 A basic design requirement of PTL circuits is that every node have, at all times, a low resistance path to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It is provided in

(b) through switch S2.

Figure 15.8

For NMOS switch, load capacitor charges to vC - Vt

Body effect -> Vt

NMOS switch discharges capacitor completely

For PMOS switch, C charges to vC and discharges to Vt

Figure 15.11 The CMOS transmission gate and its circuit symbol.

CMOS switch - C charges to vC and discharges to 0

Figure 15.12

Figure 15.16 Realization of a two-to-one multiplexer using pass-transistor logic.

Figure 15.17 Realization of the XOR function using pass-transistor logic.

Figure 15.18 An example of a pass-transistor logic gate utilizing both the input variables and their complements. This type of circuit is therefore known as complementary pass-transistor logic, or CPL. Note that both the output function and its complement are generated.

Figure 15.19 (a) Basic structure of dynamic-MOS logic circuits. (b) Waveform of the clock needed to operate the dynamic logic circuit. (c) An example circuit.

Dynamic / Domino Logic