Research Triangle Park, NC - June 2007

IBM PCB - OS Symposium

Faster, reliable and lower cost electronics throughinnovative technology integration

IBMBldg 400

Research Triangle Park, NC

June 19, 20 & 21, 2007

IBM PCB - OS Symposium Program Agenda June 19. 20 & 21, 2007

Day 1

Adjourn & other activities

05:30 - 07:00Poster

04:00-05:30IBM & Suppliers panelist Panel discussionThe purpose of this panel is to discuss the requirementsand challenges, define potential solutions, identify risksand tradeoffs, examine the synergy and leverage areasbetween PCB & OS

03:40-04:00Martin Goetz, IBM-STGPackaging solutions: meeting the challenge& tradeoffs

Martin GoetzChairperson & Moderator03:10-03:40Break

01:30-02:0002:00-02:3002:30-02:5002:50-03:10

George Dudnikov, Sanmina Glen Thomas, KyoceraLei Shan, IBMStefano Oggioni, IBM

PCB challenges and Mfging solutionsThin Core Challenge for Organic SubstratesPCB Memory/ IC simulation Substrate Design Challenges

Application challengesDon ThomasSession Chairperson

12:10-01:30Lunch

10:30-10:5010:50-11:1011:10-11:4011:40-12:10

Bruce Chamberlin, IBMEd Blackshear, IBMDieter Bergman, IPC Dave Wolf, CAT Inc

PCB Technology RequirementsOS Technology RequirementIPC Technology RoadmapIndustry capability & gap data

Technology roadmapMoises Cases Session Chairperson

10:00-10:30Break

09:00-09:2009:20-09:4009:40-10:00

Harald Pross, IBMMoises Cases, IBMTodd Takken, IBM

Enterprise System OverviewX-series/ bladesBlue Gene & other systems

08:30-09:00Gregg McKnight, CTO IBM- STG Key note speakerTechnology requirements

Maurice BlandSession Chairperson08:15-08:30Ahmad KatnaniAdmin, logistic remarks08:00-08:30Registration

TimePresenterTopic

IBM PCB - OS Symposium Program Agenda June 19. 20 & 21, 2007

Systems and Technology Group

2007 IBM CorporationPCB & OS Symposium

Server Design Evolution, Challenges, and Implications

Gregg McKnight - CTOModular and Storage Development System and Technology GroupJune 2007


2007 IBM Corporation2 PCB & OS Symposium 6/16/2007

Next Generation System Direction and Strategy

Clusters Web, Mail, File/Print Terminal Servers

ComputationalInfrastructure

Workloads

Scale-Out Solutions

Power

Intel AMD

BladeCenter

BC-E

System

s Managem

ent

Virtualization

BC-HT

BC-H

Enterprise

EXA

Database Virtualization

Computational Application Server

Workloads

BlueGene

Modular

DS3000 & DS4000 Storage



Two Socket System x Racks Opteron in Grey

Built to meet the needs of HPC applications

Flexible I/O with HTxOptimized to improve interconnect latency

Density Optimized 1U serverExceptional for supercomputing clusters

12 DIMMs

x3455High Performance

Compute Node

x3550

1U, 2 SocketTarget Applications: Academia & Government ResearchFinancial Market ModelingDigital RenderingElectronic DesignBusiness Intelligence

Application density for power managed

datacenters

2U, 2 SocketTarget Applications:Business IntelligenceBusiness ContinuityDatabaseDigital Media (IPTV/VoD)Grid ComputingVirtualization & SCON

The perfect mix Inspired reliability and application performance

Leadership I/O and large memory capacity

16 DIMMs

x3655Business Performance

Server

Application DensityOptimize Space

Power ExecutiveOptimize/lower power cost

Advanced ManagementLower support costs

8 DIMMs

1U, 2 SocketTarget Applications:DatabaseERP/SCM/CRM/PLME-mail collaborationFile & PrintBranch OfficeSecurityWeb serving

Stable Integrated functionLower business support costs

High availabilityProtect data/lower costs

Power ExecutiveOptimize/lower power cost

12 DIMMs

x3650Stable Business

Critical application server

2U, 2 Socket Target Applications: Business ContinuityContent/Doc ManagementE-mail/CollaborationERP/SCM/CRM/PLMHosted ClientVirtualization & SCON



Four Socket+ Systems x Racks Opteron in Grey

X3850 / x366

Third generation application serverReliability and availability for critical business applications

Extreme Commercial Performance 100+ #1 benchmarks with IBM chipset design

16 DIMMs

3U, 4 SocketTarget Applications: Email / CollaborationDatabaseERP/SCM/CRM/PLMVirtualization & SCONWeb ServingSecurity

x3755HPC large memory

compute node

4U, 4 Socket Target Applications: Financial Risk AnalysisAerospace & AutomotiveExploration and Simulation Computer Aided EngineeringAutomated trading

Optimized for High Performance ComputingEntry price with extreme floating point performance

Flexible PerformanceCPU variations without sacrifice to performance

32 DIMMs

Commercial Enterprise and Mid-market

X3950 / x460

Third generation scalable serverReliability and availability for critical business applications

Extreme Commercial Performance 100+ #1 benchmarks with IBM chipset design

16 DIMMs/Node

3U, 4 Socket ScalableTarget Applications: DatabaseERP/SCM/CRM/PLMVirtualization & SCON

Commercial Enterprise and Mid-market



2 / 4 Socket BladeCenter Servers Opteron in Grey

AIX application compatible

PowerPC processor

High Speed CapableSupports 10 Gig fabrics

4 DIMMs

JS21High Performance Blade with Native

Virtualization

2 Socket, 30mm

Target Applications: AIX / Linux ApplicationsBusiness ContinuityCluster / HPCSecurityGrid ComputingVirtualization & SCON

Upgraded processor performance

At only 31 Watts per processor

For 32 bit applications

4 DIMMs

HS20 ULP

Performance Without the Power

2 Socket, 30mm

Target Applications: Customers with power and cooling constraintsBranch OfficeEmail / CollaborationHosted ClientFile & Print

2-4 Socket, 60mm

Target Applications: Business ContinuityCluster / HPCVirtualization & SCONBusiness IntelligenceERP/SCM/CRM/PLMModeling & Simulation

Greater maximum memory capacity

16 DIMMs


2+2 Scalability and Investment protection

LS41Scalable Enterprise Performance Blade

Server

LS21

High Performance Blade Server

Greater maximum memory capacity

8 DIMMs


2 Socket, 30mm

Target Applications: Cluster / HPCDigital MediaSecurityVirtualization & SCONWeb ServingModeling & Simulation

Intel Xeon 5100 Series (Woodcrest) Processor

General Purpose


4 DIMMs

HS21

General Purpose Enterprise Server

2 Socket, 30mm

Target Applications: Business ContinuityContent & Document ManagementE-mail collaborationFile & PrintHosted ClientWeb Serving



Battle for Technology Leadership

GridGrid

NAS/SANNAS/SAN

Grid

NAS/SAN

VPN

Cactus

NTG

(SF) Express Project

MFG

Fin.Services

SSG Management Application

BrowserBrowser

Other Managers

XML/CIM overHTTP

Virt EngineVirt Engine

Storage TankStorage Tank Shark, Tape, etc.Shark, Tape, etc.

Non-IBM Device

CIM Provider InterfaceCIM Provider Interface CIM Provider InterfaceCIM Provider Interface CIM Provider InterfaceCIM Provider Interface CIM Provider InterfaceCIM Provider Interface

Legacy devicesLegacy devices

ProxyProxy

XML / CIM

XML / CIM

XML / CIM

IBM

Scale UP

Scale OUT

Reduced SpaceReduced SpaceRapid DeploymentRapid DeploymentEfficient InfrastructureEfficient InfrastructureReduced ComplexityReduced Complexity

8-Way SMPHigh Speed I/OHA Clustering

Rack OptimizationSpace UtilizationCable ManagementRack "Ecosystems"

Tower ServersSmall SMPInternal StorageLarge Form Factors

Direct Attached External StorageStorage Area Networks

Scalable NodesScalable NodesResource ManagementResource ManagementResource ModularityResource ModularityEconomic ModularityEconomic Modularity

Heterogeneous SANHeterogeneous SANEnterprise NASEnterprise NASStorage VirtualizationStorage Virtualization

Modular Computing Evolution

Lower IT Costs

Minimize IT Complexity

Increase Business Efficiency

Challenges

CRM

ERP

SCM

IT Applications

Autonomic Computing

SystemTechnologies

Server Virtualization

Storage ReplicationFunctions

Management FunctionsManagement FunctionsSecurity, QoS, etc.Security, QoS, etc.

Storage software in subsystem

LPARS

Scale Out and Integration

Storage Virtualization and SAN File SystemsCommon Server & Storage Software

Modular Computing '02-'03

Grid Technologies CoD

TapeSubSys & LibrariesTape Drives

MidrangeDisk &

Servers

Low-end Servers

Blade Servers Networking and Storage

Storage fabric

productsNAS

Core Products

EnterpriseDisk &

Servers

CRM

Core Technologies

Operating Systems

Firmware

Processors

Packaging



2007 Modular Industry Trends AMD Challenges Intel market position

Microsoft embraces Linux

Quad-core pervasive - Pancakes SMP systems

Power consumption expenses approach server hardware spending

Multiple standards compete for unifying networking and storage fabrics

Good Enough technology powers Internet data centers

Virtualization penetrates all server footprints

Growing client interest in special purpose accelerators

Security is critical focus for server environments



System x Server Design Environment

Intel and AMD based processors Short range processor roadmaps Proprietary and standard processor bus interfaces

Industry standard interfaces Memory, IO, storage, etc. Understand technology roadmaps and forecasts

Create eco-systems when advantageous to IBM Partnering with suppliers for time-to-market advantage and/or

complete solutions

Capitalize on enterprise-based features when they provide business advantages



System x Server Design Drivers

Cost Competitive position, profitability, market share Best cost-performance designs

Time Short development cycles

Quality Number of design passes Number of escapes/ errors/ field returns

Productivity and efficiency Resources, both IT and people Reusability of components and sub-systems Standardization of designs and design tools



System Design Key Challenges:

Cost/ performancePower/ cooling

Innovation/ leadership

System Design Implications:Balanced cost system design TCO (Total Cost of Ownership)

Design and business processes SCM (Supply Chain Management)

System modularity and design reusability

MechanicalElectro-mechanical

Vacuum tubeDiscrete transistor

Integrated circuit

1

Com

puta

tions

/ se

c1900 1920 1940 1960 1980 2000 2020

10-6

10-3

103

106

1012

109

$1,000 buys

Kurzweil, 1999 & Moravec, 1998




Cost/ performance

Power/ coolingInnovation/ leadership

System Design Implications:Cost of power and cooling management

Opportunities for innovation/ leadership

$0

$20

$40

$60

$80

$100

$120

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

Installed Base(M Units)

Spend(US$B)

New Server Spend

Power and Cooling Spend

0

5

10

15

20

25

30

35

40

45

50

IDC Presentation, The Impact of Power and Cooling on Data Center InfrastructureDoc #201722, May 2006



0.0%10.0%20.0%30.0%40.0%50.0%60.0%70.0%80.0%

2000 2001 2002 2003 2004 2005 2006

x86 8-Socket Server Volume Share

IBM

HP

Dell

Other

IntroductionOf EXA

WW Q406 IDC Server Tracker Data


Cost/ performance

Power/ cooling

Innovation/ leadership

System Design Implications:Innovative packaging materials and structures

Innovative usage of PCB materials

Innovative and more efficient devices



Performance

The classical set of challenges are still with us!

Density

Power

Reliability

Affordability

+Innovate and add value



Thank You !


2007 IBM CorporationPCB & OS Symposium - June 2007

System x and Blades Design Environment and Challenges

Moises Cases, DE System and Technology GroupJune 2007


2007 IBM Corporation2 PCB & OS Symposium June 2007 6/10/2007

Agenda

System x & blade design Environment

Drivers

Design challenges Some examples

System x & blade design challengesMaterial implications

Tools implications

Summary



System x/ Blade Server Design EnvironmentIntel, AMD and IBM based processors Short range processor roadmaps Proprietary and standard processor bus interfaces

Industry standard interfaces Rack: FSB, CSI, HT3, DDR3, PCIe, HSS, SAS, SATA Blade: DDR3, PCIe, SAS, SATA, FC, Ethernet Switches: Fiber Channel, Ethernet, Infiniband, Myrinet

Create eco-systems when advantageous to IBM Partnering with suppliers for time-to-market advantage and/or

complete solutions Collaboration with blade.org

Capitalize on enterprise-based features when they provide business advantages



System x/ Blade Server Design DriversCost Competitive position, profitability, market share Best cost-performance designs

Time Short development cycles

Quality Number of design passes Number of escapes/ errors/ field returns

Productivity and efficiency Resources, both IT and people Reusability of components and sub-systems Standardization of designs and design tools



Blade Electrical Design GoalsMid-plane design to support both legacy and high-speed lanes for BC1, BCH ,BCE, BCT, and BCHT

Full backward compatibility across all chassis: 1.25Gb/s Ethernet Interface 2.125Gb/s Fiber Channel Interface 4.125Gb/s Fiber Channel Interface 8.5Gb/s Fiber Channel Interface 10Gb/s Ethernet Interface

PCB design implications and tradeoffs: Use low loss dielectric material intelligently Minimize cost

Use back-drilling to avoid via stub resonance on selected planes

Use transceiver equalization (FFE and DFE) to increase channel bandwidth, extend product life, and preserve customer investment



BC1, BCH, and BCE Legacy Channel

Switch Midplane Conn. RCVRBlade Conn.Option Conn.DVR4 4.5 18 6 8

InterposerMidplane Conn.

RCVR

Blade Conn.Option Conn.DVR4 4.5 18 5.8

BCHT Legacy Channel (Telco)

Max Length of 32 inch Min Length of 7 inch

Switch Conn.6 8

Max Length of 37 inch Min Length of 12 inch



Rack Server Scalability Link Performance Trend

* Estimated performance

Source: ECTC 2007 Proceedings DeAraujo, et. al.

Scalability Link Speed (Gbps)

0

2.5

5

7.5

10

12.5

15

17.5

20

22.5

25

2001 2004 2007* 2010* 2013*Year

Gbp

s

Link Speed



BACK

BACK

BACK

BACK

BACK

BACK

BACK

BACK

BACK

BACK

BACK

BACK

BACK

BACK

Module4-2-4 Std. Core

Board ViaStub/Thru

Card fan-out

Transmission linesStd. FR4

Board connectorHmZd

Cable connectorFujitsu GigaCN

TwinAx 26 AWG

4 socket, single node, 3U chassis

8 Socket System

16 Socket System32 Socket System

~2-3 m9-13 in 4-6 in 4-6 in 9-13 inScalability Controller

Scalability Controller

Rack Server Scalability Connectivity



0.5 to 3 0.5 to 3 2.5 to 6 7 to 8.5 5.5

Rack/Blade Server Scalability Channel Challenge

Switch Conn. RCVRConn.

DVR

BCH Configuration Bi-directional Xswitch for Scalability

Telco Configuration Bi-directional Xswitch for Scalability

Interposer

RCVR Switch Conn.4

Cntlt Blade TBD1 DC card TBD2 Interposer Airmax Midplane GBX Switch Redriver

Conn.

Cntlr Blade TBD1 DC card TBD2 Interposer Airmax Midplane GBX interposer

Redriver Switch GBX

0.5 to 3 0.5 to 3 2.5 to 6 7 to 8.5 1to 10

1 to 10

Conn.

Conn.Conn.

DVR Conn.Conn.



System x/ Blade PCB Projected Requirements

2005 2006 2007 2008 2009 2010+

Standard loss Df < 0.022 @ 1GHz

Bla

deC

ente

rxS

erie

s Ser

vers

Standard loss Df < 0.022 @ 1GHz

Low loss Df < 0.010 @ 1GHz

Low loss Df < 0.010 @ 1GHz Switch Modules, Telco Interposers, Telco Midplane

Very Low loss Df < 0.006 @ 1GHz Switch Modules, Telco

Very Low loss Df < 0.006 @ 1GHz



PCB Dielectric Material - Cost Challenge Example

Source: PPC Electronics

The cost pyramid for PCBs How do we manage cost effectively?Co

st (R

elativ

e to

FR4)



PCB Back Drilled Via - Cost Challenge Example

Source: Euro DesignCon 2004, Manufacturing Process and Electrical Behavior of Back-Drilled Holes for High-Speed Data Transmission, PPC Electronics/Siemens

Cost depends on how it is used!!!

12% back drilledsingle depth =

~5% cost adder



System Electrical Design Drivers Materials ImplicationsCost Optimal cost-performance design points Volume amortization via multiple usage Intelligent use of expensive materials and components

Time Cost and qualification time of emerging technologies Reduce qualification cycles Comprehensive and flexible long range procurement plan

Quality Comprehensive and timely qualification plan Capitalize on existing data repositories

Productivity and efficiency Intelligent use of expensive materials and components Develop an utilization strategy for optimal cost Standardization of components and materials usage across groups



System Electrical Design Drivers Tools ImplicationsCost Ease of exploring multiple solution space Ease of optimizing designs for cost/performance Ease of use Standard interfaces, portability, etc.

Time Ease of use - Standard interfaces, portability, etc. Seamless integration with physical design tools for both signal and power integrity Macro modeling of drivers, receivers, interconnects, connectors, cables, etc.

Quality Accuracy of modeling and simulation including parameter tolerances Capable of handling end-to-end topologies seamlessly Dynamic allocation of signal jitter and voltage margins Include all relevant signal and power integrity effects

Productivity and efficiency Tool performance, reusability for multiple applications and usages Use of parallelized code tuned to supercomputer architectures Integrated use of statistical analysis techniques Intelligent use of IT resources for job submission and prioritization



Electrical Design Challenges - SummaryHigh speed serial link electrical packaging challenges Increasing data rates

5-10 Gbps Increasing link loss

15-25 dB channel loss (i.e. ~85-95% signal loss) Increased complexity for loss mitigation

Equalization challenges (FFE / DFE / peaking amps) Low loss materials, back drilling, etc. Cable / Flex multi-chassis challenges

Diminishing noise margins Aggressive designs targets & careful noise management

High-frequency multiple board design optimization Interconnect modeling with connectors and cables Accuracy of model extraction and simulation algorithms including parameter

tolerances

High performance memory design subsystem challenges Increase memory capacity per blade using standard DIMMs Power distribution for DIMMs Multiple core effect on memory bandwidth/ capacity requirements


2007 IBM CorporationPCB & OS Symposium 2007

Enterprise System Overview

Harald ProssSTSM & CPMSTG System Hardware Development

IBM Boeblingen, [email protected]


2007 IBM Corporation2 PCB & OS Symposium 2007 6/14/2007

Agenda

System OverviewpSeries

iSeries

zSeries

sSeries

Packaging Challenges for Highend Servers



System z S/390 (Zero-Downtime)

System pRS/6000 (Performance)

System iAS/400 (Integration)

System s(Storage Architecture)

System xIntel-Server (Enterprise

X-Architecture)

IBM Server ClusterThe IBM Server Family

IBM Bladesintel-based (HS20, HS40)PPC970 based (JS20)

presentation focus



Mission: To Develop, Design and Implement Systems z/i/p & Storage Products That Provide Leadership Performance, Quality and Achieve Cost Competitive Targets.

Scope: System Design Definition, Documentation & Debug

System Hardware Roadmap Content & Line Items

System Cost Management

Feature / PN / Simplification Assessments

IO Interface Design, Implementation & Characterization

1st Level Packaging Design, Development & Characterization

Card and Connector Design, Development & Qualification

Electronic Packaging Integration of System & Chips

System Electrical Integrity (Signal Integrity & Noise Containment)

Power Subsystem Design Regulation, Distribution & Management

Power Supply Design, Specification & Debug

High End Power Code & FW

Mechanical Packaging Design, Implementation & Debug

System Thermal Design, Development & Verification

Commodity Management & Life Cycle Management (PE)

Systems Hardware Design Organization Mission



Systems Hardware Design Global Organization

Boeblingen, Germany

Poughkeepsie, NY

Rochester, MN

Raleigh, NC

Tuscon,AZ

Austin, TX



pSeriesiSeries



Virtualisation from Entry to High-End ServerBinry CompatibleAIX 5L or Linux on POWER

System p5 520

p5 520Q

BladeCenter JS21

System p5 575System

p5 570

System p5 505

IntelliStationPOWER 185/285

System p5 510

p5 510Q

System p5 550

p5 550Q

~p5

590/595

System p5 560Q

System p5 185

POWERPC 970 POWER5+ POWER5

IBM System p5

Future TrendsFuture TrendsComplex PCBsComplex PCBsLong TracesLong TracesHighest FreqHighest FreqPower EfficientPower Efficient

Future TrendsFuture TrendsLaminate PackageLaminate PackagePower ControlledPower ControlledDense PCB, Dense PCB, Minimum LayersMinimum Layers



zSeries



zSeries upgrades to System z9

growth temporary oder permanent

On/Off Capacity on Demand Upgrades

Reconfiguration of Prozessoren on Demand

Extension to Capacity BackUp (CBU)

* z800 Model 004 only ** All models except z900 Model 100

z800* z890 z900** z990

z9 BC

Upgrade to z9 BC Upgrade to z9 EC

z9 EC

Investment Protection on IBM System z Technology



Maschine-Type 20945 Models: S08, S18, S28, S38, S54Processor Units (PUs)

12 (16 for Model S54) PUs per Book 2 SAPs per Book, standard 2 Spares per Server (z990: per Book!) 8, 18, 28, 38 oder 54 PUs available

Central Processors (CPs), Integrated Facility for Linux(IFLs), Internal Coupling Facility (ICFs), System z9 Application Assist Processors (zAAPs), optional System Assist Processors (SAPs)

Memory Minimum 16 GB up to 512 GB per System, 16 GB Steps

I/O up to 16 STIs per Book, each @ 2.7 GB/s up to 4 Logical Channel Subsystems (LCSSs)

up to 4 x 256 = 1024 channels Overal l/O Bandwidth 172.8 GB/s

Virtualisation up to 60 LPARs

IBM System z9 EC berblick



z9 EC Prozessor Cage/Book Layout



TotalstoragesSeries



DS6000 / DS8000

DS6000 DS8000

The IBM TotalStorage DS8000 highlights:Delivers robust, flexible, and cost-effective disk storage for mission-critical workloads

Helps to ensure exceptionally high system availability forcontinuous operations

Scales to 192 TB and facilitates unprecedented asset protectionwith model-to-model field upgrades



Server Packaging Focus



TECHNOLOGY

System Application Processor Backplane Processor Backplane Processor Backplane Processor Backplane Processor Backplane

COMPLEXITY HYBRID/LGA HYBRID SMT/LGA HYBRID HYBRID/LGA HYBRID HYBRID/LGA COMPLIANT PIN

BOARD THICKNESS 104 mils 104 mils 114 mils 156 mils 137 mils 183 mils 174mils 184mils

NUMBER OF NETS 3209 6291 16833 70788 3084 2812 9355 7255

NO. OF COMPONENTS 2864 1516 2583 954 2073 0

COMPLIANT PIN YES YES YES YES YES YES YES YES

LINE SPACING 4.0mils 4.0mils 4.0 mils 4.0mils 4.0 mils 4.0 mils 4.0mils 4.0mils

LINE W IDTH 3 mils 3 mils 3.0 mils 3 mils 3.0 mils 3.0 mils 3.0mils 3.0mils

(5) Number of PTH's (A/B) 19,818 33,547 72,167 85,000 18,807 15,967 40,295 31,812

(4) Total Line Length (A) 19,829 44,285 110,483 178,120 47,017 20,290 77,453 52,500

(3) Total line length at min. space (B) 6,591 2,826 14,592 18,807 10,145 19,378 5,067

(6) BOARD DIMENSIONS 16.3" x 11.2" 17.8" x 19.2" 19.3" x 22.3" 20.5" x 24.8" 18.5" x 21" 22.3" x 20.9" 20.866" X 18.503" 23.500" x 22.283"

LGA YES NO YES YES YES NO YES NO

CCGA YES NO NO NO NO NO NO

BGA NO NO NO NO NO NO

SCM NO NO NO NO NO NO

LAYERS 10S12P2M 10S10P2M 14S14P2MP 18S11P2M 10S17P2MP 8S20P2MP 14S24P2MP 8S22P2MP

FINISHED VIA DIAMETER 8 mils 8 mils 10.0 mils 12mils 10mils 16.0 mils 10.0 mils 16.0 mils

ACTIVE/PASSIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PASSIVE ACTIVE PASSIVE

BURIED VIAS NO NO NO YES NO NO NO NO

BLIND VIAS NO NO NO NO NO NO NO NO

Server PCB Trends current board samples



Design and Business Driverperformance speedbus width interconnectionpackaging densitypower/cooling targetdesign effort time to marketquality & reliability & high-availabilityproductivity & efficiencymodularityre-use & compatibility & upgrade-ability

no free lunch -> Cost of development expense performance: MIPS/$$$ power&cooling: Watts/$$$ performance density: MIPS/BoxVolume performance efficiency: MIPS/Watts (Green Datacenter)

-> innovative usage of technology and material



Packaging ChallengesSignal Integrity

Connector Technology

Power (Current) Density

Real Estate (Component Density)

Environmental (RoHS)

Cost

Reliability and System Lifetime High-Reliability / High-Availibility

Continuous stress testing

Reliability line monitors

Field fail - Cost of Reliability is huge

Reputation



full steam ahead

to overcome these packaging challenges for next generation pSeries, iSeries Server Family next generation zSeries Server

>>> with YOUR help and YOUR Technology



Questions



Thank youwe covered

Enterprise System Overview pSeries / iSeries

zSeries

sSeries

highend server packaging challenges

- Thank you- Grazie - Arigato

- Muchas gracias- Shukriya

- Muhuway su- Danke Schn

Harald Pross

charts are courtesy of:Dietmar Amrein

Hans-Dieter WehleJuergen ProbstAhmad Katnani

Harald Prossthank you very much

IBM Research

6/11/2007 2007 IBM Corporation

Blue Gene Packaging

Paul Coteus & Todd Takken

2

IBM Global Engineering Solutions

Goals:Strategic partnership with key client (LLNL) - shared funding model

Validation and optimization of architecture based on real applicationsLeverage and validate SOC for density and powerTop500 leadership (by 8x)Client viewAssist us in the investigation of the reach of this machine (Research vehicle)Unparalleled scalability, best power performance

Grand challenge science stresses Scaleable I/O, memory (bandwidth, size and latency), and processing power.

Goals:Continue partnership with DOE to extend performance

Evolutionary step in architecture and performance (2.4x)Increase the Blue Gene community via Open SourceGrand challenge science stresses Application investment on BG/L applicable to BG/PImprove compilers, communications, application reach.Production system (broaden application base)

Goals:Mission driven partnership with DOE/NNSA/OoS

Push state of the art scaleable systems by >10xRadically new node and system architectureLeverage Blue Gene OS communitiesGrand challenge science stressesProduction system for weapons codes

1GB VersionAvailable 1Q06

Blue Gene/L(PPC 440-700 Mhz)

Scalable to 360 TFlops

Blue Gene/Q(Power architecture)

Scales 20PFBlue Gene Roadmap

Perf

orm

ance

Blue Gene/P(PPC 450: 0.85 GHz)Scalable to 1 PFlops

LA: 12/04, GA 6/05

Target LA: 3Q07, Petaflop: 1Q08

Target Avail: 4Q2010

2004 2006 20102008

SoC DesignA2 core basedCu-45 tech

SoC DesignCu-08 (9SF) tech

IBM Systems & Technology Group and IBM Research

2007 IBM Corporation3

13.6 GF/s8 MB EDRAM

4 processors

1 chip, 20 DRAMs

13.6 GF/s2.0 (or 4.0) GB DDR

32 Node Cards

14 TF/s2 TB

72 Racks

1 PF/s144 TB

Cabled 8x8x16Rack

System

Compute Card

Chip

435 GF/s64 GB

(32 chips 4x4x2)32 compute, 0-1 IO cards

Node Card

BlueGene/P Up to 1 Petaflop Performance

IBM Systems & Technology Group and IBM Research

2006 IBM Corporation4 6/11/2007

BG/P Compute Card

5.7 inches

32 Compute nodes

Optional IO card (one of 2 possible)

with 10Gb optical link

Local DC-DC regulators

(6 required, 8 with redundancy)

BPC Node Card

AC-DC Power Supply

Node cards

(fans on opposite sides)

Empty node cards in lower midplane

Global clock network (425 MHz)

1 Gb optical Ethernet control network

First BG/P Rack

Large midplane (48V power delivery, interconnect, control, fans)

Card attributesMidplane is 550 mm x 636 mm, 14 layers (large panel) full triplate(differential signaling) Node card is 400 mm x 427 mm, 16 layer (more power dist), 1 up standard panelCompute card is 145 mm x 55 mm, 14 layer.

Long lines are 8.5/11 line/space; short lines 4.0/5.0 line/space (3.0 mil lines on compute cards). 12 mil min drill through via, FR4.

Low loss dielectric would be required at somewhat higher signal freq

Blind / short stub vias not required at these freq.

Aggressive chip/package floorplanning and torus interconnect avoided need for buried vias.

Module attributesBlueGene/L (circa 2001) used ceramic packages.Future BlueGene machines will use organic chip packages.BlueGene/P is 4+2+4, next generation will be more.For reliability reasons, all chips are direct soldered (coplanarityissues, reflow temperature issues, Pb-free issues, )

Power distribution attributesN+1 redundancy throughout (AC-DC & DC-DC)

Custom converters with OR-FET controlDistribute 48 V DC intermediate voltage in rack

12 V DC too high loss400 V DC inconvenient & not yet standard

Final low voltage conversion on node card near point-of-loadSeparate pluggable card - too high distributon lossIntegrated with load too costly to make redundant

Future BlueGene machines will use400 V DC distributionFactorized powerN+1 or N+2 redundancy

What does the future look like?

Future is highly parallel! So cost, reliability, and risk of packaging is paramount. For BlueGene/Q and other 2010 machines, will move to largest available card sizes, very dense connectors, aggressive use of optics, and point of load DC-DC conversion. The relative weighting of these technologies will depend on availability, cost & risk. This conference, and other information exchanges like it, will help IBM decide whether or not to use presently high cost & potentially risking technologies such as massive card sizes, very high layercounts, low loss dielectrics, blind/buried or short-stub vias, fine pitch wires, etc.

2005 IBM Corporation

PCB Technology Challenges

B. Chamberlin June 11, 2007PCB Engineering, Dept FM2

2006 IBM Corporation2 June 11, 2007

FM2 Printed Circuit Board Engineering

Driver: Signal Integrity

Low Transmission Line Attenuationo Limits Progression towards Finer Line Widths/Spaces (3 mils -> 4 mils)

o Example: 2008 HE - 5 mil lines (midplane) 4.5 mil lines (node)o Driving Toward 1 Ounce Signal Lineso Low Loss Dielectric (0.010) in Limited Use Today (Z9)o Very Low Loss (0.005)

- Required for 2007 and beyondo Potentially Further Copper Roughness and Copper Resistivity Control

Impedance Control: Accuracy and Toleranceo Measurement Technique per IBM Specification

o Some product require functional net measurements in addition to in-board impedance couponso Implementing impedance shift to compensate for mfg measurement offseto Line Geometry and Dielectric Thickness Control Critical Coupon-to-Functional Net Correlation and Variation across Functional Nets



Triplate Design / HPC Technology

Balanced Triplates Generally Required (Power-Signal-Power-Signal...)even when buried vias are required:(Signal Signal Core Usage Restricted due to Signal Coupling)

o HPC Technology currently shipping in zSeries machines and required foripz near future- Expected to continue to be low volume

o Benefits in both wiringefficiency and mid-viastub reduction

HPC Option 1 Option 2



Driver: Signal Integrity- Stub Reduction

Minimize Signal Reflection Due to PTH Stubso Stub reduction technology usage 2006 and expected to expando HE ipz 2008 was able to design out stub reduction but next system willneed some form of stub reduction technology

o Backdrilling-- xSeries first to use in IBM- IBM ES written to define functional requirement

and protect reliability- Challenging in tight registration areas

(i.e. 1 mm LGA array)- Can be used selectively, easy to reduce or

eliminate if not needed



Driver: Signal Integrity- Stub Reduction, Wireability Improvement

Blind Vias

o Microvias

o Subcomposites- Beyond 2008? With composite through holesWith z Interconnect?

Cost versus performance will determine technology!



PTH Aspect Ratio * / Max Board Thickness

* Overall board thickness / Drilled hole diameter

Thickness (mils)

Aspect Ratio



Driver: I/O and Connectors

Connector Technology Impacto Forced Design Rules (Pad Stack Requirements)

Past: Pitch and Finished Hole Size SpecifiedPresent: Past + Drilled Hole Size and Plating Thickness SpecifiedFuture: Power Clearance and Internal Lands also Specified

o Registration Budgeto Board planarity/flatness (1% standard, 0.5% SMT Challenge)



Driver: I/O and Connectors

BGA / CGA Modules

o SCM / DCM 1.0 mm Pitch with I/O to 2500o SCM Pitch 0.8 mm Going to 0.75 with I/O to 400

Land Grid Array: MCM Attach Method for High End Systems

o Up to 7300 I/Oo 1.0 mm Pitch: No Projections to Decreaseo PCB Challenges

Plating Methodology (Ni/Au slivers, galvanic PTH etch concerns) Planarity (thickness variation) and Cleanliness



Driver: Increasing Current Density



Driver: Increasing Current Density

Increased Board Power Dissipationo Resulting in Higher Global and Local Board Operating Temperatureso LGA PTH Currents Breaking 2.0 A per 10 mil via

Resulting in Localized Heatingo Being Assessed Using Special Thermal Test Boards

Voltage Drop Challengeo Increased by Multiple Voltage Sense Points o "Swiss Cheese" Effect of High I/O, Small pitch

Example: 1 mm Array, 32 mil Clearance Holes

Leaves only 7 mil Web

Mitigation: Increased Copper Content in Boardso 5 oz planes, 60 oz boardso Impact on Processibility and Reliability

o Compounded by high voltage safety spacing requirements



Driver: Real Estate and Form Factor

Buried Resistorso Real Estate and Performance Main Driverso Not Justified Solely by Cost o Tolerance and Reliability Need to be Addressed

Buried CapacitorsReal Estate and Performance Advantages, ANDPlanar capacitance can reduce board thickness, BUTMust address IBM reliability restrictions

Panel Sizeo Peaking at 24 x 28, with push to stay within 19.5" x 24, BUTo Larger boards could be an opportunityo Complexity and High Density of Smaller Packages Expanding to Large Boards

PCB Thickness Constraintso Applications such as Blade Servers Restrict PCB Thickness

Driving Thin Cores, Denser Wiring, Smaller Vias, etc.



Driver: Environmental Factors

Environmental Legislation: RoHS

o Lead-free Assembly CompatibilityRaw Cards must be Capable of Withstanding Higher Assembly Temperatures

Tin/Silver/Copper (SAC) Solder (Tmp= 217, Tmin Reflow = 230 235, Board temp to 260 C)

Thick, high aspect ratio, and heavy copper boards a challengeWill Affect Subsequent Processes, Surface Finishes, and Reliability TestsMSA now, with Pb free server exemption through 2008 GA, REQUIRED BEYOND 2008! PCB Distortion will Increase with Higher Reflow TemperaturesCopper Dissolution During PIH Rework, thermal break performance important



Driver: Environmental Factors

Environmental Friendliness: Green Laminate

o Market Driving Low End --------- Identify New Materialo Not Required for Server or Storage Applications



Driver: Cost / Reliability

Reduce Cost while Maintaining High Reliability

Front End Collaboration to Achieve

o Design for Reliability and Manufacturabilityo Optimize Component Placement and Panel Utilizationo Bill of Material

Test Strategy

o Early Warnings to Minimize Cost of Scrapo Enhance Yield through Continuous Improvemento Potential Need for High Rel Tests (Near Opens, Near Shorts, HiPot)

- Currently usage:Leakage- 500V/300MOhm Limited HE ipzSeries boardsNear Opens- NLC (Non-Linear Conductivity) HE

Packaging Research and Development Center


IBM Buildup Laminate Substrate Requirement

E. Blackshear 6/19/07



Terms:

Solder Mask- Same Material as in PCB. Function now includes adhesion to underfill, patterning at C4 pitches.

Build up layers- High density circuit outer substrate layers

Core- Conventional epoxy glass PCB like inner substrate layers

RFP- Resin filled plated through holes in the core

Micro vias- Laser or photo process drilled blind vias in the build up layers

Top Side Metal (TSM)- The metal on the substrate top surface used for chip joining

Bottom Side Metal(BSM)- Substrate bottom metal use for interface to the next level assembly.

Stacked vias- microvias placed sequentially vertically inline forming a wiring stack



Chip C4s, 100um bumps, 200 um pitchLasered uVias, stacked, filled

Buildup dielectric, particle filled epoxy

Core dielectric, glass

reenforced

Resin filled plated through hole, mechanically drilledCore internal plane, Cu foil

Build up metal, semi additive plated

Stairstepped uvias

Unfilled uvias

Buildup Laminate



IBM Stable of Flip Chip Substrates- A wide application space must be covered

Low cost

carrier Thin Core Build UpMid, Thick Core Build Up Coreless CarrierAdvanced Carrier

600, 800um Core

multilayer

2-8 build up

Large formfactor

LGA

Few chip

To 70 mm?

400um Core

250um PTH Pitch

2-5 buildup

To 55 mm

ASIC workhorse

>200um Core

> 200um PTH Pitch

Layer counts, max size

TBD

Primarily wirebond

replacement

0-4-0, 1-2-1

400, 600, 800 um core

+ + + +

We monitor roadmapsOf > 7 suppliers andEngage selectively

Industry development

Much potential

Closely monitored


2003 IBM CorporationNote: Market share in units

Tape BGA$25M (25M Units)

Ceramic PGA/BGA/CSP$160M (45M Units)

Rigid CSP$900M (8,500M Units)

PBGA$830M (1,380M Units)

RF Modules (Organic)$100M (1,100M Units)

Cavity PBGA$130M (50M Units)

FC-PPGA$1,050M (250M Units)

FC-PBGA$1,250M (410M Units)

Film CSPs$125M (950M Units)

kc46.081skc-SUPPLYBASE

GLOBAL PACKAGE SUBSTRATE SUPPLY BASE - 2005

Rigid CSP PBGA Cavity PBGA FC-PBGA FC-PGA/LGA UMTC 18% PPT 180% Ibiden 30% Nan Ya 29% Ibiden 42%Ibiden 16% ASEM 14% Kinsus 35% Ibiden 18% Shinko 28%Samsung 12% Samsung 9% Kyocera SLC 7% NTK/Nan Ya 30%Shinko 13% JCI/TCI 9% SEMCO 17% Eastern JCI ASEM Nan Ya Others (Kinsus, PPT)

9% 8% 8% 7%

10%

Nan Ya Kinsus LG Others

12%9%

6% 23%

Kyocera SLC Shinko Eastern Others

5% 10% 5% 15%

ASEM PPT Shinko Kinsus

1%9%9%2%



FC-BGA/PGA/LGA BY APPLICATION

2005

MPU255M 42% MPU

400M 29%

Other MPU20M 3%

Other MPU65M 5%

ASIC/Logic35M 6%

ASIC/Logic75M 5%

DSP20M 3%

DSP40M 3%

Northbridge158M 26%

Northbridge345M 25%

Southbridge1M 0%

Southbridge150M 11%

Graphics for PC97M 17%

Graphics for PC110M 8%

Memory15M 2%

Memory35M 2%

Other1M 0%

Other80M 6%AMB

(Advanced Memory Buffer)

50M 3%

Graphics for Game Console

3M 0% Graphics for Game Console

50M 3%

TOTAL: 605M Units

ls86.088bp-fcbga

TOTAL: 1,400M Units

2010



FLIP CHIP SUBSTRATES DEMAND AND SUPPLY ESTIMATION

(M Units per Month) 2005 2006 (Est.) 2007 (Forecast) PC, NB, Servers (Intel), 17 20 22 PC, NB Servers (AMD and others) 4 6 7 Game (IBM) and others 0.2 2 3

CPU

Other MPU 0.5 0.5 1 PC NVIDIA, ATI 10 9 10 GPU Game NVIDIA, ATI 0.2 2 3 Intel 15 18 20 Via, SiS, NVIDIA 2 5 6 Northbridge Game Console 0 1 2

Southbridge Intel, Via, SiS, NVIDIA 0 0 1 Others 9 10 14 Total Demand 57.9 73 89 Intel Demand 32 38.3 43 Intel Share 55% 53% 48%

Supply Estimation Customers 2005 2006 (Est.) 2007 (Forecast) Ibiden Intel, AMD, NVIDIA, IBM, etc. 20 21 23 Shinko Intel IBM, Toshiba, Nintendo 10 11 12 Nan Ya Intel, NVIDIA, ATI 16 21 26 NTK Intel, AMD, NVIDIA, IBM, etc. 2 3 4 SEMCO Intel, NVIDIA, ATI 6 10 17 PPT ATI, NVIDIA, Via 5 10 14 Kinsus Xilinx, Altera 1 1.5 3 Kyocera SLC Technology (KST) IBM, Altera, Toshiba, NEC, LSI 2 3.5 4 ASEM ATI, NVIDIA, Via 1 0 1 Unimicron NVIDIA 0 3 5 Others (Toppan, etc.) 3 5 5 Total 66 88 114 Capacity/Demand Ratio 1.14 1.21 1.28

106.1/081bp



IBM Overall Substrate Direction20092007NowFeature

864BU layers (max)

3-9 (SIP) 1# Chips

53Suppliers

100K POH typ.

Cycles by App.Field life

0.45W/mm20.30W/mm2Chip Power

BGA+LGABGAInterconnect

+Coreless or high performance

+600 m / 2-4800 m / 2-6

400 m / 2Core / Layers

13 - 7013 - 55 mmSize



FC-PBGA Laminate Roadmap Top Layer Die Area

15 - 20 m20 mLine/Line Space

2009NowFeature

100 - 110 m130 mPad Diameter

15 - 18 m20 mLine Width

10 - 12.5 m15 mRegistration

80 - 85 m 100 mSolder Resist Opening

150 m200 mMin. Bump Pitch



FC-PBGA Laminate Roadmap Build-Up Layers

2009NowFeature

4 - 63Via Stack Height

25 m25/30 mMin Line Width/Space - Global

33 - 35 m33 - 35 mDielectric Thickness

18 m20 mMin Line Width/Space - Escape

40- 50 m 60 - 70 mVia Diameter

100 m95 - 110 mVia Land Diameter



FC Laminate Roadmap - Core

2 - 42 - 6Core Layers

2009NowFeature

400 - 234 m600-250 mPTH Pitch

35 / 45 mLine Width/Space

40 mLand/Land Space

75 - 200 m105-200 mPTH Diameter

200 - 800 m 400 - 800 mCore Thickness



FC Laminate Roadmap - Materials

Solder mask - Registration improvement needed to handle C4 pitch down.

Maximum use temperature limit of photosensitizers seen

Build up Significant reduction in CTE needed to accommodate

large die/low k dielectric

maximum use temperature limit needs definition for CPU

Core Significant reduction in CTE needed to accommodate large

die/ low K dielectric.

Drill size/pitch reduction needed for wireability, performance

Via fill - Closer match to core properties needed for warpage control

Solderable finish Migration to Pbfree processing underway.



State of the art Cell Processor Package

3/2/3 thincore substrate

Three stacked, filled vias

Via on RFP

Delivers best

-Wireability

-Performance

-Cost

IPC International Technology Roadmap for Electronic Interconnections 2006 - 2007

Preparing for the next generation



To guide manufacturing, process, material, equipment, and product, research and development, in order to establish leadership in electronic interconnection technology;

Integrate the development in the electronic industry with partners in academia and government; and excel in the global market by implementing these developments and continuously improving customer satisfaction.

Roadmap mission



Focus of the IPC Roadmap Electronic interconnections include the

processes for fabrication of the interconnection structure and materials plus the attachment mounting the assembly of electronic components.

This International Technology Roadmap is intended to provide the vision, and direction for product development, process development and services required to satisfy the short term, near term and long term requirements for electronic interconnections



60s 70s - Main Frames

70s 80s - Personal Computers

80s 90s - Hand Held

90s High Speed data and RF

Today Packaging / Silicon

Future Optoelectronics? Enhanced copper performance?

Driving Forces



The roadmap may be thought about as four different sections

Components

PCB manufacturing

Assembly of PCBs

Infrastructure and support



Multi-dimensional ApproachMARKET SECTORS

AutoComputerMilitaryTelecommunicationsEducation/RetailConsumerIndustrialInstrumentation

PERFORMANCE SECTORSHarsh EnvironmentPortablesHigh PerformanceLow Cost, High VolumeCost & Performance Sensitive

TECHNOLOGY SECTORSCommodityLeading EdgeState of the Art

Tech

nolog

y

Secto

rs

Per

form

ance

Sec

tors

Market

Sectors

Technology Planningis Multidimensional



History of IPC RoadmappingBase Element First National Technology Roadmap SurveyEstablished IPC as a National Roadmapping entity

9 Business Segments151 R&D Tasks Identified Potential Showstoppers

Lack of coordinated technology integration into manufacturing

No single common set of needs between industry, government and academia

Lack of process controls Poor customer/supplier

relationships4 year outlookLed to the creation of ITRI

Base Element - OEM Input - 8 Emulators

Nationally Integrated, NEMI, SIA, MCC, SIA

Presented to U.S. Congress - June 1995

15 Year OutlookFocus on Revenue Center of Gravity

ConventionalLeading Edge

Initiated the 1996 Worldwide Benchmark

Base Element - OEM Input - 20 Emulators

Nationally IntegratedAdded Chapters

Ceramic InterconnectionsBackplanesConnectors

Added State of the Art focus

Base Element - Survey10 Business Segments (EH&S)162 R&D Tasks4 Year OutlookEstablished ITRI Priorities

1993 1995

19941997



Base Element - OEM Input -

Nationally Integrated

11 Product Sectors

Added Chapters

Component Manufacturing

Packaging

Optoelectronic

Reliability

2000 2001

2002 - 2003

2004 - 2005

Base Element - OEM Input

Internationally Integrated

8 Product Sectors

Added information

Embedded Passives

Optoelectronics

Backplanes



8 Product Sectors

Added information

Embedded Passives

E- Test

Optoelectronics

Reliability roadmap





8 Product Sectors

Added information

Factory environment

Design

Equipment

Reliability roadmap

2006 / 2007



ITRIInternalR&D

ExternalR&D

ExternalR&D

Consortia

Suppliers

ITRI

NIST

NCMSNAVSEA CRANE

ARPA

Who uses the IPC Roadmap?

HDPUGiNEMI

IPCRoadmap



Interconnect & assembly technology only

Operational level detail

Emulator analysis and Comparison

Two points of reference data for each time frame RCG / SoA

What makes the IPC Roadmap different?



Organization of the 2006-2007 Roadmap

Component Packaging Manufacture

Electronic Assembly Manufacture

Additional Considerations

Component Technology

Related Technologies

OEMRequirements

Emulator DetailsEmulator Needs Assessment

Design IssuesUse of DistributorsSupply Chain ManagementCost Relationships

Purpose &Overview

Package Style and Physical AttributesGround and Voltage DistributionComponent Assurance TestingReliability Expectations

Organic Interconnecting StructuresCeramic Interconnecting StructuresAssembly of Die and PassivesPackaging and Handling

Rigid Printed BoardsFlexible Printed BoardsHigh Density InterconnectAssembly of Printed Boards

Environmental Health and SafetySystem ReliabilitySystem ArchitectureRelationship of other Roadmaps



Accomplishments of IPC Roadmaps

Created ITRI DuPont Shipley Consortia NCMS PCB & Embedded Passives Consortia Prioritized Industry R&D Activity Prioritized New and Improved Standards HDI,

Electronic Design, and now Optoelectronics Established a Working Agenda for Congress Worldwide Acceptance Encouraged international vision and participation



Internationalizing the IPC National Technical Roadmap

European Input Michael Weinhold, EIPC

Japan Input - Hisao Kasuga- Aki Shibata- Henry Utsunomiya

Hong Kong - S.L.Law

China Huawei Technologies



Focus group concept

10 Very successful focused meetingsPackagingDesignFlexReliabilityFactory environmentEquipmentMaterialsOptoelectronic assemblyPCQR2

Whats new for 2006 - 2007



Detail Validation for Printed Boards



Whats new for 2006 - 2007

Reliability section updated

Optoelectronic substrate assembly completely revised

New section on Printable Electronics



Product Emulators 2006 - 2007

E-1 Electronic gamesE-2 Low Cost ElectronicsE-3 Hand-held / Wireless ElectronicsE-4 Mid Range ElectronicsE-5 High Performance ElectronicsE-6 RF and Microwave ElectronicsE-7 Harsh Environments/Aerospace E-8 Harsh Environments/Auto Electronics



Component Packaging

In the 2006-2007 packaging is still the main technology driver. Packaging I/O density and new package configurations continue to be the most significant driver of PCB technology



PCB Manufacturing Technology

The challenge to PCB manufacturers continues to bedensity and layer count. Connect density has not slowed down and is not forecasted to slow.Layer count, especially in the larger boards continuesto show an increase.



Electronic Manufacturing Assembly

Products will continue to be a through hole and surface mount mix. Assembly will be driven by multi-chip package designs with an increasing number of I/Os to support power requirements and bandwidth. Array pitches will continue decrease to new levels. Thermal issues will become critical. MEMs is still a niche technology with wireless becoming widely used.Optoelectronic assembly continues to evolve and grow



Environmental topics

Environmental regulations changing from domestic regulations, increasingly to global regulations. A new trend of international market driven environmental initiatives focusing on materials. The highest priority issues are those relating to RoHS compliance, reducing the burden associated with exchanging materials composition information. Regulations governing the environmental impacts of manufacturing, including the use, storage, transportation, and disposal of hazardous materials, continue to exert a significant influence on the manufacturing process.



Design issues

Design and simulation tools are the main roadblocks to more rapid introduction of new technologies in a number of rapidly developing areas:

Mechanics and Reliability Modeling Thermal and Thermo-fluid Simulation Improved design tools for emerging technologies Prediction tools needed for embedded potential Issues highlight importance of emulators



Emulator Importance Design drivers The mid range emulator contains cost sensitive, single user, general purpose

computing systems such as personal computers and industry targeted products such as telecom line cards. This includes computer products such as desktop systems, laptop computers, workstations and small business systems and routers.



Emulator Importance Printed Board Drivers



Emulator Importance Assembly Drivers



Emulator Driver Comparisons



Added descriptions to drivers EXAMPLE In addition, the following characteristics also apply: I/O explosion; plastic array packages with high I/O count Many systems will make use of daughter board (super

component) concepts Connectors will require High I/O and high frequency capabilities HDI and Via usage will increase with decreasing package pitch

Discussed inconsistencies Evaluated survey from roadmap users Developed new methodology for future Started data model for XML schema

Major Emulator Review



Most of the technology breakthroughs are coming from Silicon

Silicon continues to make higher speeds on FR4 possible (Advanced pre- emphasis, de-skew buffers)

Only incremental improvements on the PCB and interconnect side (Counterbore, HDI etc.)

Not enough data available from Materials/PCB manufacturing to allow accurate modeling

Both the substrate and the package are limiting factors in system cost and performance

Strong need for suppliers, fabricators and OEMs to work pro-actively to agree upon standards

Process change will continue to evolve

Summary

Outline

PCQR2 Database OverviewIndustry CapabilitiesDiscussion

Consists of statistical data collected from a family of industry-standardized process capability panel designs Test and analysis quantifies the capability, quality, and reliability demonstrated by suppliersBenchmarking resource based on industry developed test patterns, proven test methods, and statistical analysis techniques

What is the IPC PCQR2 Database?

IPC PCQR2 Database Partnership

www.pcbquality.com

STANDARDIZED PCB BENCHMARKING DATA one click away

Process Capability, Quality, and Relative Reliability

www.ipc.orgwww.cat-test.info

Measuring Capability and Quality

Specialized test patterns designed to reproduce the features present on product boardsProven data acquisition methods to collect capability, quality and reliability dataStatistical data analysis techniques to generate relevant statisticsIndustry standardization to encourage cooperation and reduce duplication of efforts

Database Applications

Developed for designers, manufacturers, purchasers, and assemblers of printed circuits

Statistically benchmark board suppliers' capabilitiesPerform intelligent sourcingSelect new suppliersEnsure design for manufacturabilityEstablish realistic design rules

Database Components

Design libraryRigid boardVia boardRigid-flexPackage substrate

Analysis reportsDetailed data on each suppliers processOver 100 pages of tables and graphsReports available for 12 months

Comparison dataDetailed data comparing each suppliers capabilitiesFiltering options to segregate data by layer count, board thickness, etc. Spreadsheet and graphical outputsData available for 24 months

Database Access

SubscribersAnnual subscription fee based on previous years electronics revenuesRequest panel submissions from current and potential supply baseAccess to all database components

SuppliersNo testing fee if submission is requested by a SubscriberSelf-submissions are allowed and encouragedAccess to associated Analysis Report and Comparison Report

Database Subscribers

BAE Systems North AmericaGeneral Electric CompanyHoneywell International, Inc.Intel CorporationLockheed Martin CorporationNational Aeronautics and Space Administration (NASA)Naval Surface Warfare Center Crane Div.Qimonda AGRaytheon Company Reptron Manufacturing ServicesRockwell Collins, Inc.Sandia National LaboratoriesTeradyne, Inc.Texas Instruments, Inc.

Defense and Aerospace User Group

BAE SystemsHoneywellLockheed MartinNASANSWC-CraneRaytheonRockwell CollinsSandia Labs

Europe, Middle East & A frica

1%Asia/Pacific19%

Greater China43%

North America37%

Database Submissions by Region

From last 24 months

Supplier Facilities Last 24 Months

AT&S Shanghai, ChinaAT&S Nanjangud, India CATAC Electronics Zhongshan, ChinaCentury Printed Circuit Lu Chu Hsiang, TaiwanChuan Yi Computer Shenzhen, ChinaCircuit Connect Nashua, NHCircuit Mission Ltd. Guangdong, ChinaCoretec Cuyahoga Falls, OH Cosmotronic Irvine, CA Dynamic PCB Electronics Kunshan, China Eagle Circuits Dallas, TXElec & Eltek Guangzhou, China Elec & Eltek Kai Ping, China Ellington Electronics Guangdong, China Endicott Interconnect Technologies Endicott, NYFTG Circuits - Scarborough, ONFTG Circuits Chatsworth, CAGBM (PC Asia) Kunshan, ChinaGold Circuits Suzhou, China Gorilla Circuits San Jose, CAGraphic Research Chatsworth, CA Harbor Electronics - Santa Clara, CA Hitachi Chemical - Singapore Holaday Circuits Minnetonka, MN Integrated Test Corporation Dallas, TXKCA Electronics Anaheim, CA Korea Circuit Kyungki-Do, South Korea Lockheed Martin Owego, NYLone Star Circuits Wylie, TX

Marcel Electronics International Orange, CA Meadville Circuits Dongguan, ChinaMerix - Forest Grove, OR Moog Components Group Galax, VA Nan Ya PCB Kunshan, ChinaNan Ya PCB Jing Hsin, TaiwanNTU Electronics Largo, FLNTU Electronics Largo, FLOki Printed Circuits Joetsu, JapanOriental Printed Circuits - Tai Po, Hong Kong Pan-International (Foxconn) Dongguan, China Pioneer Circuits - Santa Ana, CA Samsung Electro-Mechanics Suwon, S. Korea Simmtech - Heungduk-Ku, South Korea Seminole (NTU) Electronics Taiwan Synergie CAD - Carros Cedex 1, France Topsearch Printed Circuits Shenzhen, China Tripod Technology - Taoyuan, Taiwan TTM Technologies - Santa Ana, CA Tyco Electronics PCG Dallas, OR Tyco Electronics PCG - Santa Clara, CA Tyco Electronics PCG Stafford, CT Unimicron Shenzhen, China Viasystems - Guangzhou, China Wus Printed Circuit Kunshan, China Wus Printed Circuit Kaohsiung, Taiwan Ya Hsin Electronics Dongguan, China Yang An Electronics - Taoyuan, Taiwan Yu Fo Electronics Huizhou, China

Historical Supplier FacilitiesAdiboard Jundiai, Brazil AT&S Leoben, Austria AT&S Shanghai, ChinaAT&S Nanjangud, India BoardTek Electronics Kuan-Yin, Taiwan Broad Technology Guangzhou, China CATAC Electronics Zhongshan, ChinaCCI Electronics Yangmei, TaiwanCentury Printed Circuit Board Lu Chu

Hsiang, TaiwanChina Circuit Technology Shantou, China Chuan Yi Computer Shenzhen, ChinaCircatex South Tyneside, England Circuit Connect Nashua, NHCircuit Mission Ltd. Guangdong, ChinaCMK Dongguan, China Compeq Huizhou, China Compeq Taoyuan, Taiwan Coretec Cuyahoga Falls, OH Coretec Denver, CO Cosmotronic Irvine, CA Diversified Systems Indianapolis, IN Dynamic Details Anaheim, CA Dynamic Details Milpitas, CA Dynamic Details Sterling, VA Dynamic PCB Electronics Kunshan, China Eagle Circuits Dallas, TXEastern Pacific Circuit HuiYang, China Elec & Eltek Guangzhou, China Elec & Eltek Kai Ping, China Elec & Eltek Kowloon, Hong Kong Elec & Eltek Pathumthai, Thailand Electropac Canada Point-Claire, QC Electro Plate Circuitry Carrollton, TX Ellington Electronics Guangdong, China Eltek Petach Tikva, IsraelEndicott Interconnect Technologies

Endicott, NY

First Hi-Tec Enterprise Taoyuan, Taiwan FTG Circuits Scarborough, ONFTG Circuits Chatsworth, CAGBM (PC Asia) Kunshan, ChinaGold Circuits Suzhou, China Gold Circuits Chung Li, Taiwan Gorilla Circuits San Jose, CAGraphic Research Chatsworth, CA Gul Technologies Singapore Hallmark Circuits Poway, CA Harbor Electronics Santa Clara, CA Hitachi Chemical Loyang, SingaporeHoladay Circuits Minnetonka, MN Integrated Test Corporation Dallas, TXISU Petasys Taegu, South Korea ITL Circuits Markham, ON KCA Electronics Anaheim, CA KCE Electronics Bangkok, Thailand Korea Circuit Kyungki-Do, South Korea LG Electronics Osan City, South Korea Lockheed Martin Owego, NYLone Star Circuits Wylie, TXMarcel Electronics International Orange, CA Meadville Circuits Dongguan, ChinaMerix Forest Grove, ORMoog Components Group Galax, VA Multek Vila Andrade, Brazil Multek Zhuhai, China Multek Boeblingen, Germany Nan Ya PCB Kunshan, ChinaNan Ya PCB Jing Hsin, TaiwanNorth Texas Circuit Board Grand Prairie, TX NTU Electronics Largo, FLOki Printed Circuits Joetsu, Japan Oriental Printed Circuits - Tai Po, Hong Kong Pan-International (Foxconn) Dongguan, ChinaPioneer Circuits Santa Ana, CA Plato Electronic Shenzhen, China

Prestwick Circuits Irvine, Scotland Red Board Dongguan, ChinaSamsung Electro-Mechanics Suwon, S. KoreaSanmina-SCI Owego, NY Sanmina-SCI Phoenix, AZ Simmtech - Heungduk-Ku, South Korea Seminole (NTU) Electronics - TaiwanSovereign Circuits - North Jackson, OHSynergie CAD - Carros Cedex 1, FranceTai Hong Circuit - Kweishan Hsiang, Taiwan Taiwan PCB Techvest Ping Chen, Taiwan Teradyne Connection Systems Nashua, NH Topsearch Printed Circuits Shenzhen, ChinaTripod Technology - Taoyuan, TaiwanTTM Technologies - Santa Ana, CA Tyco Electronics PCG Austin, TX Tyco Electronics PCG Dallas, OR Tyco Electronics PCG Logan, UT Tyco Electronics PCG - Inglewood, CA Tyco Electronics PCG Madrid, Spain Tyco Electronics PCG - Santa Clara, CA Tyco Electronics PCG Stafford, CT Tyco Electronics PCG Valladolid, Spain Unicap Electronics - Ping Chen, Taiwan Unimicron Shenzhen, ChinaUnimicron Taoyuan, Taiwan Unitech PCB - Tu-Cheng, Taiwan Vertex Precision Electronics - Chung-Li, Taiwan Viasystems - Guangzhou, ChinaViasystems - Granby, QCVOGT Electronic Gittelde, Germany Wus Printed Circuit Kunshan, China Wus Printed Circuit Kaohsiung, Taiwan Ya Hsin Electronics Dongguan, ChinaYang An Electronics - Taoyuan, Taiwan Yu Fo Electronics Huizhou, ChinaYu Fo Electronics - Taoyuan, Taiwan

Design Library

Rigid Board

18 x 24 inch panel size

Via Board


Package Substrate


Rigid-Flex


Test Modules

Conductor/Space

Soldermask Registration Controlled Impedance

Via Formation & ReliabilityVia Registration

Process Capability Panel

IPC-14R-D Stackup

IPC-10R-D, 14R-D and 18R-D Map

IPC-24VC-D Stackup

IPC-24VB-D and 24VC-D Map

Database Elements

Test Module Capability Quality Reliability

Conductor/Space Conductor and spaceyield

Conductor width and height control

--

Via Registration --

Via Formation Via yield Resistance control Cycles to failure

Soldermask Registration

--

Controlled Impedance

--

Probability of breakout

Impedance control

Probability of encroachment

Capability Ability to form featuresQuality Conformance to specificationsReliability Relative industry comparison

IPC Roadmap Section A-6

ScopeDocument current and historical rigid board manufacturing capabilities from IPC PCQR2DatabaseValidate "current" technology roadmap data and expand on roadmap information to include additional attributesFocus on historical data to make future projectionsRCG = Revenue Center of Gravity (practiced by 95% of the industry)SoA = State of the Art (practiced by 5% of the industry)

Outerlayer Conductor/Space Formation

Conductor Formation Space Formation

Width Control

Innerlayer Conductor/Space Formation

Conductor Formation Space Formation

0.5 oz. Width Control 1.0 oz. Width Control

Through Via Formation

Via Formation Via Registration

1-Deep Blind Via Formation

Via Formation Via Registration

Soldermask Registration

Controlled Impedance Formation

Surface Microstrip Embedded Microstrip

Stripline Edge-Coupled Stripline

Final Thoughts

It is difficult, if not impossible, to make sound decisions without good dataGood data requires

Appropriate and flexible test vehiclesProven data acquisition methodsStatistical data analysis techniquesConsistent reporting

Differentiating factors of the IPC PCQR2Database

Test vehicle standardizationQuantitative benchmark and comparative dataCost sharing

Contacts (www.pcbquality.com)

Dave WolfCAT [email protected]

Tim EstesCAT [email protected]

Gary LongIntel Corp. (D36 Chairman)[email protected]

Dave [email protected]

John [email protected]

ELECTRONICS MANUFACTURING SERVICES

2006 Sanmina-SCI Corporation. Sanmina-SCI is a trademark of Sanmina-SCI Corporation. All trademarks and registered trademarks are the property of their respective owners.

PCB Challenges and Manufacturing Solutions for High Density and Advanced Applications

George DudnikovSr. VP CTO PCB Division

[email protected]

Presented to IBM PCB OS Symposium

June 19th 2007

Sanmina-SCI Confidential

PCB Technology and Market Migration

The Market Trend is ObviousCompanies Must Think and Manufacture GloballyEngineering and NPI still NA based ..how long?Innovations will be required to compete

Where will the future R&D come from?


Technology Drivers: More speed and functionality

10Gbps plus

Signal Integrity

Higher I/O Packages and Density

Form Factor Reduction

High Power Components

DCA / Flip Chip

Reliability

Compliance Customer Spec,

UL,IPC,Telcordia ,Mil)

Cost/Performance

PCB Effects: Fine Line & Space

Higher Layer Counts

Low Dk/Df Materials

Thinner Dielectrics

Thin foils/Thicker Foils

Smaller holes/Higher Density

HDI Micro Vias

Engineered Via Structures

Tighter Tolerances

Filled Vias

Embedded Passives

PCB Technology Challenges and Drivers


Presentation Focus

Signal IntegrityLaminate MaterialsEmbedded PassivesHDI StructuresNew Innovations


Signal Integrity


2.5 Gb/s 5 Gb/s 10 Gb/s10-12

10-14 11 hours 5.6 hours 2.8 hours

10-16 1.5 months 3.3 weeks 1.7 weeks

10-18 12.7 years 6.4 years 3.2 years

Two 2X Data Rate Increases2.5/3.125 5/6.25 10/12.5 Gb/s

6.7 min3.125 Gb/s

8.9 hours

1.3 months

10.2 years

5.3 min6.25 Gb/s

4.4 hours

2.7 weeks

5.1 years

12.5 Gb/s

2.2 hours

1.3 weeks

2.5 years

10-13 16.7 min1.1 hours 33 min53 min 26.7 min 13.3 min

10-15 4.6 days 1.4 days 27.8 hours3.63 days 1.85 days 22.2 hours

10-17 1.3 years 7.6 months 3.8 months 1 year 6.1 months 3.1 months

Two 1,000XBER

Reductions

10-12

10-15

10-18

Mean TimeBetween Bit Errors

BER1.7 min3.3 min 2.7 min 1.33 min

4X Growth Capability

MarketDrivers

1: Active compensation (waveshaping, driver pre/de-emphasis, receiver equalization)2: Connector and attachment technology (press-fit, pressure-fit, SMT, BGA)3: Backplane/PCB material (dielectric) and interconnect geometry (via/trace size/shape

TechnologyDomains

Difficult

MoreDifficult

Entry Level

2X Growth Capability

10-20 13 centuries 6.4 centuries 3.2 centuries10-19 1.3 centuries 64 years 32 years

10-21 130 centuries 64 centuries 32 centuries10 centuries

1 century

100 centuries

5.1 centuries

51 years

51 centuries

2.5 centuries

25 years

25 centuries

Signal IntegrityPerformance Trends/Expectations

MostDifficult

A Goal


Bare PCB PCB + Connectors

1 Gb/s

2 Gb/s

3 Gb/s

4 Gb/s

5 Gb/s

6 Gb/s

SI Degradation From Backplane Connectors

Note distortion (eye closure) occurs faster than attenuation (peak-peak amplitude)

Excerpts From Bit StreamEye C

losure Versus Frequency


Sources of Passive InterconnectLosses and Distortions

TraceDielectricVia FieldConnector

X

Conduction Losses 1

Dielectric Losses

Impedance Mismatches 2

Material 4Primary Source of Grief

Undesired Effect

1 5 10 20Data Rate (Gb/s)

PCB/Backplane

XX

XX

X

X

X

Geometry Geometry Geometry

X

Note how geometry (size/shape) in the connector/via field regions dominates the majority of undesired sources of interconnect distortion at higher data rates.

3 Includes via thru/stub ratio effect

1 Includes skin depth, surface roughness and non-uniform current crowding effects2 Includes distributed/lumped element mismatches and memory effects

4 Technology does not exist to tweak at the molecular level. Can only change molecules (materials).

Connectors migrating away from Press-Fit

Via-Fields migrating away

from PTH

Crosstalk

Systemic/Random Variations 3

Loss

esD

isto

rtio

ns


Via stubs introduce horizontal pedestals into the logic transitions resulting in eye closure.

Stubless vias have clean logic transitions and correspondingly larger open eyes.

Backdrilled vias have significantly-reduced pedestal widths and significantly larger eye openings.

Backdrilling to remove a via stub.

Pedestal Height

PedestalWidth

Backdrilling Performance Improvements


Approximate Stub Loss Effects

Stub Length(mils)

Signal Loss(Percent)

1 0.25%

2 0.5%

5 1.25%

10 2.5%

20 5%

40 10%

60 15%

100 25%

150 37.5%

200 50%

250 62.5% 0 50 100 200

0

10

20

30

40

50

150Stub Length (mils)

App

roxi

mat

e Si

gnal

Los

s (%

)

60

250

10% Trace Impedance Mismatch 20 mil Stub = 5% Loss

** Applicable for Dk > 3.5, DF > 0.005, 20 35 mil connector drill diameters, data rates < 8 Gb/s. (This is a rule of thumb, not a design guide.)


Opti-Via (Patent Pending)

Opti-viasare a family of engineered via structures whose S-parameters have been optimized for high speed performance

Adjustment of antipad size/geometry (not always round anymore) of remaining via structure (after backdrilling) for optimum performance. [See Improved Diff Pair Anti-Pad slide for an example.]

Before Optimization After Optimization

Unusable Eye Diagram Usable Eye Diagram

Non-uniform S-parameters Flat S-parameters

12.5 Gb/s Data Rate

Backdrilled Via Stub

Optimizeantipad size/shape

on a per-layer basis,not a per-via basis.


Summary Comparison of Approaches

Backdrilling Lower Df Dielectric

5 15% 200 400 %

Yes No

Yes No

Yes No

Yes No

Relative Cost

Minimize Via Stub Effects

Reduction of Via-Via Xtalk

Reduction of EMI

Significant Distortion Reduction

Consistent Interconnect Response Yes No


Laminate Materials


Dielectric Material Selection

FR4FR406, N4000-6, TUC722TUC752, PCL FR370HR

Ventec 47

Mid Dk/DfFR408, IS620

N4000-12, N4000-13TUC 832, Ventec 46

Low Dk/DfN4000-13SI

Rogers RO4350B, Hitachi LX67Y Megtron6

PTFE / SpecialtiesRogers, Taconic, Arlon

Nelco N9000 series

1x ~ 2x2x ~ 4x4x ~ 100x

Approximate Material Cost Factor

Asian Material Manufacturers are Catching Up


Challenges for Laminate Materials

Too many classesSimplification to manageable level- Core thickness variance- Prepreg flow characteristic

Electrical Properties Fillers Raise Dk No two manufactures measure electricals the

same

Lead free still some performance issuesLower CTEz- Drill-ability- Adhesion to copper & glass

Cost challenge, performance challengeDifferent goal by application- Regional competitiveness- Processability as a part of performance

Halogen free high Tg

Non-dicy mid Tg w/ filler

Non-dicy high Tg w/ very filler

Non-dicy high Tg w/ very filler

Dicy high Tg

Non-dicy high Tg

Non-dicy mid Tg w/ fillerAnd

Halogen FreeOr

Low cost Non-dicy high Tg

Dicy mid Tg

Non-dicy high Tg w/ fillerNon-dicy high Tg w/ filler

Halogen free

Dicy Std. TgDicy std. Tg

Projected PortfolioCurrent Portfolio

TOO MANY FR-4 OPTIONS CURRENTLY ON THE MARKET


High Performance Material Challenges

Electrical Properties- Stable and repeatable - Uniformity

Compatible with thicker boardsLower CTEz- Drill processability

Little competitionAdds demand for:- Processability- Reliability

Asian ( non Japanese) Manufacturers Catching Up

Halogen free a new candidateLower Df is attractive- Cost & availability- Processability- Reliability

0.0025

0.005

0.010

0.020

Df range

Special

Low3.5 ~ 3.7

Middle3.7 ~ 4.0

~ 3.5

FR44.0 ~ 4.8

ClassDk Range

TOO FEW MID and LOW Dk/Df HIGH PERFORMANCE OPTIONS


Leadfree Assembly Challenges

Some materials do not survive lead-free assembly and rework temperatures and cycles

Physical evidence is beneficial. Many defectsAre not evident after assembly

High Pin Count BGA (


PCB Fabricators Must Develop Own Database

TMA: CTEz, Tg, T260Thermal resistance

TGA: Decomposition Temperature (Td)Thermal resistance

m-FSR: Dielectric constant (Dk) Impedance Propagation Delay

Research Triangle Park, NC - June 2007

Documents