Report vlsi and verilog

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Dept. of EC Mangalam College of Engineering

First Semester - 1- VLSI and embedded system design Lab

Expt No:1

Date: 5/9/2013

Half-Adder using gates

AIM: To design and simulate Half-adder using gates.

CIRCUIT DIAGRAM :

TRUTH TABLE:

PROGRAM CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity HALFADDER isPort ( a : in STD_LOGIC;

b : in STD_LOGIC;

sum : out STD_LOGIC;

carry : out STD_LOGIC);

end HALFADDER;architecture Behavioral of HALFADDER is

beginsum<=a xor b;

carry<=a and b;

end Behavioral;

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1





SIMULATION OUTPUT:

RESULT:

The half adder was modeled using VHDL and the waveforms were plotted successfully.

The waveforms tally with the expected behavior of the half adder.





Expt No:2

Date: 5/9/2013

Full-Adder using gates

AIM: To design and simulate Full-adder using gates.

CIRCUIT DIAGRAM :

TRUTH TABLE:

PROGRAM CODE:

library IEEE;


entity FULLADDER is

Port ( a : in STD_LOGIC;b : in STD_LOGIC;

cin : in STD_LOGIC;



end FULLADDER;

A B C SUM CARRY

0 0 0 0 0

0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1

1 1 1 1 1





architecture OPERATION of FULLADDER is

signal x,y,z,n: std_logic;begin

x <= a xor b;sum <= x xor cin;

y <= a and b;

z <= b and cin;

n <= a and cin;

carry <= y or z or n;

end OPERATION;

SIMULATION OUTPUT:

RESULT:

The Full adder was modeled using VHDL and the waveforms were plotted successfully.

The waveforms tally with the expected behavior of the Full adder.





Expt No:3

Date: 5/9/2013

Half-Subtractor using gates

AIM: To design and simulate Half-Subtractor using gates.

CIRCUIT DIAGRAM :

TRUTH TABLE:

PROGRAM CODE:

library IEEE;


entity HALFSUBSTRACTOR is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

diff : out STD_LOGIC;

borrow : out STD_LOGIC);

end HALFSUBSTRACTOR;

architecture Behavioral of HALFSUBSTRACTOR is

signal x : std_logic;

A B Difference BORROW

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0





Dept. of EC

First Semester

Expt No:4

Date: 5/9/2013

AIM: To design and simulate Full-Subtractor

CIRCUIT DIAGRAM :

TRUTH TABLE:

PROGRAM CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.AL

entity FULLSUBSTRACTOR is


b : in STD_LOGIC;

bin : in STD_LOGIC;borrow : out STD_LOGI

diff : out STD_LOGIC);

end FULLSUBSTRACTOR;

A B C DIFFERE

0 0 0 0

0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0

1 1 1 1

M

- 7- VLSI an

Full-Subtractor using gates

sing gates.

L;

;

CE BORROW

0 1 1 1 0 0 0

1

ngalam College of Engineering

embedded system design Lab





architecture Behavioral of FULLSUBSTRACTOR is

signal x,y,z,n,m: std_logic;begin

x <= a xor b;

y<= not a;diff <= x xor bin;

m <=not x;

n <= m and bin;

z <= y and b;

borrow <= z or n;

end Behavioral;

SIMULATION OUTPUT:

RESULT:

The Full subtractor was modeled using VHDL and the waveforms were plotted successfully.

The waveforms tally with the expected behavior of the Full Subtractor.





Expt No:5

Date: 5/9/2013

4x1 MUX using gatesAIM: To design and simulate 4x1MUX using gates.

CIRCUIT DIAGRAM :

TRUTH TABLE:

PROGRAM CODE:

library IEEE;


entity MULTIPLEXER is

Port ( c1 : in STD_LOGIC;

C1 C2 OUTPUT

0 0 X0

0 1 X1

1 0 X2

1 1 X3





c2 : in STD_LOGIC;

c3 : in STD_LOGIC;c4 : in STD_LOGIC;

a : in STD_LOGIC;

b : in STD_LOGIC;d : out STD_LOGIC);

end MULTIPLEXER;

architecture Behavioral of MULTIPLEXER is

signal y,z,n,m,l,o : std_logic;

begin

y <= not a;

z <= not b;

n <= c1 and y and z;m <= c2 and y and b;

l <= c3 and a and z;

o <= c4 and a and b;d <= n or m or l or n;

end Behavioral;

SIMULATION OUTPUT:

RESULT:

The 4x1MUX was modeled using VHDL and the waveforms were plotted successfully.

The waveforms tally with the expected behavior of the 4x1 MUX .





Expt No:6

Date: 5/9/2013

4x1 MUX using gatesAIM: To design and simulate 1x4 DEMUX using gates.

CIRCUIT DIAGRAM :

TRUTH TABLE:

INPUT OUTPUT

D A B Y0 Y1 Y2 Y3

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1







RESULT:

The 1x4 DEMUX was modeled using VHDL and the waveforms were plotted successfully.

The waveforms tally with the expected behavior of the 1x4 DEMUX .









Expt No:8

Date: 8/9/2013

3x8 Decoder using gatesAIM: To design and simulate 3x8 Decoder using gates.

CIRCUIT DIAGRAM :

TRUTH TABLE:

A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 1





PROGRAM CODE:

library IEEE;


entity decoder is


b : in STD_LOGIC;

c : in STD_LOGIC;d : out STD_LOGIC_vector(7 downto 0));

end decoder;

architecture Behavioral of decoder is

signal x,y,z: std_logic;

begin

x <= not a;

y <= not b;

z <= not c;d(0) <= x and y and z;

d(1) <= x and y and c;

d(2) <= x and b and z;

d(3) <= x and b and c;

d(4) <= a and y and z;

d(5) <= a and y and c;

d(6) <= a and b and z;

d(7) <= a and b and c;end Behavioral;

SIMULATION OUTPUT:

RESULT:

The 3x8 Decoder was modeled using VHDL and the waveforms were plotted successfully.

The waveforms tally with the expected behavior of the 3x8 Decoder.





Expt No:9

Date: 10/9/2013

Full Adder using Half AddersAIM: To design and simulate Full Adder using Half Adder.

CIRCUIT DIAGRAM :

TRUTH TABLE:

PROGRAM CODE:

library IEEE;


entity fulladder is

Port ( ain : in STD_LOGIC;bin : in STD_LOGIC;

cin : in STD_LOGIC;

s : out STD_LOGIC;

A B C SUM CARRY

0 0 0 0 0

0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1

1 1 1 1 1





c : out STD_LOGIC);

end fulladder;

architecture Behavioral of fulladder is

signal s1,s2,m1 : std_logic;component HALFADDERport(a,b: in std_logic;

sum,carry: out std_logic);

end component;

component or1

port(w,q: in std_logic;

r: out std_logic);

end component;

beginha1: HALFADDER port map (ain,bin,s1,s2);

ha2: HALFADDER port map (cin,s1,s,m1);o1: or1 port map (m1,s2,c);

end Behavioral;

Half adder :library IEEE;

use IEEE.STD_LOGIC_1164.ALL;entity HALFADDER is


b : in STD_LOGIC;



end HALFADDER;

architecture Behavioral of HALFADDER is

beginsum<=a xor b;

carry<=a and b;

end Behavioral;

OR :

library IEEE;


entity or1 isPort ( w : in STD_LOGIC;

q : in STD_LOGIC;

r : out STD_LOGIC);

end or1;

architecture Behavioral of or1 is

begin

r <= w or q;end Behavioral;







Expt No:10

Date: 10/9/2013

Full Subtractor using Half SubtractorAIM: To design and simulate Full Subtractor using Half Subtractor.

CIRCUIT DIAGRAM :

TRUTH TABLE:

PROGRAM CODE:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity fullsubtractor is

Port ( qin : in STD_LOGIC;

win : in STD_LOGIC;

rin : in STD_LOGIC;d : out STD_LOGIC;

bo : out STD_LOGIC);

end fullsubtractor;

A B C DIFFERENCE BORROW 0 0 0 0 0

0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0

1 1 1 1 1





architecture Behavioral of fullsubtractor is

component HALFSUBSTRACTOR

port(a,b: in std_logic;

diff,borrow: out std_logic);

end component;component or1port(w,q: in std_logic;

r: out std_logic);

end component;

signal d1,d2,d3: std_logic;

begin

hs1: HALFSUBSTRACTOR port map(qin,win,d1,d2);

hs2: HALFSUBSTRACTOR port map (d1,rin,d,d3);

o1: or1 port map(d2,d3,bo);end Behavioral;

Half Subtractor :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;entity HALFSUBSTRACTOR is

Port ( a : in STD_LOGIC;b : in STD_LOGIC;

diff : out STD_LOGIC;

borrow : out STD_LOGIC);

end HALFSUBSTRACTOR;

architecture Behavioral of HALFSUBSTRACTOR is

signal x : std_logic;

begin

x <= not a;diff <= a xor b;

borrow <= x and b;

end Behavioral;

OR :

library IEEE;


entity or1 isPort ( w : in STD_LOGIC;

q : in STD_LOGIC;

r : out STD_LOGIC);

end or1;

architecture Behavioral of or1 is

begin

r <= w or q;end Behavioral;





SIMULATION OUTPUT:

RESULT:

The Full Subtractor was modeled using VHDL and the waveforms were plotted successfully.

The waveforms tally with the expected behavior of the Full Subtractor.





Expt No:11

Date: 10/9/2013

4x1 MUX using 2x1 MUXAIM: To design and simulate 4x1 MUX using 2x1 MUX.

CIRCUIT DIAGRAM :

TRUTH TABLE:

PROGRAM CODE:

library IEEE;


entity multiplexer4x1using2x1 is

Port ( s : in STD_LOGIC_vector(3 downto 0);

c : in STD_LOGIC_vector(1 downto 0);

o : out STD_LOGIC);

C1 C2 OUTPUT

0 0 X0

0 1 X1

1 0 X2 1 1 X3





end multiplexer4x1using2x1;

architecture Behavioral of multiplexer4x1using2x1 is

signal s4,s5:std_logic;

component MUX2

Port ( a : in STD_LOGIC;b : in STD_LOGIC;s : in STD_LOGIC;

o : out STD_LOGIC);

end component;

begin

o1: MUX2 port map (s(0),s(1),c(0),s4);

o2:MUX2 port map(s(2),s(3),c(0),s5);

o3:MUX2 port map (s4,s5,c(1),o);

end Behavioral;

2x1 MUX :

library IEEE;


entity MUX2 isPort ( a : in STD_LOGIC;

b : in STD_LOGIC;s : in STD_LOGIC;

o : out STD_LOGIC);

end MUX2;

architecture Behavioral of MUX2 is

signal m:std_logic_vector(2 downto 0);

begin

m(0) <= s and a;

m(1) <= not s;m(2) <= m(1) and b;

o <= m(0) or m(2);

end Behavioral;





SIMULATION OUTPUT:

RESULT:

The 4x1 MUX was modeled using VHDL and the waveforms were plotted successfully.

The waveforms tally with the expected behavior of the 4X1 MUX.





Expt No:12

Date: 10/9/2013

Ripple Carry AdderAIM: To design and simulate Ripple carry adder.

CIRCUIT DIAGRAM :

PROGRAM CODE:

library IEEE;


entity RADD isPort ( a : in STD_LOGIC_vector(3 downto 0);

b : in STD_LOGIC_vector(3 downto 0);c: in STD_LOGIC;

ca : inout STD_LOGIC_vector(3 downto 0);su : out STD_LOGIC_vector(3 downto 0));

end RADD;

architecture Behavioral of RADD is

component fulladder

Port ( ain : in STD_LOGIC;

bin : in STD_LOGIC;

cin : in STD_LOGIC;s : out STD_LOGIC;c : out STD_LOGIC);

end component;

begin

fa1: fulladder port map(a(0),b(0),c,su(0),ca(0));

fa2: fulladder port map(a(1),b(1),ca(0),su(1),ca(1));



end Behavioral;





Full Adder:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;entity FULLADDER is


b : in STD_LOGIC;

cin : in STD_LOGIC;



end FULLADDER;

architecture OPERATION of FULLADDER issignal x,y,z,n: std_logic;

begin

x <= a xor b;sum <= x xor cin;

y <= a and b;

z <= b and cin;n <= a and cin;

carry <= y or z or n;end OPERATION;

SIMULATION OUTPUT:

RESULT:

The Ripple Carry Adder was modeled using VHDL and the waveforms were plotted successfully.

The waveforms tally with the expected behavior of the Ripple Carry Adder.







r : in STD_LOGIC;

rst: in std_logic;q : inout STD_LOGIC;

qbar : inout STD_LOGIC;

e : in STD_LOGIC);end srflipflop;

architecture Behavioral of srflipflop is

begin

process (r,s,rst,e,q,qbar)

begin

if (e = '1' and e'event) then

if (rst = '1') then

q <= '0';qbar <= '1';

else

if (s ='0' and r= '0') thenq <= q;

qbar <= qbar;

elsif (s='0' and r= '1') thenq <='0';

qbar <='1';elsif (s='1' and r='0') then

q <='1';

qbar <='0';

elsif (s='1' and r='1') then

q <= 'X';

qbar <= 'X';

end if;

end if;end if;

end process;

end Behavioral;

SIMULATION OUTPUT:

RESULT:

The SR Flipflop was modeled using VHDL and the waveforms were plotted successfully.

The waveforms tally with the expected behavior of the SR Flipflop.





Expt No:14

Date: 12/9/2013

J-K FlipflopAIM: To design and simulate J-K Flipflop.

CIRCUIT DIAGRAM :

TRUTH TABLE:

Q(t) J K Q(t+1)

0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0

PROGRAM CODE:

library IEEE;


entity jkflipflop is

Port ( j : in STD_LOGIC;

k : in STD_LOGIC;

qout : inout STD_LOGIC;

qn : inout STD_LOGIC;clk : in STD_LOGIC;

rst : in std_logic);

end jkflipflop;







Dept. of EC

First Semester

Expt No:15

Date: 12/9/2013

AIM: To design and simulate D Flipflop.

CIRCUIT DIAGRAM :

TRUTH TABLE:

PROGRAM CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.AL

entity dfliflo isPort ( d : in STD_LOGIC;

q : inout STD_LOG cl

rst: in std

qn : inout STD_LOGIC);

end dfliflo;

architecture Behavioral of dfliflobegin

process(d,clk,rst)begin

if (rst = '1') then

q <= '0';

Q(t) D Q(t+1)

0 0 0

0 1 1

1 0 0

1 1 1

M

- 34- VLSI a

D Flipflop

L;

C;: in std_logic;

logic;

is


d embedded system design Lab





qn<= '0';

elseif (clk = '1' and clk'event) then

q <= d;

qn<= not q;end if;

end if;

end process;

end Behavioral;

SIMULATION OUTPUT:

RESULT:

The D Flipflop was modeled using VHDL and the waveforms were plotted successfully.

The waveforms tally with the expected behavior of the D Flipflop.





Expt No:16

Date: 12/9/2013

T FlipflopAIM: To design and simulate T Flipflop.

CIRCUIT DIAGRAM :

TRUTH TABLE:

Q(t) T Q(t+1)

0 0 0 0 1 1

1 0 1

1 1 0

PROGRAM CODE:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity tflipflop is

Port ( t : in STD_LOGIC;clk : in STD_LOGIC;

rst : in STD_LOGIC;

q : inout STD_LOGIC;

qn : inout STD_LOGIC;

qout : out STD_LOGIC);

end tflipflop;architecture Behavioral of tflipflop is

begin

process (clk,rst,t)

begin





if (rst ='1') then

q <= '0';qn<= '1';

else

if ( clk = '1' and clk'event) thenif (t = '0') then

q <= q;

qn<= qn;

else

q <= not q;

qn<= not qn;

end if;

end if;end if;

qout<= qn;

end process;end Behavioral; SIMULATION OUTPUT:

RESULT:

The T Flipflop was modeled using VHDL and the waveforms were plotted successfully.

The waveforms tally with the expected behavior of the T Flipflop.





Expt No:17

Date: 24/9/2013

Serial In Serial Out Shift RegisterAIM: To design and simulate Serial In Serial Out Shift Register.

CIRCUIT DIAGRAM :

PROGRAM CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;entity siso is

Port ( din : in STD_LOGIC;

clk : in STD_LOGIC;

rst : in STD_LOGIC;qout : out STD_LOGIC);

end siso;architecture Behavioral of siso is

signal q: std_logic_vector(2 downto 0);

begin

process (din,clk,rst)

beginif (rst = '1') then

qout <= '0';else

if (clk = '1' and clk'event) then

if (din = '1') then

q(0) <= din;

q(1) <= q(0);

q(2) <= q(1);

qout <= q(2);

end if;





end if;

end if;end process;

end Behavioral;

SIMULATION OUTPUT:

RESULT:

The SISO Shift Register was modeled using VHDL and the waveforms were plotted successfully.

The waveforms tally with the expected behavior of the SISO Shift Register.





Expt No:18

Date: 24/9/2013

Serial In Parallel Out Shift RegisterAIM: To design and simulate Serial In Parallel Out Shift Register.

CIRCUIT DIAGRAM :

PROGRAM CODE:

library IEEE;


entity sipo isPort ( din : in STD_LOGIC;

q : inout STD_LOGIC_VECTOR (2 downto 0);

clk : in STD_LOGIC;

rst : in STD_LOGIC;

qout : out STD_LOGIC);end sipo;

architecture Behavioral of sipo is

begin

process (din,clk,rst)

begin

if (rst = '1') thenqout <= '0';

q(0) <= '0';q(1) <= '0';

q(2) <= '0';

else







Expt No: 19

Date: 24/9/2013

PARALLEL IN SERIAL OUT SHIFT REGISTER(PISO)

AIM:

To design and simulate parallel in serial out shift register.

CIRCUIT DIAGRAM:

PROGRAM CODE:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity piso is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

o : out STD_LOGIC;

rst : in STD_LOGIC;

load : in std_logic;

clk : in STD_LOGIC);

end piso;

architecture Behavioral of piso is





Signal t: std_logic_vector(3 downto 0);

begin

process (a,clk,rst)

begin

if rst ='1' then

o<= '0';

elsif (clk ='1' and clk'event) then

case load is

when '1' => t<=a;

o<= a(3);

when others=>

t(2)<= t(3);

t(1)<= t(2);

t(0)<= t(1);

o<= t(0);

end case;

end if;

end process;

end Behavioral;

OUTPUT:

RESULT:

The parallel in serial out shift register is designed and simulated. The output is verified.





Expt No: 20

Date: 24/9/2013

PARALLEL IN PARALLEL OUT SHIFT REGISTER(PIPO)

AIM:

To design and simulate parallel in parallel out shift register(PIPO).

CIRCUIT DIAGRAM:

PROGRAM CODE:

library IEEE;


entity pipo is

Port ( d : in STD_LOGIC_VECTOR (3 downto 0);

q : out STD_LOGIC_VECTOR (3 downto 0);

clk : in STD_LOGIC;

rst : in STD_LOGIC);

end pipo;

architecture Behavioral of pipo is

begin

process (d,clk,rst)

begin

if (rst = '1') then

q(3)<= '0';

q(2)<= '0';





q(1)<= '0';

q(0)<='0';

else

if (clk = '1' and clk'event) then

q(0) <= d(0);

q(1) <= d(1);

q(2) <= d(2);

q(3) <= d(3);

end if;

end if;

end process;

end Behavioral;

OUTPUT:

RESULT:

The parallel in parallel out shift register is designed and simulated.The output is verified.



Dept. of EC

First Semester

Expt No: 21

Date: 1/10/2013

DESI

AIM:

To develop a source code for arithe

CIRCUIT DIAGRAM:

TRUTH TABLE:

M

- 46- VLSI a

N OF ARITHEMETIC AND LOGIC UNIT

etic and logic unit by using vhdl.







PROGRAM CODE:

library IEEE;


use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all; entity alu is


b : in STD_LOGIC_VECTOR (7 downto 0);

s : in STD_LOGIC_VECTOR (3 downto 0);

y: out STD_LOGIC_VECTOR (7 downto 0);

cin: in STD_LOGIC);

end alu;

architecture Behavioral of alu is

signal p,n : std_logic_vector(7 downto 0);

component arithmatic




cin: in STD_LOGIC;

q : out STD_LOGIC_VECTOR (7 downto 0));

end component;

component logic





end component;

component mux



s : in STD_LOGIC;





y : out STD_LOGIC_VECTOR (7 downto 0));

end component;

begin

AR: arithmatic port map(a,b,s(2 downto 0),cin,p);

LO: logic port map(a,b,s(2 downto 0),n);

MUX1: mux port map(p,n,s(3),y);

end Behavioral;

Arithmetic:

entity arithmatic is




cin: in STD_LOGIC;


end arithmatic;

architecture Behavioral of arithmatic is

begin

process (a,b,cin,s)

begin

case (s) is

when "000" => q <= a;

when "001" => q<= a +1;

when "010" => q <= a-1;

when "011" =>q <= b;

when "100" =>q<= b+1;

when "101"=>q<=b-1;

when "110" =>q<=a+b;

when "111"=>q<=cin+a+b;

when others =>q<="00000000";





end case;

end process;

end Behavioral;

Logic:

library IEEE;



use ieee.std_logic_unsigned.all;

entity logic is





end logic;

architecture Behavioral of logic is

begin

process (a,b,s)

begin

case (s) is

when "000" => q <= not a;

when "001" => q<= not b;

when "010" => q <= a and b;

when "011" =>q <= a or b;

when "100" =>q<= a nand b;

when "101"=>q<= a nor b;

when "110" =>q<=a xor b;

when "111"=>q<=a xnor b;

when others =>q<="00000000";

end case;





end process;

end Behavioral;

MUX:

library IEEE;


entity mux is



s : in STD_LOGIC;


end mux;

architecture Behavioral of mux is

begin

process (a,b,s)

begin

if (s = '0') then

y <= a;

elsif(s = '1') then

y <= b;

end if;

end process;

end Behavioral;





OUTPUT:

RESULT:

The ALU is designed and simulated. The output is verified.



Dept. of EC

First Semester

Expt No: 22

Date: 1/10/2013

AIM:

To design and simulate a 4 bit upcou

CIRCUIT DIAGRAM:

PROGRAM CODE:

library IEEE;



use ieee.std_logic_unsigned.all; enti

entity upc is

Port ( rst : in STD_LOGIC;

clk : in STD_LOGIC;

qout : out STD_LOGIC_vect

end upc;

architecture Behavioral of upc is

component tflipflop is

Port ( t : in STD_LOGIC;

M

- 52- VLSI a

UP COUNTER

nter.

ty alu is

or(3 downto 0 ));







clk : in STD_LOGIC;

rst : in STD_LOGIC;




end component;

signal q:std_logic_vector(5 downto 0 );

begin

q(2) <= q(0) and q(1);

q(4) <= q(1) and q(0) and q(3);

qout <= (q(5),q(3),q(1),q(0));

t1: tflipflop port map ('1',clk,rst,q(0));

t2: tflipflop port map(q(0),clk,rst,q(1));



end Behavioral;

T Flipflop:

library IEEE;


entity tflipflop is


clk : in STD_LOGIC;

rst : in STD_LOGIC;




end tflipflop;

architecture Behavioral of tflipflop is







Dept. of EC

First Semester

Expt No: 23

Date: 1/10/2013

AIM:

To design and simulate a 4 bit down

CIRCUIT DIAGRAM:

PROGRAM CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.A



entity downc is

Port ( clk : in STD_LOGIC;

rst : in STD_LOGIC;

qout : out STD_LOGIC_VE

end downc;

M

- 56- VLSI a

DOWN COUNTER

counter.

LL;

TOR (3 downto 0));







architecture Behavioral of downc is

component tflipflop is


clk : in STD_LOGIC;

rst : in STD_LOGIC;




end component;

signal q:std_logic_vector(9 downto 0 );

begin

q(0)<= not q(6);

q(1)<= not q(7);

q(3)<= not q(8);

q(5)<= not q(9);

q(2) <= q(0) and q(1);

q(4) <= q(1) and q(0) and q(3);

qout <= (q(9),q(8),q(7),q(6));

t1: tflipflop port map ('1',clk,rst,q(6));




end Behavioral;

T Flipflop:

library IEEE;


entity tflipflop is






clk : in STD_LOGIC;

rst : in STD_LOGIC;




end tflipflop;

architecture Behavioral of tflipflop is

begin

process (clk,rst,t)

begin

if (rst ='1') then

q <= '0';

qn<= '1';

else

if ( clk = '1' and clk'event) then

if (t = '0') then

q <= q;

qn<= qn;

else

q <= not q;

qn<= not qn;

end if;

end if;

end if;

qout<= qn;

end process;

end Behavioral;







Expt No: 24

Date: 1/10/2013

UP DOWN COUNTER

AIM:

To design and simulate an updown counter using vhdl.

CIRCUIT DIAGRAM:

PROGRAM CODE:

library IEEE;




entity updownc is


clk : in STD_LOGIC;

s1 : in STD_LOGIC;

y : out STD_LOGIC_vector(3 downto 0));

end updownc;

architecture Behavioral of updownc is

component downc






rst : in STD_LOGIC;

qout : out STD_LOGIC_VECTOR (3 downto 0));

End component;

component upc


clk : in STD_LOGIC;

qout : out STD_LOGIC_vector(3 downto 0 ));

End component;

Component mux21



s : in STD_LOGIC;


End component;

Signal a,b: std_logic_vector(3 downto 0);

begin

d1: downc port map (clk,rst,a);

u1:upc port map(rst,clk,b);

mu1:mux21 port map (a,b,s1,y);

end Behavioral;





OUTPUT:

RESULT:

The updown counter is designed and simulated. The output was verified.



Dept. of EC

First Semester

Expt No: 25

Date: 8/10/2013

AIM:

To write the vhdl code for moore m

CIRCUIT DIAGRAM:

PROGRAM CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.

entity mofsm is


clk : in STD_LOGIC;

z : out STD_LOGIC);

end mofsm;

architecture Behavioral of mofsm is

type more_state is (s0,s1,s2,s3);

signal state_type: more_state;

begin

process (clk,a)

begin

M

- 63- VLSI a

MOORE MACHINE

chine and simulate.

LL;







if (clk ='1' and clk'event) then

case state_type is

when s0 => z<='1';

if (a = '1') then

state_type <= s2;

end if;

when s1 => z <= '0';

if (a = '1') then

state_type <= s3;

end if;

when s2 => z <= '0';

if (a = '0') then

state_type <= s1;

else

state_type <= s3;

end if;

when s3 => z <= '1';

if (a = '1' )then

state_type <= s0;

end if;

end case;

end if;

end process;

end Behavioral;





OUTPUT:

RESULT:

The moore machine was simulated. The output is verified.



Dept. of EC

First Semester

Expt No: 26

Date: 8/10/2013

AIM:

To write the vhdl code for mealy ma

CIRCUIT DIAGRAM:

PROGRAM CODE:

library IEEE;


entity mealy is


clk,rst : in STD_LOGIC;

z : out STD_LOGIC);

end mealy;

architecture Behavioral of mealy is

type mealy_type is (s0,s1,s2,s3);

signal p_state,n_state: mealy_type;

begin

process (p_state,a,n_state,clk,rst)

begin

if (rst = '1') then

M

- 66- VLSI a

MEALY MACHINE

chine and simulate.

LL;







p_state<= s0;

n_state<= s0;

end if;

if( clk = '1' and clk'event) then

p_state<= n_state;

case p_state is

when s0 =>

if (a = '1') then

z <= '1';

n_state<= s3;

else

z <= '0';

end if;

when s1 =>

if (a = '1') then

z <= '0';

n_state <= s0;

else

z <= '1';

end if;

when s2 =>

if (a = '1') then

z <= '1';

n_state<= s1;

else

z <= '0';

end if;

when s3 =>

z <='0';

if (a = '1') then











z <= '1';

state<= a;

end if ;

end case;

end if;

end process;

end Behavioral;

OUTPUT:

RESULT:

The sequence detector 1011 is simulated. The output is verified.





Expt No: 28

Date: 17/10/2013

SEQUENCE DETECTOR 11011

AIM:

To write the vhdl code for sequence detector 11011 and simulate.

CIRCUIT DIAGRAM:

PROGRAM CODE:

library IEEE;


entity sequence is

Port (clk : in STD_LOGIC;

s : in STD_LOGIC;

z : out STD_LOGIC);

end sequence;

architecture Behavioral of sequence is

type state_type is(a,b,c,d,e);

signal mealy_state:state_type;

begin





process(clk)

begin

if(clk='0')then

case mealy_state is

when a=>

if(s='0')then

mealy_state<=a;

z<='0';

else

mealy_state<=b;

z<='0';

end if;

when b=>

if(s='0')then

mealy_state<=a;

z<='0';

else

mealy_state<=c;

z<='0';

end if;

when c=>

if(s='0')then

mealy_state<=d;

z<='0';

else

mealy_state<=a;

z<='0';

end if;

when d=>

if(s='0')then





mealy_state<=a;

z<='0';

else

mealy_state<=e;

z<='0';

end if;

when e=>

if(s='0')then

mealy_state<=e;

z<='0';

else

mealy_state<=a;

z<='1';

end if;

end case;

end if;

end process;

end Behavioral;





OUTPUT:

RESULT:

The sequence detector 11011 was simulated. The output is verified.



Dept. of EC

First Semester

Expt No: 29

Date: 22/10/2013

AIM:

To write the vhdl code for clock divi

CIRCUIT DIAGRAM:

PROGRAM CODE:

library IEEE;


entity clkdiv is

generic (n: positive:=4);


clkdiv : inout STD_LOGIC;

rst : in STD_LOGIC;

clkout : out STD_LOGIC);

end clkdiv;

architecture Behavioral of clkdiv is

begin

process (clk,clkdiv,rst)

variable count : natural;

begin

clkout<=clkdiv;

M

- 76- VLSI a

CLOCK DIVIDER

der and simulate.

LL;







if rst = '1' then

clkdiv <='0';

count := 0;

elsif clk = '1' and clk'event then

count := count + 1;

if count = n then

count := 0;

clkdiv <= not clkdiv;

end if;

end if;

end process;

end Behavioral;

OUTPUT:

RESULT:

The clock divider was simulated. The output is verified.





Expt No: 30

Date: 29/10/2013

UNIVERSAL SHIFT REGISTER

AIM:

To write the vhdl code for USR and simulate.

CIRCUIT DIAGRAM:

PROGRAM CODE:

library IEEE;


entity unishifreg is

Port ( i : in STD_LOGIC_VECTOR (3 downto 0);

sr : in STD_LOGIC;

sl : in STD_LOGIC;

a : inout STD_LOGIC_VECTOR (3 downto 0);





clk : in STD_LOGIC;

rst : in STD_LOGIC;

s : in STD_LOGIC_VECTOR (1 downto 0));

end unishifreg;

architecture Behavioral of unishifreg is

signal n,b,c,d:std_logic;

component MULTIPLEXER

Port ( c4 : in STD_LOGIC;

c3 : in STD_LOGIC;

c2 : in STD_LOGIC;

c1 : in STD_LOGIC;

a : in STD_LOGIC_vector( 1 downto 0 ) ;

y : out STD_LOGIC);

end component;

component dfliflo

Port ( d : in STD_LOGIC;


clk: in std_logic;

rst: in std_logic;

qn : inout STD_LOGIC);

end component;

begin

m3: MULTIPLEXER port map(i(3),sl,a(2),a(3),s,d);

m0: MULTIPLEXER port map(i(0),a(1),sr,a(0),s,n);

m1: MULTIPLEXER port map(i(1),a(2),a(0),a(1),s,b);

m2: MULTIPLEXER port map(i(2),a(3),a(1),a(2),s,c);

d1: dfliflo port map (n,a(0),clk,rst);

d2: dfliflo port map (b,a(1),clk,rst);

d3: dfliflo port map (c,a(2),clk,rst);





d4: dfliflo port map (d,a(3),clk,rst);

end Behavioral;

OUTPUT:

RESULT:

The universal shift register was simulated and the output is verified.





Expt No: 31

Date: 29/10/2013

INSTRUCTION DECODER

AIM:

To write the vhdl code for instruction decoder and simulate.

CIRCUIT DIAGRAM:

PROGRAM CODE:

library IEEE;


entity idec is

Port ( d : in STD_LOGIC_VECTOR (7 downto 0);

hlt : out STD_LOGIC;

jmp : out STD_LOGIC;

lda : out STD_LOGIC;





add : out STD_LOGIC;

sub : out STD_LOGIC;

sta : out STD_LOGIC;

mjmp : out STD_LOGIC;

pjmp : out STD_LOGIC;

input : out STD_LOGIC;

output : out STD_LOGIC;

als : out STD_LOGIC;

ars : out STD_LOGIC;

lls : out STD_LOGIC;

lrs : out STD_LOGIC);

end idec;

architecture Behavioral of idec is

signal s:std_logic_vector(7 downto 0);

signal v,q,n,t:std_logic;

component and2

Port ( a,b : in STD_LOGIC;

y : out STD_LOGIC);

end component;

component and3

Port ( a1,a2,a3 : in STD_LOGIC;

y : out STD_LOGIC);

end component;

component and5

Port ( a1 : in STD_LOGIC;

a2 : in STD_LOGIC;

a3 : in STD_LOGIC;

a4 : in STD_LOGIC;

a5 : in STD_LOGIC;

y : out STD_LOGIC);





end component;

component and6

Port ( a1 : in STD_LOGIC;

a2 : in STD_LOGIC;

a3 : in STD_LOGIC;

a4 : in STD_LOGIC;

a5 : in STD_LOGIC;

a6 : in STD_LOGIC;

y : out STD_LOGIC);

end component;

component nornin

Port ( b : in STD_LOGIC;

c : in STD_LOGIC;

d : in STD_LOGIC;

y : out STD_LOGIC);

end component;

begin

s<= not d;

t<= not n;

i1: nornin port map (d(0),d(1),d(2),v);

i2:and3 port map (d(0),d(1),d(2),q);

i3:and3 port map(s(0),s(1),d(2),lda);

i4:and3 port map(s(0),d(1),s(2),add);

i5:and3 port map(s(0),d(1),d(2),sub);

i6:and3 port map(d(0),s(1),s(2),sta);

i7:and3 port map(s(0),d(1),s(2),mjmp);

i8:and3 port map(d(0),s(1),d(2),pjmp);

i9:and5 port map(s(3),s(4),s(5),s(6),s(7),n);

i10:and6 port map (s(3),s(4),d(5),s(6),s(7),q,output);



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