1 | Page MA IMPLEMENTATION O Submitted in Partial F ELECTRONICS A DEPARTMENT OF B.T.KUMAON INSTIT UTTRAKHAND T AJOR PROJECT REPORT ON OF STAR TOPOLOGY FOR NOC ROUTE VERILOG Fulfillment of the requirements for the aw Degree of Bachelor of Technology in AND COMMUNICATION ENGINEER Submitted by VINOD DEOLAL (110180102135) VIKAS TIWARI (110180102133) SHIVAM SAINI (110180102116) Under the supervision of Mr. Vikash Sharma ELECTRONICS & COMM. ENGINE TUTE OF TECHNOLOGY DWARAHA TECHNICAL UNIVERSITY, DEHRA ER USING ward of RING EERING AT-263653 ADUN
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MAJOR PROJECT REPORT ON
IMPLEMENTATION OF
Submitted in Partial Fulfillment of the requirements for the award of
ELECTRONICS AND COMMUNICATION ENGINEERING
DEPARTMENT OF ELECTRONICS & COMM.
B.T.KUMAON INSTITUTE OF TECHNOLOGY DWARAHAT
UTTRAKHAND TECHNICAL UNIVERSITY, DEHRADUN
MAJOR PROJECT REPORT ON
IMPLEMENTATION OF STAR TOPOLOGY FOR NOC ROUTER USING VERILOG
Submitted in Partial Fulfillment of the requirements for the award of
Degree of
Bachelor of Technology
in
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted by
VINOD DEOLAL (110180102135)
VIKAS TIWARI (110180102133)
SHIVAM SAINI (110180102116)
Under the supervision of
Mr. Vikash Sharma
DEPARTMENT OF ELECTRONICS & COMM. ENGINEERING
B.T.KUMAON INSTITUTE OF TECHNOLOGY DWARAHAT
UTTRAKHAND TECHNICAL UNIVERSITY, DEHRADUN
FOR NOC ROUTER USING
Submitted in Partial Fulfillment of the requirements for the award of
ELECTRONICS AND COMMUNICATION ENGINEERING
ENGINEERING
B.T.KUMAON INSTITUTE OF TECHNOLOGY DWARAHAT-263653
UTTRAKHAND TECHNICAL UNIVERSITY, DEHRADUN
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This is to certify that the
Topology for NoC Router
No.110180102116), Vikas Tiwari
Deolal (Roll No. 110180102135
the award of Bachelor of
Engineering of the Bipin Tripathi Kumaon Institute of Technology Dwarahat,
Uttarakhand Technical University, Dehradun
work carried out by them under my supervision and guidance.
Mr. Vikash Sharma Dr. R.S. Prasad
PROJECT GUIDE
Bipin Tripathi Kumaon InstDepartment of Electronics and Communication Engineering
Dwarahat (Almora)
CERTIFICATE
This is to certify that the Major Project entitled “Implementation of Star
Topology for NoC Router” which is being submitted by Shivam Saini
Vikas Tiwari (Roll No. 110180102133) and Vinod Kumar
(Roll No. 110180102135) for the partial fulfillment of the requirements for
Bachelor of Technology in Electronics Communication
Bipin Tripathi Kumaon Institute of Technology Dwarahat,
Uttarakhand Technical University, Dehradun is a record of candi
work carried out by them under my supervision and guidance.
Mr. Vikash Sharma Dr. R.S. Prasad
PROJECT GUIDE PROFESSOR
Bipin Tripathi Kumaon Institute of TechnologyDepartment of Electronics and Communication Engineering
Dwarahat (Almora) – 263653, Uttarakhand
Implementation of Star
Shivam Saini(Roll
Vinod Kumar
for the partial fulfillment of the requirements for
Electronics Communication
Bipin Tripathi Kumaon Institute of Technology Dwarahat,
is a record of candidate’s own
Mr. Vikash Sharma Dr. R.S. Prasad
PROFESSOR & HEAD
tute of Technology Department of Electronics and Communication Engineering
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ACKNOWLEDGEMENT
We take this opportunity to express my profound gratitude and deep regards to my
guide Mr. Vikas Sharma for his exemplary guidance, monitoring and constant
encouragement throughout the project. The blessing, help and guidance given by
him time to time shall carry us a long way in the journey of life on which we are
about to embark.
We are grateful to Dr. R.S. Prasad (Head of Department, Electronics and
Communication Engineering) for being a great motivator and for providing
necessary facilities in the department.
We also take this opportunity to express a deep sense of gratitude to all ECE staff
members for their cordial support, valuable information and guidance, which helped
us in completing this task through various stages.
Lastly, we thank almighty, my parents, brother and friends for their constant
encouragement without which this assignment would not be possible.
Date
Place Shivam saini
110180102116
Vikas Tiwari
110180102133
Vinod Kumar Deolal
110180102135
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TABLE OF CONTENTS .
CERTIFICATE i
ACKNOWLEDGEMENT ii
TABLE OF CONTENT iii
LIST OF FIGURES v
ABSTRACT vi
Chapter1
Introduction 1.1 Introduction to NOC router for SOC communication…………….….………....……..1 1.2 Requirement for NOC router……………………………………….………….…..…..1 1.3 NOC Router Architecture……………………………………………….…….……….2
Chapter 2 Introduction To VERILOG
2.1 Hardware descriptive languages (HDL)………………………………………………..3 2.2 Verilog HDL…………………………………………………………………………...3 2.3 Levels of Design abstraction…………………………………………………………...3 2.4 Components of a Verilog Module……………………………………………………...4 2.5 Gate level Modeling…………………………………………………………………....4 2.6 Behavioral Modeling…………………………………………………………………...5 2.7 Operator types……………………………………………………………………….....5 2.8 Initial statement………………………………………………………………………...5 2.9 Always statement……………………………………………………………………....6
Chapter 3 3.1 Arbiter
3.1.1 Round Robin Arbiter Design…………………………………………………..7 3.1.2 Bus Arbiter Design…………………………………………………………….7 3.1.3 Truth table for 4x4 Priority Logic Block………………………………………8 3.1.4 Assumptions for Arbiter Design…………………………………………….....9
3.2 Routing Engine and Look Up Table ……….………………………………...9 3.3 Crossbar Switch…………………………………………………………………..10
3.3.1 Flowchart for crossbar switch………………………….……………………….11
3.4 FIFO Buffer 3.4.1 Working of Circular FIFO Buffer…………………………………….……….....11
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3.4.2 Flowchart for circular FIFO……………………………………………………...12
Chapter 4 Star topology Implementation of NoC Router
4.1 NoC Topologies……………………………………………………………………13 4.2 Star Topology………………………………………………………………………14
4.3 Data flow in Star topology ………………………………………………………...15
Chapter 5 Simulations and Results 5.1 Input Arbiter
4. Equality: ==, !=, ===(case equality including x and z) , !==
5. Bitwise operators: ~, &, |, ^, ^~ or ~^
6. Reduction: &, ~&, |, ~|, ^, ^~ or ~^
7. Shift: >>, <<, >>> (Arithmetic right shift), <<<
8. Concatenation: { }
9. Replication: { { } }
10. Conditional: ?:
2.8 Initial statement
• All statements inside an initial statement constitute an initial block.
• An initial block starts at time 0, executes exactly once during a simulation and then does
not execute again. All initial blocks start executing concurrently at time 0.
• Each block finishes execution independent of other blocks.
• Multiple behavioral statements must be grouped using the keywords begin and end
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• Initial blocks are used for
executed only once during the simulation.
2.9 Always statement
• All behavioral statements inside an always statement constitute an always block.
• Starts at time ‘0’ and executes the statements in the always block continuously in a
looping fashion.
• Models a block of activity that is repeated continuously in a digital circuit.
Initial blocks are used for initialization, monitoring, waveform generation that
executed only once during the simulation.
All behavioral statements inside an always statement constitute an always block.
Starts at time ‘0’ and executes the statements in the always block continuously in a
Models a block of activity that is repeated continuously in a digital circuit.
, monitoring, waveform generation that must be
All behavioral statements inside an always statement constitute an always block.
Starts at time ‘0’ and executes the statements in the always block continuously in a
Models a block of activity that is repeated continuously in a digital circuit.
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CHAPTER 3 COMPONENTS OF ROUTER
In this noc router we have implemented Arbiter, Routing engine and lookup table, crossbar matrix
and FIFO buffer using Verilog HDL in Xilinx ISE Design Suite 14.1. Then simulation results of
both modules and combined modules are shown in next chapter.
3.1 ARBITER
Input arbiter controls the arbitration of the input ports or channels and resolves
connection problem. It keeps the updated status of all the ports and knows which port is
free and which port is communicating with each other. Arbiter also solves the problem of
multiple requests coming at single output port. We are using round robin arbitration algorithm in
our simulation. The round robin arbiter scheduled the packets with same priority and destined to
the same output. The round robin operates on the principle that an input channel requests
which was served has the lowest priority in the next round arbitration.
3.1.1 ROUND-ROBIN ARBITER DESIGN
A round-robin token passing bus or switch arbiter guarantees fairness (no starvation)
among masters and allows any unused time slot to be allocated to a master whose round-robin
turn is later but who is ready now. The worst-case wait time is proportional to number of
requestors minus one. The protocol of a round-robin token passing bus or switch arbiter works as
follows. In each cycle, one of the masters (in round-robin order) has the highest priority
(i.e., owns the token) for access to a shared resource. If the token-holding master does not need
the resource in this cycle, the master with the next highest priority who sends a request
can be granted the resource, and the highest priority master then passes the token to the next
master in round-robin order.
3.1.2 Bus Arbiter Design
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Fig. 2. Logic diagram of 4x4 bus arbiter block
It works on three process request, grant and Accept.
Step1- Request
Each unmatched input sends a request to every output which for which it has a queued cell.
Step2- Grant
In an unmatched output receives any requests, it chooses the one that appears next in a fixed,
round-robin schedule starting from the highest priority element. The output notifies each input
whether or not its request was granted. The pointer to the highest Priority element of the round-
robin schedule is incremented (modulo N) to one location Beyond the granted input if the grant is
accepted in Step 3 of the first iteration.
Step 3- Accept
If an unmatched input receives a grant, it accepts the one that appears next in a fixed, round-robin
schedule starting from the highest priority element.
3.1.3 Truth Table for 4x4 Priority Logic Block
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Consider a scenario with four processors as bus masters connected to the same bus with one large
shared memory on the bus as a slave. Suppose the token is 4 (token=4’b0100, which means
processor 2 has the token), and only processor 0 (which uses req[0]) and processor 1 (req[1]) want
to access the memory at this cycle. Token=4’b0100 leads to the enabling of only Priority Logic 2
in Fig. 1. In Priority Logic 2, the connection to in[0] (req[2] from processor 2) indicates the
highest priority. Since req[3] is connected to in[1] of Priority Logic 2 in Fig. 1, processor 3 has
the next highest priority. However, since neither processor 2 nor processor 3 make a request, in[2]
which is connected to req[0] is next in line in priority. Thus, processor 0 is granted access to the
memory, and then the memory controller of the accessed memory sends an ack signal, whose
connection to the BA, indicating when the memory transaction is successfully completed. Next,
which could be several processor clock cycles later, the token is passed to processor 3 (the 4-bit
ring counter is rotated when the ack signal is received) in which case the token is 4’b1000.
3.1.4 ASSUMPTION FOR ARBITER DESIGN
There are three independent requests say r1, r2, r3. In the project three inputs is given as in
detailed when the input is given through the r1, r2, r3 then after the processing it shows result in
form of g1, g2, g3.
It is assumed that the priority in the order r1>r2> r3. Highest priority among the input’s is r1, then
r2 and lowest priority is r3 . When the high priority work is given to the high priority input then
when request is sent to the high priority input then acknowledge is send immediately and process
on work start on the input. Duration of access time (Timeout period) is programmed through the
independent processor and the data bus. Duration of execution or responding the programme
access time (time out period) play important role for executing the input signals. If any signal is
given to the input according to the priority but arbiter does not respond in given time then whole
process repeat again in certain time period and same acknowledge is given by certain time and
grant signal generate in timeout period then process further start, otherwise further process
become stop and process of acknowledge and grant repeat again and again.
3.2 ROUTING ENGINE WITH LOOKUP TABLE
In proposed work the function of routing engine is received packets routing to the destination
output ports. It inspects the input data stream, an address from which a data packet is coming, and
determines a destination address and output port. Routing algorithm, this defines as the path taken
by a packet between the source and the destination. Here we use the XY routing algorithm. This
way we implemented X (source address) – y (destination address) algorithm of routing. A XY
routing algorithm mainly used in NOC because for its simplicity. Is the look-up table; containing
the parameter (rotation, translation, etc.) values for the movement of each joint. Here look-up
table provides a set of source-destination address data pairs. Routing engine “takes a look” into
the look-up table and matches source packet address to the destination one. For the purpose of a
practical design simulation, we decided for ATM protocol packets. ATM provides functionality
that is similar to both circuit switching and packet switching networks. ATM uses the
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asynchronous time-division multiplexing that encodes data into small and fixed size packets. In
Fig. ATM cell which consists of a 5-byte header and a 48-byte payload.
Fig 3 routing engine
3.3 Introduction to Crossbar Switch
In a network, a cross-bar switch is a device that is capable of channelling data between any two
devices that are attached to it up to its maximum number of ports. The paths set up between
devices can be fixed for some duration or changed when desired and each device-to-device path
(going through the switch) is usually fixed for some period. The crossbar provides a logical
connection between an input port and an output port. It consists of four horizontal buses (rows)
and four vertical buses (columns). A horizontal bus intersects a vertical bus at a crosspoint.
In NOC router the design of crossbar used 4-in-1 multiplexer array structure which enables each
input data channel to be connected to each output data channel. Crossbar-matrix is controlled by
two bit selected (sel) signals that are coming as process out from the routing engine. Crossbar –
based systems can be significantly less expensive than bus or ring systems with equivalent
performance because the crossbar allows multiple data transfers to take place simultaneously.
Input packets from input channel0 to input channel4 to each crossbar multiplexer. Thus every
crossbar multiplexer is having four packets as input. Output of every crossbar depends on bits
occurs on select lines of that particular crossbar multiplexer. The crossbar output lines are inputs
to output FIFO buffers.
Fig 4 cross bar switches
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The above diagram shows functionality of cross bar switch. Every input data channel is connected
with every data channel. The grant signals control the flow of input data through the cross bar
switch and hence decides which input channel is connected to which output channel at a particular
instant. In NOC router the crossbar switch decides the input to the FIFO buffers in similar fashion
FLOW CHART
3.4 Introduction to FIFO Buffer
Provides temporary storage of data.
Variable size as per requirement.
Used to transfer data between devices with different clocks.
Two pointers for read and write are used.
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Circular FIFO is required.
Size means number of variab
Two FIFO is used for input and output.
3.4.1 Working of Circular FIFO Buffer
RP: Read pointer
WP: Write Pointer
Fig 5
3.4.2 FlOW CHART
Circular FIFO is required.
Size means number of variables & depth means no of bits in one variable.
Two FIFO is used for input and output.
Working of Circular FIFO Buffer
Fig 5 circular fifo
les & depth means no of bits in one variable.
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4
Chapter 4 STAR TOPOLOGY IMPLEMENTATION OF NOC ROUTER 4.1 NOC TOPOLOGIES Network topology refers to the shape of the network. How the different nodes in a network are
connected to each other and how they communicate are determined by the network's
topology.
Mesh topology comes in two types. They are full mesh and partial mesh. Full mesh
means that a node is connected to every other node in the network; this is a very costly
method and mostly used to connect busses.
Partial mesh means that a node doesn’t have to be directly connected to all other nodes. This type
of mesh is not as costly as full mesh, but the disadvantage is less redundancy.
2D-array is a type of mesh in which nodes form a two dimensional grid where each node
is connected to the four adjacent routers. The routers at the edges have only two or three
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connections since they don’t have more adjacent routers. The number of nodes will then become
CxR where C is the number of columns and R is the number of rows.
Torus is a topology, which is similar to the 2D-array in which nodes form a regular cyclic 2-
dimensional grid. Here all routers have four connections since a torus basically is a mesh with
wrap-around on the edges.
Star topology uses a central hub to which all recourses are connected. All
communication between resources is then passed through the central hub.
Ring topology when the resources are connected to each other in a ring. Every resource is
then connected to its two neighbours communication with other resources then has to pass
through the neighbours.
Bus topology means that several resources use the samecommunication channel.
Octagon Topology is one of the type of ring topology. It consists of several eight paths
so it is called as octagon.
Binary Tree Topology(BFT) has a central root node that is connected to one or more
nodes of a lower hierarchy. In a symmetrical hierarchy, each node in the network has a
specific fixed number of nodes connected to those at a lower level. Scalable,
Programmable, Integrated Network (SPIN) architecture. This architecture implements the
topology similar to Butterfly Fat Tree Topology with some changes. In this topology router in
each level consists of same number of parent ports and child ports. This type of topological
structure provides higher throughput compared with Butterfly Fat Tree Topology.
In an ordinary local area network this can results in collisions, caused by two resources sending a
packet at the same time. If you want to avoid collisions it is a possible to let the resources send
their packet in a time slot, which is unique for each resource
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4.2 STAR TOPOLOGY
Star networks are one of the most common computer network topologies. In its simplest form, a
star network consists of one central switch or hub which acts as a conduit to transmit messages.
This consists of a central node, to which all other nodes are connected; this central node provides
a common connection point for all nodes through a hub. In star topology, every node (computer
workstation or any other peripheral) is connected to a central node called a hub or switch. The
switch is the server and the peripherals are the clients. Thus, the hub and leaf nodes, and the
transmission lines between them, form a graph with the topology of a star. If the central node
is passive, the originating node must be able to tolerate the reception of an echo of its own
transmission, delayed by the two-way transmission time (i.e. to and from the central node) plus
any delay generated in the central node. An active star network has an active central node that
usually has the means to prevent echo-related problems.
ADVANTAGES
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Better performance: Star topology prevents the passing of data packets through an
excessive number of nodes. At most, 3 devices and 2 links are involved in any
communication between any two devices.
Isolation of devices: Each device is inherently isolated by the link that connects it to the
hub. This makes the isolation of individual devices straightforward and amounts to
disconnecting each device from the others. This isolation also prevents any non-
centralized failure from affecting the network.
Benefits from centralization: As the central hub is the bottleneck, increasing its capacity,
or connecting additional devices to it, increases the size of the network very easily.
Centralization also allows the inspection of traffic through the network. This
facilitates analysis of the traffic and detection of suspicious behavior.
Easy to detect faults and to remove parts.
No disruptions to the network when connecting or removing devices.
Installation and configuration is easy since every one device only requires a link and one
input/output port to connect it to any other device(s).
DISADVANTAGES Reliance on central device: star topology relies on the central device (the switch, hub or
computer). This device is a single point of failure -- if this device fails, the whole network will
fail in turn.
Higher costs: the need for a central device increases costs compared to the bus and ring
topologies. The star topology also requires more cable when using Ethernet cables than ring and
bus topologies.
Limited capacity for nodes: as this type of network needs all connections to go through a central
device the amount of nodes in a network is limited by this factor whereas bus and ring topologies
are not limited in such a way
4.3 DATA FLOW IN STAR TOPOLOGY In our project we have implemented star topology with 4 routers. All the 4 Routers are connected to the hub, which is responsible for creating connections between routers depending upon the source and destination address. Each router have 4 inputs and 4 outputs. The inputs are from any processing device which is adjacent to the transmitting router and the output of destination router will going to be the input for processing device which is adjacent to the destination router. As we are having 4 routers so the address requires only 2 bits.
ROUTER ADDRESS
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R1 00 R2 01 R3 10 R4 11
HUB establishes the connection depending upon the source and destination address. Suppose in address field we have 0010 this means the source router is router R1 and destination Router is R3. Now we have to swap the outputs which means outputs of router R1 will appear on the output of router R3.
Fig 7 data flow in star topology
CHAPTER 5. RESULTS AND SIMULATION
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5.1 INPUT ARBITER Input to the arbiter are four request signals, clock and reset. Output of the module are four grant signals according to the priority of inputs. 5.1.1 SCHEMATIC DIAGRAM To see schematic diagram
1. Click on implementation tab. 2. Synthesis the module. 3. Click on view RTL schematic option. 4. Choose the module for which schematic is required.
5.1.2 SIMULATION
To see simulation results
1. Click on simulation tab. 2. Select the test bench code for the module. 3. Click on behavioral syntax check. 4. Click on simulate behavioral model.
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5.1.3 DESIGN SUMMARY
To check design summary for components utilize 1. Under implementation tab click on synthesize –XST
2. Double click on design summary/report.
5.2 ROUTING ENGINE AND LOOKUP TABLE 5.2.1 SCHEMATIC DIAGRAM
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5.2.2 SIMULATION
5.2.3 DESIGN SUMMARY
5.3 CROSSBAR MATRIX Input to this module are in1,in2,in3,in4 each of 8 bit. Four grant signals gnt1,gnt2,gnt3,gnt4 each of one bit are taken. Output is decided on the basis of grant signals. If value of first grant signal is high then first input in1 will be transferred to all the four outputs and so on for every grant signal.
5.3.1SCHEMATIC DIAGRAM
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5.3.2SIMULATION
5.3.3 DESIGN SUMMARY
5.4 FIFO BUFFER
input to the module are data_in of 8 bit for input data, clk for syncronisation, e (enable) of 1 bit to
enable the fifo,read signal of 1 bit for read operation, write signal of 1 bit for write operation and
reset signal of 1 bit to make buffer reset.
Outputs are data_out of 8 bit to pop the value from the buffer
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5.4.1SCHEMATIC DIAGRAM
5.4.2 SIMULATION
5.4.3 DESIGN SUMMARY
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5.5 COMBINED MODULE for ROUTER Inputs of this module are in1,in2,in3,in4, Clk,Reset,Write and Read.
Outputs are data_out0,data_out1,data_out2,data_out3.
5.5.1 SCHEMATIC DIAGRAM
5.5.2 SIMULATION RESULT
5.5.3.DESIGN SUMMARY
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5.6Module for Star Topology
5.6.1SCEMATIC DIAGRAM
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5.6.2 SIMULATION RESULT
For inputs
For control signals
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For outputs
5.6.3 DESIGN SUMMARY
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APPENDIX 1
VERILOG CODE FOR INPUT ARBITER
module arbitter(req0,req1,req2,req3,gnt0,gnt1,gnt2,gnt3,rst,clk); input wire [0:7]req0,req1,req2,req3; input rst,clk; output gnt0,gnt1,gnt2,gnt3; reg gnt0=0; reg gnt1=0; reg gnt2=0; reg gnt3=0; reg temp0=0; reg temp1=0; reg temp2=0; reg temp3=0; always@(posedge clk) begin if(rst) begin gnt0=0; gnt1=0; gnt2=0; gnt3=0; end else begin gnt0=temp0; gnt1=temp1; gnt2=temp2; gnt3=temp3; end end always@(req0,req1,req2,req3) begin if (!req0 && !req1 && !req2 && !req3)begin temp0=0; temp1=0; temp2=0; temp3=0; end else if (!req0 && !req1 && !req2 && req3) begin temp0=0; temp1=0;
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temp2=0; temp3=1; end else if (!req0 && !req1 && req2 && (!req3 || req3)) begin temp0=0; temp1=0; temp2=1; temp3=0; end else if (!req0 && req1 && (!req2 || req2) && (req3 || !req3)) begin temp0=0; temp1=1; temp2=0; temp3=0; end else if (req0 && (!req1 || req1) && (!req2 || req2) && (req3||!req3)) begin temp0=1; temp1=0; temp2=0; temp3=0; end else begin temp0=0; temp1=0; temp2=0; temp3=0; end end endmodule
E1<=one; E2<=zero; E3<=zero; E4<=zero; end else if (x==1) begin E1<=zero; E2<=one; E3<=zero; E4<=zero; end else if (y==1) begin E1<=zero; E2<=zero; E3<=one; E4<=zero; end else if (z==1) begin E1<=zero; E2<=zero; E3<=zero; E4<=one; end else begin E1<=zero; E2<=zero; E3<=zero; E4<=zero; end end endmodule
reg [0:7]dat2=8'b00000000; reg [0:7]dat3=8'b00000000; reg [0:7]dat4=8'b00000000; always @(gnt1 or gnt2 or gnt3 or gnt4 or In1 or In2 or In3 or In4) begin case({gnt1,gnt2,gnt3,gnt4}) 4'b1000:begin dat1<=In1; dat2<=In1; dat3<=In1; dat4<=In1; end 4'b0100:begin dat1<=In2; dat2<=In2; dat3<=In2; dat4<=In2; end 4'b0010:begin dat1<=In3; dat2<=In3; dat3<=In3; dat4<=In3; end 4'b0001:begin dat1<=In4; dat2<=In4; dat3<=In4; dat4<=In4; end default:begin dat1<=8'b00000000; dat2<=8'b00000000; dat3<=8'b00000000; dat4<=8'b00000000; end endcase end endmodule
[1] Arivu P, Shanmugasundaram N, Kamalanathan C, Dr.S.Valarmathi ,Master of Engineering Student - BIT,Sathyamangalam. Associate Professor-BIT,Sathyamangalam. Professor-BIT,Sathyamangalam. “Design of Synchronous NoC Router for System-on-Chip Communication and Implement in FPGA using VHDL” . [2] Marko R. Ili , Vladimir Z. Petrovi and Goran S. Jovanovi “Simulation of synchronous Network-onchip router for System-on-chip communication” 20th Telecommunications forum TELFOR 2012 [3] Anuprita.S. Kale, Prof. M.A.Gaikwad “Design and Analysis of On-Chip Router for Network on Chip” [4] http://eewiki.net/pages/viewpage.action?pageld=20939499 [5]http://www.design-reuse.com/articles/10496/a-comparision-of-network-on-chip-and-busses.html