Tri-gate technology
Tri-gate technology
CHAPTER 1INTRODUCTION
Performance and productivity of microelectronics have increased
continuously over more than four decades due to the enormous
advances in lithography and device technology. Since in the late
1950s, planar transistors have acted as the basic building block of
microprocessors. The scaling of planar transistors requires the
scaling of gate oxides and source/drain junctions. However, as
these transistor elements become harder to scale, so does the
transistor gate length. The scaling of planar transistors is
getting more difficult due to the worsening electrostatics and
short-channel performance with reducing gate-length dimension. In a
multigate device, the channel is surrounded by several gates on
multiple surfaces, allowing more effective suppression of
"off-state" leakage current. Multiple gates also allow enhanced
current in the "on" state, also known as drive current. These
advantages translate to lower power consumption and enhanced device
performance. Non-planar devices are also more compact than
conventional planar transistors, enabling higher transistor density
which translates to smaller overall microelectronics.A new
technology that can significantly improve the electrostatics and
short-channel performance is the Tri-gate technology which is used
in the manufacture of tri-get transistors, as shown in the below
figure This transistor, which can be fabricated either on the SOI
substrate or standard bulk-silicon substrate, has a gate electrode
on the top and two gate electrodes on the sides of the silicon
body. The top-gate transistor has physical gate length LG and
physical gate width WSi, while the side-gate transistor has
physical gate length LG and physical gate width HSi, as shown in
Figure-1.
Figure 1: Tri-Gate Transistor
Due to this Tri-gate technology the number of transistors that
can be fabricated on a single chip is doubled when it is compared
to the old 2D planar technology, which satisfies the Moores law.1.1
MOORES LAW The number of transistors and resistors on a chip
doubles every 18 months. This was said by Intel co-founder Gordon
Moore regarding the pace of semiconductor technology. He made this
famous comment in 1965 when there were approximately 60 devices on
a chip. Proving Moore's law to be rather accurate, four decades
later, Intel placed 1.7 billion transistors on its Itanium chip. In
1975, Moore extended the 18 months to 24 months. More recently, he
said that the cost of a semiconductor manufacturing plant doubles
with each generation of microprocessor. CHAPTER 2LITERATURE SURVEY
High Performance Fully-Depleted Tri-Gate CMOS Transistors
B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J.
Kavalieros, T. Linton, Member, IEEE, A. Murthy,R. Rios, Member,
IEEE, and R. Chau, Senior Member, IEEE
FD tri-gate CMOS transistors with gate lengths of 60 nm have
been fabricated and compared to well-optimized bulk CMOS
transistors at these dimensions.
Intel Ivy Bridge Unveiled The First Commercial Tri-Gate, High-k,
Metal-Gate CPU
Dick James Chip works, 3685 Richmond Road, Ottawa, Ontario,
Canada K2H 5B7 978-1-4673-1556-2/12/$31.00@2012 IEEEIntels 22-nm
tri-gate Ivy Bridge processor chip is the first example of a
finFET/tri-gate part in high-volume commercial production, and
shows many innovations in its device structure. The Potential and
Realization of Multi-layers Three-Dimensional Integrated
CircuitHong Kong University of Science & Technology, Clear
Water Bay, Kowloon, Hong Kong
0-7803-6520-8/01/$10.00 (F3 2001 IEEE).
3D IC technology with transistors stacked on top of one another
in multiple silicon layers has always been a vision in the future
technology direction to provide a breakthrough towards higher
circuit density and functionality. While the idea is simple, the
technique to obtain high performance multi-layer transistors is
extraordinarily difficult. Advanced Depleted-Substrate Transistors:
Single-gate, Double-gate and Tri-gateRobert Chau, Brian Doyle, Jack
Kavalieros, Doug Barlage, Anand Murthy, Mark Doczy,
Reza Arghavani and Suman Datta,member, IEEE
All the three fully-depleted SOI transistor structures were
discussed and Of the three, the tri-gate depleted substrate
transistor has the least stringent silicon thickness and silicon
width requirements.
Integrated CMOS Tri-Gate Transistors: Paving the Way to Future
Technology Generations
Robert S. Chau, Doug Barlage, Anand Murthy, Mark Doczy, senior
member, IEEEAs transistors get smaller, parasitic leakage currents
and power dissipation has become significant issues. By integrating
the novel three-dimensional design of the tri-gate transistor with
advanced semiconductor technology such as strain engineering and
high-k/metal gate stack, Intel has developed an innovative approach
toward addressing the current leakage problem while continuing to
improve device performance.
CHAPTER 3TRI-GATE TECHNOLOGYTri-gate technology is one of the
major innovations made in the field of microprocessors. Tri-Gate
isn't a wholly new announcement - it was first mooted as a
technology by Intel in 2002. But it remains that three-dimensional
transistors represent a fundamental departure from the
two-dimensional planar transistor structure that has powered all
computers, mobile phones, and car tech and consumer electronics to
date. Intel is now clearly stoked about the news. "Intel's
scientists and engineers have once again reinvented the transistor,
this time utilizing, the third dimension," said by Intels President
and CEO Paul Otellini.
3.1 Introduction to Tri-GateFirst invented by Intel research
scientists in 2002, Tri-Gate is a new way of manufacturing
transistors that the corporation will introduce with its move to
22nm logic technology late in 2011. And, what's more, they bring a
whole new dimension to proceedings; the three-dimensional Tri-Gate
transistors represent a fundamental departure from the
two-dimensional planar transistor structure that has powered all
consumer electronics devices to date. The Tri-Gate transistor is so
named as the gate has three sides. The traditional 'flat'
two-dimensional planar gate is replaced with an incredibly thin
three-dimensional silicon fin that rises up vertically from the
silicon substrate. Control of current is accomplished by
implementing a gate on each of the three sides of the fin two on
each side and one across the top - rather than just one on top, as
is the case with the 2D planar transistor. And since these fins are
vertical, transistors can be packed closer together.
The new Tri-Gate transistors enable chips to operate at lower
voltage with lower leakage, broadly meaning improved performance
and energy efficiency compared to previous state-of-the-art
transistors. The capabilities give chip designers the flexibility
to choose transistors targeted for low power or high performance,
depending on what they're needed for - Intel is talking about a 37
percent performance increase at low voltage versus Intel's 32nm
planar transistors.
Figure 3.1(a): 32nm 2D planar transistor fabricated on a
chip.
Figure 3.1(b): 22nm Tri-Gate transistors fabricated on a
chip.Figure 3.1(a) shows how the 32 nm 2D planar transistors that
we've been using for half a century. This shows 32nm transistors
with the source, drain and channel (the latter covered by the gate)
all in the same plane. The number of 32 nm transistors that can be
incorporated on a chip is less when it s compared to the 22nm
transistors. Figure 3.1(b) shows the vertical fins of Intel's
revolutionary tri-gate transistors passing through the gates.Why is
Tri-Gate needed?Without the new transistors, it would have been
difficult for Intel to continue to uphold Moore's Law. This is the
1965 theory by Intel co-founder Gordon Moore that the number of
transistors in a given area would double every two years, with
increased functionality and reduced cost. Intel says its scientists
have long recognized the benefits of a 3D structure for sustaining
the pace of Moore's Law as device dimensions become so small that
physical laws become barriers to advancement as process technology
has got smaller, problems such as current leakage have needed to be
dealt with.
"For years we have seen limits to how small transistors can
get," said Moore of Intel's latest innovation. "This change in the
basic structure is a truly revolutionary approach, and one that
should allow Moore's Law, and the historic pace of innovation, to
continue."
Figure 3.1(c): 2D planar and a tri-gate transistorIn figure
3.1(c) the transistor on the left side is the 32nm planar
transistor in which the current (represented by the yellow dots)
flows in a plane underneath the gate. On the right is the 22nm 3D
Tri-Gate transistor with current flowing on three sides of a
vertical fin.When will Tri-Gate transistors be announced?We'll
start to see 22nm processors appear later in the year and the
process will supecede the current Sandy Bridge processors in due
course. This keeps on track Intel's plan to introduce a completely
new processor generation every two years. Intel has already
demonstrated a 22nm chip codenamed Ivy Bridge the corporation has
also said they will continue to use the Intel Core branding for
desktop and laptop chips as well as Atom for handhelds and other
mobile devices.
Tri-Gate replaces the High-k Metal Gate transistors announced
alongside the move to 45nm in 2007. Each 22nm processor will have
somewhere in the region of 2.9 billion transistors on board. More
than 6 million 22nm Tri-Gate transistors could fit into the space
taken up by the full stop at the end of this sentence.
What devices will 22nm are used in?
As well as servers, desktops and laptops, Intel says 22nm is
poised to take a hold in the mobile device market. "The low-voltage
and low-power benefits far exceed what we typically see from one
process generation to the next," says Intel Senior Fellow Mark
Bohr. "It will give product designers the flexibility to make
current devices smarter and wholly new ones possible. We believe
this breakthrough will extend Intel's lead even further over the
rest of the semiconductor industry."Great for mobile technologyThat
means the 22nm processors will be ideal for use in small handheld
devices, which operate using less energy to "switch" back and
forth. Alternatively, the new transistors consume less than half
the power when at the same performance as 2D planar transistors on
32nm chips. The performance gains and power savings of Intel's
unique 3-D Tri-Gate transistors are like nothing we've seen before,
continues Mark Bohr.
"This milestone is going further than simply keeping up with
Moore's Law. The low-voltage and low-power benefits far exceed what
we typically see from one process generation to the next. It will
give product designers the flexibility to make current devices
smarter and wholly new ones possible. We believe this breakthrough
will extend Intel's lead even further over the rest of the
semiconductor industry.Will the new 22nm processors cost more?In
its documentation Intel says the new manufacturing process costs
around 2-3 per cent more, but we wouldn't expect this to mean
anything by the time it gets inside your next PC, Mac or
tablet.
CHAPTER 4WORKING OF TRANSISTORSTransistors are the building
blocks of microprocessors, which are the 'brains' or computational
devices inside PCs, laptops; Smartphones and pretty much all modern
electronic devices. A transistor is essentially an automated switch
that can store information as either a '1' or a '0', depending on
whether the switch is on letting electric current through or off.
The wiring of several transistors together creates a device called
a logic gate, which takes these ones and zeros and performs basic
calculations with them. Home computers available today contain
billions of transistors wired into logic gates, and have huge
processing power as a result.
4.1 PLANAR TRANSISTOR
Figure 4.1(a): Planar Transistor
The simplest type of transistor is a planar device, called 2D
because it is flat. Flat is somewhat of a misnomer as shown in
Figure-4.1(a). The gate stack does come up from the silicon
substrate. The source and drain collectively called the channel are
where the electrons flow from and to. This channel is on the
surface of the wafer, with the silicon itself connecting them, all
of which is 2D.
From there, there is a block called the gate on top of the
channel, in green on the diagram above. The gate oxide, in yellow,
prevents current flowing from the gate in to the current path
itself. Theoretically, when you switch the transistor on, the
electric field from the current in the gate extends down in to the
silicon substrate. This modifies the electrical characteristics of
the inversion layer allowing electrons to pass through as shown in
figure 4.1(b).
One of the most common modifiers to the transistor is called
PD-SOI or Partially Depleted Silicon over Insulator. This attacks
leakage, the phenomenon where current moves from the source to the
drain when the transistor is off. Leakage is wasted energy, a very
bad thing that is getting worse as transistors shrink. One way to
combat leakage is to put a layer of oxide under the surface of the
silicon to stop current from flowing below the gate, which explains
the name quite nicely.
PD-SOI works well to a point, but the cost is not worth the
benefit according to Intel. AMD has been using PD-SOI for several
years, so they have a different view of the cost/benefit tradeoff.
In any case, the benefits of SOI are largely a factor of the ratio
between the source/drain channel and the depth of the oxide layer.
As geometries are reduced, and structures shrink, the ratio needed
means the layer needs to get closer and closer to the surface. Most
companies are not using SOI below the 32nm node because of this
phenomenon.
This leads to a new type of SOI called FD-SOI, or Fully Depleted
SOI. In FD-SOI, the oxide layer is almost on the surface of the
wafer, and all of the structures are basically built on that. One
rule of thumb here is that the silicon body has to be thinner than
the channel length, something currently measured in nm. Several
companies have discussed making FD-SOI chips, but none have
publicly committed to production. Cost and complexity are the two
commonly discussed concerns, things that may or may not change
before any FD-SOI chips come off the line in volume.
Figure 4.1(b): 2D planar transistor
4.2 FIN-FIELD EFFECT TRANSISTORS
Figure 4.2: Fin Field Effect TransistorIf you take a 2D
transistor and flip it 90 degrees up, and then put another gate on
the other side, you have a FINFet as shown in figure 4.2. The fin
is the source/drain channel, and you can make it as thin or as
thick as you want. Instead of being the same thickness as the
wafer, it is just another structure of the chip that you build up
or etch down.FINFets effectively have two coupled gates on either
side of the channel, and a controllable channel thickness. The
contact area between the gate and the channel is effectively 2x the
size of a planar part; the channel is constrained on two sides, not
one. This allows the electric field from the gates to penetrate the
channel much more quickly and comprehensively.The speed and
completeness of the field penetration through the body controls the
speed of the transistor and the ramp of the on/off curve, more
penetration means more performance.FINFets allow much more room for
tradeoffs in power and performance. This new knob for the chip
designer to turn means more control over some previously static
parameters. More importantly, there is a huge reduction in area
between the channel and the silicon substrate. If you recall, a lot
of leakage is a result of current flowing under the gate, so if you
reduce the gate to channel contact area, you reduce leakage a
lot.
The biggest problem with FINFets is not conceptual, it is
physical. How do you make them? Instead of laying down layers of
materials or implanting ions on the surface of a flat wafer, you
have to make a set of extremely thick but narrow high aspect ratio
structures. Instead of painting on a canvas, FINFets force you to
stack bits of colored atoms on edge to achieve the same picture.The
problems are immense and most of them involve how to make high
aspect ratio structure with effectively flat, right angle walls.
Since the performance of the transistor is related to the thickness
of the fin, any variance in widths, typically the top thinner than
the bottom, means inconsistent performance and a host of other
problems. Making correct and consistent structures by the billions
is extremely complex work.4.3 TRI-GATE TRANSISTOR
Figure 4.3 (a)
Figure 4.3 (b)Confining the channel on two sides with FINFets is
good, but wouldnt three sides be better? If you look at the FINFet
pictured above, you will see a cap on top of the fin meaning no
gate contact on the third side. With their 22nm process, Intel
added gate contact on the third side, instead of a cap they put
more gates on top as shown in figure 4.3(a). This increases
manufacturing complexity a bit, but it also constrains the channel
on a third side, leading to the tri- in Tri-Gate.
According to Intel, Tri-Gate performs better than FINFets in a
few cases, and no worse in all cases shown figure 4.3(b). It is
another tradeoff, and one Intel seems to think is well worth the
cost for their 22nm process. The end result is a claimed 37%
performance increase at low voltages or 50%+ lower power use at the
same performance. These macro level gains are the result of the
reduced leakage, faster switching, three sided confinement, and
increased drive strength inherent in the vertical 3D fin
structures.
One interesting thing about FINFets and Tri-Gate transistors is
the area reduction, and ability to parallelize transistors for
increased drive strength. Instead of tuning the transistor by
varying thicknesses of layers, a designer can simply put a second
channel beside the first. Or a third beside that, and as many more
as you want to draw if you need to do silly things like ESD
protection on I/O circuitry.
The end result is that some of the tuning available to Tri-Gate
transistors is now quantized. Instead of tuning an analog radio,
you have a knob with specific stops. You can still tune the
vertical fins in some of the same ways as planar, but that route is
much harder than before. The net result is a few different tuning
parameters than before, but things are still quite tunable. Think
about there being some new knobs, some old knobs, some missing
knobs, and some different knobs, but there are still knobs.
One more added advantage in case of Tri-Gate is, it can have
multiple fins connected together as shown in figure 4.3(c) to
increase total drive strength for higher performance.
Figure 4.3(c): Tri-Gate transistor with multiple fins4.4
Analysis of Tri-Gate TechnologyDifference between 2D and a 3D
transistorTransistors are usually made from silicon, which is a
semiconductor a material that can behave as both an electrical
conductor and an insulator. They consist of a straight channel
connecting a source to a drain, interrupted half way by a wide
gate. The gate is what makes the transistor a switch: apply the
right voltage and a conductive pathway known as an inversion layer
forms, allowing current to flow from the source to the drain. In
this instance, the transistor is on; without the inversion layer,
no current flows and the transistor is off.
All transistors mass-produced during the past 50 years or so
have been 2D. This means that the source, the drain and the channel
connecting them all lie flat on the same plane. In Intel's 3D
transistors, on the other hand, the channel protrudes from the
surface in a ridge or 'fin'. The result is that it has not one, but
three sides in contact with the overlapping gate thus its name
'Tri-Gate'
Why is the 3D design better?Chip manufacturers such as Intel
have been progressively shrinking transistors in order to pack more
onto each chip and, ultimately, make faster computers. At present,
the fastest chips use transistors that are about 32 nanometers in
diameter that's on the order of about 100 silicon atoms and
manufacturers will soon be producing 22-nanometre versions. But
this continued miniaturization has an attendant problem: as the
transistor's source and drain get closer together, and as the
channel gets smaller, it becomes harder for the gate to control the
formation of the inversion layer. Simply put, the distinction
between 'off' and 'on' becomes fuzzier.
Having a 3D structure solves this problem. Because it is in
contact with three sides of the channel, the gate has much greater
control over the inversion layer. This means that the on and off
states are more distinct even when the transistor is shrunk.
What is the benefit for computing?Intel will be incorporating
Tri-Gate structures into its next generation of 22-nanometre
transistors, slated to be production ready by the end of this year.
The company says that, compared with its current 32-nanometre, 2D
transistors, Tri-Gate transistors will be up to 37% faster. In
general, the 3D design should allow transistors to be packed more
closely to one another, and so make it possible to fit more into
the same space.
There are subtle advantages, too. According to Intel, the
structures leak less current than standard 2D ones when not in use,
which will improve the battery life of portable electronic devices
such as laptops and Smartphones. Moreover, when they are run at
relatively low voltages, they should consume less than 50% of the
power required by Intel's current transistors which will be a boon
for heavy-duty network servers.
Did Intel invent the 3D transistor?The concept of 3D transistors
has been around for well over a decade the difficulty has been how
to engineer one that can successfully be mass-produced. Because
transistors now comprise just a few dozen atoms, even minor defects
can have a huge effect on performance. Having features protrude
from the substrate is particularly tricky, and Intel has not
disclosed how its engineers have tackled this.
The Tri-Gate design is essentially a variant of a 'FinFET' 3D
structure developed in the late 1990s by Chenming Hu and his
colleagues at the University of California, Berkeley. Other chip
manufacturers such as IBM, Samsung and TSMC are all working on 3D
designs, but are not expected to put them into production until at
least the next generation of miniaturization, after 22
nanometers.
What will follow 3D?Intel thinks the Tri-Gate structure should
scale down to transistors of 14 nanometers and smaller. In
principle, it should be possible to make transistors, 3D or
otherwise, of just a few atoms, although manufacturing consistency
becomes ever more difficult as size diminishes.
At some point, manufacturers will be forced to explore yet more
dimensions. Perhaps at that stage the answer will be spintronics an
emerging technology that makes use of an electron's spin, as well
as its charge.4.5 Advantages of Tri-gate Dramatic performance gain
at low operating voltage , better than Bulk, PDSOI,FDSOI Intel says
there's a "dramatic performance gain at low operating voltage"
thanks to far reduced current leakage. Indeed this translates to a
37 per cent performance increase at low voltage versus Intel's 32nm
planar transistors and under a 50 per cent power reduction with
constant performance.
Improved switching characteristics Higher drive current for a
given transistor Only 2 3% cost adder Tri-Gate can have multiple
fins connected together to increase total drive strength for higher
performance. Figure 1.
Figure 2.Figure 1: 22 nm 3-D Tri-Gate transistors can operate at
lower voltage with good performance, reducing active power by
>50%.
Figure 2:22 nm 3-D Tri-Gate transistors provide improved
performance at high voltage and an unprecedented performance gain
at low voltage.
Figure 3.
Figure 4. Figure 5.
Figure 6. Figure 3: The fully depleted characteristics of
Tri-Gate transistors provide a steeper sub-threshold slope that
reduces leakage current.
Figure 4: The steeper sub-threshold slope can also be used to
target a lower threshold voltage, allowing transistors to operate
at lower voltage to reduce power and/or improve switching
speed.
Figure 5: Comparison with different node transistors.
Figure 6: 22 nm Tri-Gate transistors increase the benefit from a
new technology generation.
CHAPTER 5FUTURE SCOPE
As we know that 22 nm tri-gate transistors are soon to hit the
market with its high performance capability Intel is already set to
release there next transistors by the mid of 2013. Intel has taken
the next generation manufacturing process that would be 14 nm, from
the drawing board to the test lab It is not just the shrinking of
the manufacturing process that drives the strategy but also the
introduction of new solutions in the transistor design. Intel's
Tri-Gate transistors will be introduced with the 22 nm Ivy Bridge,
but will see further improvement in the next-generation 14 nm
process. The Intels technology road map is as shown in the below
figure.Will it be the end of Processor era???
Surely not!!!!!! Because a new material is all set to replace
semiconductors.
CHAPTER 6CONCLUSION
We have discussed in detail that how tri-gate technology is
better than the other transistor manufacturing technologies. And we
have also seen that Moores law stated by Gordon Moore will not see
the end as the number of transistors that can be fabricated on a
chip is getting increased by the decrease in size of the
transistors. As we all know that the user requires more faster and
high performance processors with low cost, to be fabricated on
their PCs, laptops, smart phones etc. which could make their device
more efficient and smarter. This requirement of the user can be
served with the tri-gate technology as it is the faster, efficient
and better transistor manufacturing technology ever
invented.REFERENCES[1]
http://www.techradar.com/news/computing-components/processors/intels-tri-gate-transistors-
everything-you-need-to-know-952572.[2]
http://semiaccurate.com/2011/08/18/intel-moves-transistors-from-2d-to-3d-and-more/#.
USt1BYbULVc.[3]
http://newsroom.intel.com/community/intel_newsroom/blog/2011/05/04/intel-reinvents-
Transistors-using-new-3-d-structure.[4] B. S. Doyle, S. Datta,
M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, Member,
IEEE, A. Murthy,R. Rios, Member, IEEE, and R. Chau, Senior Member,
IEEE, High Performance Fully- Depleted Tri-Gate CMOS Transistors,
EEE Electron Device Letters, vol. 24, no. 4, April 2003.
[5] M. Specht, R. Kmmling, F. Hofmann, V. Klandzievski, L.
Dreeskornfeld, W. Weber, J. Kretz, E. Landgraf, T. Schulz, J.
Hartwich, W. Rsner, M. Stdele, R. J. Luyken, H. Reisinger, A.
Graham, E. Hartmann, and L. Risch, Novel Dual Bit Tri-Gate Charge
Trapping Memory Devices, IEEE Electron Device Letters, vol. 25, no.
12, April 2004.[6] Jinping Zhang, Bo Zhang, Zhaoji Li, Improved
Performance of 3D tri-gate 4H-SiC ESFETs With Recessed Drift
Region, IEEE, 978-1-4244-2186-2, 2008.
[7] Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih
Hamzaoglu, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark
Bohr, A 4.6GHz 162Mb SRAM Design in 22nm Tri- Gate CMOS Technology
with Integrated Active VMIN-Enhancing Assist ircuitry, IEEE
International Solid-State Circuits Conference, 2012[8] Dick James,
Intel Ivy Bridge Unveiled The First Commercial Tri-Gate, High-k,
Metal-Gate CPU, 978-1-4673-1556-2,IEEE, 2012.[9] Chun-Hsien Chiang,
Ming-Long Fan, Jack Jyun-Yan Kuo, and Pin Su, Body Effect, induced
Variability in Bulk Tri-gate MOSFETs, IEEE, 978-1-4577-2084-0/.
2012.Dept. of ECE, SET, Jain University
Page 1