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APPLICATION NOTE
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Renesas Synergy™ Project Low-Power Modes and Mode Transitions on
the DK-S124
Introduction This document describes different low power modes
and mode transitions of the Renesas Synergy MCU S124 with Synergy
Software Package (SSP) and DK-S124 board. The attached application
code allows users to set the MCU S124 into different power
controlling modes, such as High-Speed Mode, Middle-Speed Mode,
Low-Speed Mode, and different low power modes, such as Sleep Mode,
and Software Standby Mode. The basic test environment is: DK-S124
(v2.0), and the Renesas Synergy™ Software Package SSP (v1.1.0) and
the Synergy™ e2 studio™ (v5.0.0.0.43).
Target Device DK-S124 Kit (Version 2)
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Contents
1. Overview
.........................................................................................................................
3
2. Power Modes of Synergy MCU S124
.............................................................................
3 2.1 Five Power Control Modes
.........................................................................................................
3
2.1.1 High-Speed Mode:
................................................................................................................
3 2.1.2 Middle-Speed Mode
..............................................................................................................
4 2.1.3 Low-Voltage Mode
................................................................................................................
4 2.1.4 Low-Speed
Mode...................................................................................................................
5 2.1.5 Subosc-Speed Mode
.............................................................................................................
5 2.1.6 Transition between Power Control Modes
.........................................................................
5
2.2 Three Low Power Modes
............................................................................................................
5 2.2.1 Sleep Mode
............................................................................................................................
8 2.2.2 Software Standby Mode
.......................................................................................................
8 2.2.3 Snooze Mode
.........................................................................................................................
8 2.2.4 Transitions between the Low Power Modes
......................................................................
8
2.3 Power Consumption for Different Power Control Modes and Low
Power modes ............... 8 2.3.1 Standby Current of the
Normal/Sleep Mode under the High-Speed Mode ..................... 9
2.3.2 Standby Current of the Normal/Sleep Mode under the
Middle/Low-Speed Modes ........ 9 2.3.3 Standby Current of the
Normal/Sleep Mode under the Low-Voltage/Subosc-Speed
Modes
...................................................................................................................................
10 2.3.4 Standby Current of the Normal/Software Standby Mode
............................................... 10
3. Project: Making Low Power Mode Transitions with DK-S124
................................... 10 3.1 Hardware: Renesas
DK-S124 Kit
.............................................................................................
11 3.2 Project Design: Algorithms
......................................................................................................
11 3.3 Project Design: User Interface
.................................................................................................
13
3.3.1 Potentiometer to select power controlling modes in FSM1
........................................... 14 3.3.2 LED2 and LED3
indicating states of FSM1
.......................................................................
14 3.3.3 Button S1 to initiate low-power mode transition in FSM2
.............................................. 14 3.3.4 LED1 for
showing CPU status: normal or sleep
..............................................................
14
4. Project Implementation: e2 studio and SSP
................................................................ 15
4.1 Synergy e² studio
......................................................................................................................
15 4.2 Synergy Software Package (SSP)
...........................................................................................
15 4.3 Configuration panels of SSP in e2 studio
...............................................................................
15 4.4 Default Clock Frequency Setup
...............................................................................................
16 4.5 Reading the Potentiometer with the SSP ADC Driver
........................................................... 17 4.6
Waking up from Software Standby Mode with the SSP RTC Driver
.................................... 19
5. Test and Observation
...................................................................................................
22
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1. Overview Reducing MCU power consumption has become a critical
challenge for IOT applications, especially wearable devices. To
provide different power controlling capabilities, an ARM®
Cortex®-M0+ based Synergy S124 MCU has five operation power control
modes with different operating frequencies and voltages, such as
High-Speed, Middle-Speed, and Low-Speed Modes and also 3 different
low power modes: Sleep, Software Standby, and Snooze modes. This
application note describes basic features of those modes and
transitions between modes triggered by a switch button and a
potentiometer on DK-S124 (v2) board.
• SW/HW Versions used in this document: • Renesas SW/HW: DK-S124
(Version 2), e2 studio (5.0.0.043), and Synergy SSP (V1.1.0)
• Minimum workstation requirements: • Microsoft® Windows® 7 with
Intel® Core™ family processor running at 2.0 GHz or higher (or
equivalent
processor), 8-GB memory, 250-GB hard disk or SSD, USB 2.0,
Internet connection
2. Power Modes of Synergy MCU S124 The S124 provides two sets of
power modes for supporting different power or performance
requirements, Power Controlling Modes and Low Power Modes. This
session will present basic concepts and usages, especially with SSP
low-power, low-level HAL framework API. More detailed descriptions
can be found in the S124 User’s Manual for the configuration of the
control registers, and the SSP User’s Manual for APIs.
2.1 Five Power Control Modes When executing a program in the
Normal mode, the MCU power consumption is mainly affected by the
clock configuration and peripheral module configurations. The S124
MCU allows you to adjust System Clock (ICLK), Peripheral Module
Clocks (PCLKB, PCLKD), External Bus Clock (BCLK), and to stop
peripheral modules by setting different control registers.
As the table shown below, the S124 has five predefined power
control modes with different clock generation sources and frequency
ranges:
Table 1 Available oscillators in each mode
Oscillator
Mode
High-Speed On-Chip Osc
Middle-Speed On-Chip Osc
Low-Speed On-Chip Osc
Main Clock Osc
Sub-Clock Osc
IWDT-Dedicated On-Chip Osc
Power Consumption
High-Speed
Available Available Available Available Available Available
High
Middle-Speed
Available Available Available Available Available Available
Low-Voltage
Available Available Available Available Available Available
Low-Speed
Available Available Available Available Available Available
Subosc-Speed
N/A N/A Available N/A Available Available Low
2.1.1 High-Speed Mode: The maximum operating frequency during
flash read is 32 MHz for ICLK. The operating voltage range is 2.4
to 5.5 V during flash read. However, for ICLK, the maximum
operating frequency during flash read is 16 MHz when the operating
voltage is 2.4 V or larger and smaller than 2.7 V. During flash
programming/erasure, the operating frequency range is 1 to 32 MHz
and the operating voltage range is 2.7 to 5.5 V. These
recommendations are summarized in Figure 1.
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Figure 1 System Clock Range for High-Speed Mode
2.1.2 Middle-Speed Mode The maximum operating frequency during
flash read is 12 MHz for ICLK. The operating voltage range is 1.8
to 5.5 V during flash read. However, for ICLK, the maximum
operating frequency during flash read is 8 MHz when the operating
voltage is 1.8 V or larger and smaller than 2.4 V. The voltage and
recommended frequencies of the Middle-Speed Mode are shown in
Figure 2.
Figure 2 System Clock Range for Middle-Speed Mode
2.1.3 Low-Voltage Mode After a reset is canceled, operation
starts in Low-Voltage Mode.
The maximum operating frequency during flash read is 4 MHz for
ICLK. The operating voltage range is 1.6 to 5.5 V during flash
read. During flash programming/erasure, the operating frequency
range is 1 to 4 MHz and the operating voltage range is 1.8 to 5.5
V.
Figure 3 System Clock Range for Low-Voltage Mode
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2.1.4 Low-Speed Mode The maximum operating frequency during
flash read is 1 MHz for ICLK. The operating voltage range is 1.8 to
5.5 V during flash read. P/E operations for flash memory are
prohibited.
Figure 4 The System Clock Range for the Low-Speed Mode
2.1.5 Subosc-Speed Mode The maximum operating frequency during
flash read is 37.6832 kHz for ICLK. The operating voltage range is
1.8 to 5.5V during flash read. P/E operations for flash memory are
prohibited.
Using the oscillators other than the sub-clock oscillator or
low-speed on-chip oscillator is prohibited.
Figure 5 The System Clock Range for the Subosc-Speed Mode
2.1.6 Transition between Power Control Modes To switch between
power modes, you must follow a recommended procedure for setting
registers. For example, switching from the Higher-Speed Mode to the
Low-Speed Mode should be performed in the following steps.
1. (Operation in High-Speed Mode) 2. Change the oscillator to
that used in Low-Speed Mode. Set the frequency of each clock lower
than the maximum
operating frequency in Low-Speed Mode 3. Turn off the
oscillators that are not required in Low-Speed Mode 4. Confirm that
the OPCCR.OPCMTSF flag is 0 (indicates transition completed) 5. Set
the OPCCR.OPCM bit to 11b (Low-Speed Mode) 6. Confirm that the
OPCCR.OPCMTSF flag is 0 (indicates transition completed) 7.
(Operation in Low-Speed Mode)
2.2 Three Low Power Modes To further reduce the power
consumption, the MCU can be “stopped”, entering one of the Low
Power Modes (LPM). The S124 has three LPM modes: Sleep mode,
Software Standby mode and Snooze mode. Their clock sources and
available peripheral modes are given in Table 2 (from the S124
User’s Manual).
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Table 2 Operating conditions of each low power mode
Item Sleep mode Software Standby mode Snooze mode*1
Transition condition WFI instruction while SBYCR.SSBY = 0
WFI instruction while SBYCR.SSBY = 1
Snooze request in Software Standby mode. SNZCR.SNZE = 1
Canceling method All interrupts. Any reset available in the
mode.
Interrupts shown in Table 10.3. Any reset available in the
mode.
Interrupts shown in Table 10.3. Any reset available in the
mode.
State after cancellation by an interrupt
Program execution state (interrupt processing)
Program execution state (interrupt processing)
Program execution state (interrupt processing)
State after cancellation by a reset Reset state Reset state
Reset state
Main clock oscillator Selectable Stop Selectable*2
Sub-clock oscillator Selectable Selectable Selectable
High-speed on-chip oscillator Selectable Stop Selectable
Middle-speed on-chip oscillator Selectable Stop Selectable
Low-speed on-chip oscillator Selectable Selectable
Selectable
IWDT-dedicated on-chip oscillator Selectable*4 Selectable*4
Selectable*4
Oscillation stop detection function Selectable Operation
prohibited Operation prohibited
Clock/buzzer output function Selectable Selectable*3
Selectable
CPU Stop (Retained) Stop (Retained) Stop (Retained)
SRAM Selectable Stop (Retained) Selectable
Flash memory Operating Stop (Retained) Stop (Retained)
Data Transfer Controller (DTC) Selectable Stop (Retained)
Selectable
USB 2.0 Full-Speed Module (USBFS)
Selectable Stop (Retained)*5 Operation prohibited*5
Watchdog Timer (WDT) Selectable Stop (Retained) Stop
(Retained)
Independent Watchdog Timer (IWDT)
Selectable*4 Selectable*4 Selectable*4
Realtime clock (RTC) Selectable Selectable Selectable
Asynchronous General Purpose Timer (AGTn, n = 0, 1)
Selectable Selectable*6 Selectable*6
14-Bit A/D Converter (ADC14) Selectable Stop (Retained)
Selectable*10
12-Bit D/A Converter (DAC12) Selectable Stop (Retained)
Selectable
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Capacitive Touch Sensing Unit (CTSU)
Selectable Stop (Retained) Selectable
Data Operation Circuit (DOC) Selectable Stop (Retained)
Selectable
Serial Communications Interface (SCI0)
Selectable Stop (Retained) Selectable*9
Serial Communications Interface (SCIn, n = 1, 9)
Selectable Stop (Retained) Operation prohibited
I2C Bus Interface (IIC0) Selectable Selectable Operation
prohibited
I2C Bus Interface (IIC1) Selectable Stop (Retained) Operation
prohibited
Event Link Controller (ELC) Selectable Stop (Retained)
Selectable*7
Low-Power Analog Comparator (ACMPLP0)
Selectable Selectable*8 Selectable*8
Low-Power Analog Comparator (ACMPLP1)
Selectable Selectable*8 Selectable*8
NMI, IRQn (n = 0 to 7) pin interrupt Selectable Selectable
Selectable
Key Interrupt Function (KINT) Selectable Selectable
Selectable
Low voltage detection (LVD) Selectable Selectable Selectable
Power-on reset circuit Operating Operating Operating
Other peripheral modules Selectable Stop (Retained) Operation
prohibited
I/O Ports Operating Retained Operating
Note: Selectable means that operating or not operating can be
selected by the control registers. Stop (Retained) means that the
contents of the internal registers are retained but the operations
are suspended. Operation prohibited means that the function must be
stopped before entering Software Standby mode. Otherwise, proper
operation is not guaranteed in Snooze mode.
1. All modules whose module-stop bits are 0 start as soon as
PCLKs are supplied after entering Snooze mode. To avoid an
increasing power consumption in Snooze mode, set the module-stop
bit of modules that are not required in Snooze mode to 1 before
entering Software Standby mode.
2. When using SCI0 in Snooze mode, the MOSCCR.MOSTP bit must be
1. 3. Stopped when the clock output source select bits
(CKOCR.CKOSEL[2:0]) are set to a value other than
010b (LOCO) and 100b (SOSC). 4. Operating or stopping is
selected by setting the IWDT stop control bit (IWDTSTPCTL) in
option function
select register 0 (OFS0) in IWDT auto-start mode. 5. Detection
of USBFS resumption is possible. 6. AGT0 operation is possible when
100b (LOCO) or 110b (SOSC) is selected by the
AGT0.AGTMR1.TCK[2:0] bits. AGT1 operation is possible when 100b
(LOCO), 110b (SOSC), or 101 (Underflow event signal from AGT0) is
selected by the AGT1.AGTMR1.TCK[2:0] bits.
7. Event lists the restrictions described in section 10.9.13,
ELC Event in Snooze Mode. 8. Only VCOUT function is permitted. The
VCOUT pin operates when ACMPLP uses no digital filter. For
details on digital filter, see section 33, Low-Power Analog
Comparator (ACMPLP). 9. Serial communication modes of SCI0 is only
in asynchronous mode. 10. When using the 14-Bit A/D Converter in
Snooze mode, the ADCMPCR.CMPAE or ADCMPCR.CMPBE
bit must be 1.
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2.2.1 Sleep Mode The CPU stops operating but the contents of its
internal registers are retained. Other peripheral functions do not
stop. The CPU can be woken by any interrupt, RES pin reset, a
power-on reset, a voltage monitor reset, an SRAM parity error
reset, or a reset caused by an IWDT or a WDT underflow. 2.2.2
Software Standby Mode The CPU, most of the on-chip peripheral
functions and oscillators stop. However, the contents of the CPU
internal registers and SRAM data, the states of on-chip peripheral
functions and the I/O Ports are retained. Software Standby mode
allows a significant reduction in power consumption because most of
the oscillators stop in this mode. Only those interrupts specified
by Wake Up Interrupt Enable Register (WUPEN) can cancel the
Software Standby Mode.
2.2.3 Snooze Mode Snooze mode is similar to the Sleep mode, but
some peripheral modules can operate without waking up the CPU.
Snooze Mode can be entered through the Software Standby Mode by
some interrupt sources, called as Snooze Requests, and woken up by
those interrupts available in the Software Standby Mode.
2.2.4 Transitions between the Low Power Modes Available
transitions between Normal mode and LPM modes are shown in Figure
6. The conditions or interrupt sources for triggering such a
transition are specified in the S124 User’s Manual.
Figure 6 The transitions between the Normal mode and three Low
Power modes
2.3 Power Consumption for Different Power Control Modes and Low
Power modes
The performance numbers, such as standby current, etc. have been
provided in the Section 41.2.9 of S124 User’s Manual. As a summary,
Table 41.11 gives the standby current for some combinations of the
power control modes and the low power modes.
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2.3.1 Standby Current of the Normal/Sleep Mode under the
High-Speed Mode
2.3.2 Standby Current of the Normal/Sleep Mode under the
Middle/Low-Speed Modes
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2.3.3 Standby Current of the Normal/Sleep Mode under the
Low-Voltage/Subosc-Speed Modes
2.3.4 Standby Current of the Normal/Software Standby Mode
Compared with the Sleep mode, the standby current of the
Software Standby Mode is even smaller.
3. Project: Making Low Power Mode Transitions with DK-S124 To
illustrate the power controlling modes transitions, and the
low-power mode transition, we created an application with DK-S124
board (V2). This section describes its HW/SW setup.
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3.1 Hardware: Renesas DK-S124 Kit This project is one of
applications developed on the Renesas DK-S124 version 2 board,
which is a development kit for the Renesas Synergy™ S124
microcontroller in a LQFP64 package as shown in Figure 7.
Figure 7 The DK-S124 Version Board
3.2 Project Design: Algorithms There are two sets of switchable
power modes supported by S124. Different modes and their
transitions can be abstracted into a finite state machine (FSM).
Therefore interaction between two sets of power modes will be
considered as a product of two FSMs. Assuming users making power
modes transitions at any time, such a product of FSMs may have 15
of states and more than 55 of transitions to be implemented. To
simplify this issue, we only consider 4 power controlling modes:
High-Speed Mode, Middle-Speed Mode, Low-Voltage Mode, and Low-Speed
Mode. The interaction of two FSMs is also implemented with a single
thread, as shown below. That application can be extended into a
more complicated implementation with two threads: one for power
controlling modes, and one for switching the normal mode into
different low power modes.
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Figure 8 Single thread based mode control algorithm
The state diagram of the FSM1 is shown in Figure 9.
Figure 9 State transition diagram of the FSM1
The FSM2 can be represented as in Figure 10.
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Figure 10 State transition diagrams of the FSM2
3.3 Project Design: User Interface The power mode transition
should be controllable, and visible for users. Therefore we need
two controllers for triggering state changes of FSM1 and FSM2, and
three LEDs to indicate different modes.
There are three push buttons, S1, S2, and S3, on the DK-S124
board. S3 is used for Reset, and S1 shares the same pin with the
interrupt signal from the 3-axis accelerometer. To use it, we have
to initialize the accelerometer through an I2C connection and pull
up P2_6/IRQ0. Thus we go through the LPM transition by pressing S1,
and generate PORT_IRQ3 for some tests by pressing S3. In addition,
the potentiometer POT1 is used for selecting different power
control modes: High-Speed, Middle-Speed, Low-Speed, and Low-Voltage
modes.
A simple user interface is designed as shown in Figure 11.
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Figure 11 User interface of design with DK-S124 (v2)
3.3.1 Potentiometer to select power controlling modes in FSM1 By
turning the potentiometer on the board, we can read its positions
or values through the ADC module in the S124, then set different
conditions for selecting power controlling modes. Table 3 shows a
possible configuration
Table 3 FSM1 transition controlled by the potentiometer
values
Conditions ADC values LED2, LED3 ConditionToHSM (14000, 17000)
11 ConditionToMSM (3000, 14000] 10 ConditionToLVM (800,3000] 01
ConditionToLSM (0, 800] 00
The values could be adjusted after calibreating the
potentiometer.
3.3.2 LED2 and LED3 indicating states of FSM1 Even though you
can use a multifunctional meter on the current measurement resistor
(R4) to observe the difference of each mode, we use a coding of
LED2 and LED3 to indicate different power controlling modes, which
is shown in Table 3above.
3.3.3 Button S1 to initiate low-power mode transition in FSM2
The transitions between the LPM and the Normal mode is triggered by
the interrupts generated by the RTC timer, AGT1 timer, and IRQ3,
which are listed in the available interrupt source for requesting
or ending the LPM. Note that the Sleep Mode can be cancelled by any
interrupt, so an IRQ3 is used here. The transition from the Normal
mode into one of the LPM is triggered by pressing S1, after the pin
P2_6 is released from the accelerometer.
3.3.4 LED1 for showing CPU status: normal or sleep To show the
CPU status: Normal or LPM, we use the LED1: On for the Normal Mode,
and Off for the LPM modes.
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4. Project Implementation: e2 studio and SSP As already shown,
to switch between different power controlling modes and low power
modes using bare-metal programming, users have to set all controls,
register by register and bit by bit in a specified order. It is
tedious and error-prone procedure. Fortunately, the Renesas
provides an IDE tool, e2 studio, and a software library/API to
overcome those barriers and accelerate project development. This
section gives a simple summery of this tool andlibrary.
4.1 Synergy e² studio The Renesas eclipse embedded studio, known
as e² studio Integrated Solution Development Environment (ISDE), is
a complete development and debug environment based on the popular
Eclipse CDT project. It allows engineers to integrate a wide range
of compilers for exploring different optimizations on running time
and memory space.
The latest version of e² studio is available for download at:
https://synergygallery.renesas.com. You need to create an account
or sign in to your account, then download the latest revision of
the e2 studio (ISDE). Following the installation instructions, you
need select the Renesas Synergy™ Device Family in the e2 studio
Setup dialog, then a GNU ARM compiler, such as GCC ARM Embedded
4.8.2014q3.
4.2 Synergy Software Package (SSP) The Renesas Synergy Software
Platform, SSP, is a complete and qualified platform for developing
embedded and IoT applications. It provides engineers with a
platform that already has basic system elements implemented,
configured, and tested. Therefore engineers can eliminate the time
normally needed to implement and integrate baseline functionality
and move almost immediately to product design, potentially reducing
time to market by months.
The latest version of SSP is also available for download at:
https://synergygallery.renesas.com. Following the installation
instructions, you can install SSP into the e2 studio.
SSP provides a power profile framework for users to put the MCU
into one of several available Low Power configurations. The
application also may make API calls that will place it into a low
power sleep mode from which an external interrupt, or periodic RTC
interrupt may awaken it.
For example, to make a switch from the High-Speed Mode into the
Low Speed Mode, users can implement with the following code:
if
(g_lpm0.p_api->operatingPowerModeSet(LPM_OPERATING_POWER_LOW_SPEED_MODE,
LPM_SUBOSC_OTHER)){ while(1); }
4.3 Configuration panels of SSP in e2 studio Assuming that a
project LPM_TRANSITION_DKS124 has been created, clicking the file
configuration.xml under Synergy Configuration tab shows the
following window for SSP setup. The SSP version and board
information are displayed on the BSP panel.
https://synergygallery.renesas.com/https://synergygallery.renesas.com/
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Figure 12 The SSP configuration Panel on the e2studio
4.4 Default Clock Frequency Setup The default clock frequencies
after power on is setup with the SSP panel, where users have five
different internal clock sources:
• Main clock oscillator (XTAL 12 MHz) • Sub clock oscillator
(SUBVLK 32,768 Hz) • High-speed on-chip oscillator (HOCO 48 MHz) •
Middle-speed on-chip oscillator (MOCO 8 MHz) • Low-speed on-chip
oscillator (LOCO 32,768 Hz)
Figure 13 CGC setup on the SSP clock panel
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The generated clocks are:
• The System clock (ICLK) is the operating clock for the CPU,
DTC, Flash, FlashIF, and SRAM. • The peripheral module clock,
(PCLKB) is the operating clocks for peripheral modules, CAC, ELC,
I/O Ports,
POEG, RTC, etc. • The peripheral module clock, (PCLKD), is the
operating clocks for GPT and ADC14 modules. Note that system clock
(ICLK), peripheral module clock (PCLKB and PCLKD), and FlashIF
clock (ICLK) must be set according to Table 8.2 in the S124 User
Manual.
4.5 Reading the Potentiometer with the SSP ADC Driver As
specified in the schematics of the DK-S124, potentiometer POT1 is
sampled through analog channel AN007 on the pin P0_12. So the
analog input function on pin P0_12 has to be enabled with the e2
studio pin configurator.
Figure 14 DK-S124 Potentiometer Circuit Schematic
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Figure 15 P0_12 Pin Configuration
An instance of the SSP ADC driver is called from the Thread
panel of the SSP configuration as shown in Figure 16. The Single
Scan mode is selected, and generates a Priority 1 interrupt at the
end of scanning. The procedure for reading POT1 can be simplified
as: //read the Potentiometer static void vReadPOT(void) { if
(g_adc0.p_api->open( g_adc0.p_ctrl, g_adc0.p_cfg )) { while(1);
} if (g_adc0.p_api->scanCfg( g_adc0.p_ctrl, g_adc0.p_channel_cfg
)) { while(1); } if (g_adc0.p_api->scanStart( g_adc0.p_ctrl )) {
while(1); } if (g_adc0.p_api->read( g_adc0.p_ctrl,
ADC_REG_CHANNEL_7, &u16ADCValue)){ while(1); } if
(g_adc0.p_api->scanStop( g_adc0.p_ctrl )) { while(1); } if
(g_adc0.p_api->close( g_adc0.p_ctrl )) { while(1); } }
Then the u16ADCValue will be used for selecting a power control
mode in the subroutine, vChangePCM(void).
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Figure 16 Set up the ADC API on the Thread panel
4.6 Waking up from Software Standby Mode with the SSP RTC Driver
One of the LPM transition paths in the FSM2 is Step3 of going from
Normal into the Software Standby Mode after an IRQ3 is generated by
pressing S2. Then Step4 returns the MCU back to Normal Mode after
an interrupt generated from a RTC periodic timer. This transition
has been used for running the ultra-low-power measurement standard,
EEMBC ULPBench on DK-S124. It runs 12 cycles or seconds of the
low-power modes and the normal mode as illustrated in Figure
17.
Figure 17 Running/sleeping cycles of the EEMBC ULPB
Note that conditions or interrupt sources from the Software
Standby mode are specified in the Wake up Interrupt Enable Register
(WUPEN) specified in the Section 12.2.8 of the S124 User’s
Manual.
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The Synergy SSP provides APIs for using RTC and LPM libraries in
the Power Profile Framework, and is configured with the Thread
panel of the SSP Configuration on e2studio.
Figure 18 Set up the RTC API on the Thread panel
An RTC-based timer is used to wake up the MCU every second. Its
counting clock source could be from sub-oscillator SOSC (32768Hz)
or LOCO (32768Hz).The LOCO is more energy efficient, so is selected
above.
Figure 19 Setup the LPM API on the Thread panel
The High-Speed Mode is selected as default state before entering
into one of the LPMs, and can be changed in the program in a simple
function call, such as switching into the Middle-Speed Mode in the
subroutine, vChangePCM(void).
if
(g_lpm0.p_api->operatingPowerModeSet(LPM_OPERATING_POWER_MIDDLE_SPEED_MODE,
LPM_SUBOSC_OTHER)){ while(1);
}
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To implement such a transition in the programming, we have the
following code for enter into and return from the Software Standby
Mode. //make a transition: Normal->Standby->Normal void
vTransition_NomSbyNom(void) { if
(g_lpm0.p_api->lowPowerCfg(LPM_LOW_POWER_MODE_STANDBY,
LPM_OUTPUT_PORT_ENABLE_HIGH_IMPEDANCE, LPM_POWER_SUPPLY_DEEPCUT3,
LPM_IO_PORT_NO_CHANGE)) { while (1); } //Get WUPEN reg value if
(g_lpm0.p_api->wupenGet(&u32WupenRegVal)) { while(1); }
//Set RTC interrupt as condition for waking up SBY if
((g_lpm0.p_api->wupenSet(u32WupenRegVal | WUPEN_RTC)) ) { while
(1); } vInitRTC(); //Start the RTC vStartRTC(); //LED1 Off
g_ioport_on_ioport.pinWrite(LED1_RED, LED_OFF); #ifdef DEBUG
printf("\n in software standby mode (step 3)\n"); #endif //WFI if
((g_lpm0.p_api->lowPowerModeEnter()) ){ while (1);
}
//wake up after RTC timer out (2sec) vToggleLED1(20);
g_ioport_on_ioport.pinWrite(LED1_RED, LED_ON); //Stop the RTC
vStopRTC(); //reset the WUPEN if
(g_lpm0.p_api->wupenGet(&u32WupenRegVal)) { while(1); } if
(g_lpm0.p_api->wupenSet(u32WupenRegVal &
(uint32_t)~(WUPEN_RTC|WUPEN_RTC)) ) { while (1); } #ifdef DEBUG
printf("\n rtc wakeup to normal mode (step 4)\n"); #endif }
5. Test and Observation Since this project is implemented with a
single tread and the same priority level for interrupts generated
from the controllers, testing and operating are relative simple.
Users can go through the power mode transitions with two ways:
• Approach 1: Adjusting the potentiometer POT1 to set a Power
Control Mode: the High-Speed Mode, the Middle-Speed Mode, the
Low-Voltage Mode and Low-Speed Mode; then pressing the button S1 to
make the MCU entering or returning from the Low Power Modes step by
step shown in the state transition diagram of the FSM2.
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• Approach 2: Modifying the void hal_entry(void) by
uncommenting/commenting the targeted transition/states to a
specific mode:
//for testing LPM states //lpm_transition = NORMAL_SLEEP_NORMAL;
//lpm_transition = NORMAL_SBY_NORMAL; //lpm_transition =
NORMAL_SBY_SNZ_SBY_NORMAL;
//lpm_transition = NORMAL_SBY_SNZ_NORMAL;
With these testing approaches, we can go through all of LPM
transitions. However, some combinations of requesting/ending Snooze
modes are still in further investigation and discussions.
Table 4 Observation of Mode Transitions
Nm -> Slp -> Nm Nm -> SBY -> Nm Nm -> SBY ->
SNZ -> SBY -> Nm
Nm -> SNZ -> Slp -> Nm
High Speed Ok Ok Ok Ok Middle Speed Ok Ok Ok Ok Low Voltage Ok
Ok Ok Ok Low Speed Ok Ok Ok Ok
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Website and Support Support:
https://synergygallery.renesas.com/support
Technical Contact Details
• America: https://renesas.zendesk.com/anonymous_requests/new •
Europe: http://www.renesas.eu/support/index.jsp • Japan:
http://japan.renesas.com/contact/index.jsp
All trademarks and registered trademarks are the property of
their respective owners.
https://synergygallery.renesas.com/supporthttps://renesas.zendesk.com/anonymous_requests/newhttp://www.renesas.eu/support/index.jsphttp://japan.renesas.com/contact/index.jsp
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A-1
Revision History
Rev. Date Description Page Summary
1.00 Jul 8, 2016 - Initial version
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reserved.Colophon 5.0
1. Overview2. Power Modes of Synergy MCU S1242.1 Five Power
Control Modes2.1.1 High-Speed Mode:2.1.2 Middle-Speed Mode2.1.3
Low-Voltage Mode2.1.4 Low-Speed Mode2.1.5 Subosc-Speed Mode2.1.6
Transition between Power Control Modes
2.2 Three Low Power Modes2.2.1 Sleep Mode2.2.2 Software Standby
Mode2.2.3 Snooze Mode2.2.4 Transitions between the Low Power
Modes
2.3 Power Consumption for Different Power Control Modes and Low
Power modes2.3.1 Standby Current of the Normal/Sleep Mode under the
High-Speed Mode2.3.2 Standby Current of the Normal/Sleep Mode under
the Middle/Low-Speed Modes2.3.3 Standby Current of the Normal/Sleep
Mode under the Low-Voltage/Subosc-Speed Modes2.3.4 Standby Current
of the Normal/Software Standby Mode
3. Project: Making Low Power Mode Transitions with DK-S1243.1
Hardware: Renesas DK-S124 Kit3.2 Project Design: Algorithms3.3
Project Design: User Interface3.3.1 Potentiometer to select power
controlling modes in FSM13.3.2 LED2 and LED3 indicating states of
FSM13.3.3 Button S1 to initiate low-power mode transition in
FSM23.3.4 LED1 for showing CPU status: normal or sleep
4. Project Implementation: e2 studio and SSP4.1 Synergy e²
studio4.2 Synergy Software Package (SSP)4.3 Configuration panels of
SSP in e2 studio4.4 Default Clock Frequency Setup4.5 Reading the
Potentiometer with the SSP ADC Driver4.6 Waking up from Software
Standby Mode with the SSP RTC Driver
5. Test and Observation