Page 1
ANGLES
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
DATE
APPDENG
DATE
APPDCK
ECNZONEREV
DO NOT SCALE DRAWING
X.XXX
X.XX
XX
DIMENSIONS ARE IN MILLIMETERS
THIRD ANGLE PROJECTIOND
SIZE
APPLICABLENOTED AS
MATERIAL/FINISH
NONE
SCALE
DESIGNER
MFG APPD
DESIGN CK
RELEASE
QA APPD
ENG APPD
DRAFTER
METRIC
OFSHT
DRAWING NUMBER
TITLE
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PARTII NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Apple Computer Inc.
12345678
12345678
B
C
D
A
B
C
D
A
REV.
DESCRIPTION OF CHANGE
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
DRAWING
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
SCHEM,MLB,MBP17
Schematic / PCB #’s
05/07/2007502656
M75/M76 Rule DefinitionsM76 Specific Constraints
ALS Support
Clock TerminationDDR2 SO-DIMM Connector ADDR2 SO-DIMM Connector B
33
34
T9_NOME49 12/21/200645 SMC
M75_MLB47 12/21/200644 Left Clutch Barrel Interconnect
M75_MLB46 12/04/200643 External USB Connector
M75_MLB44 12/07/200642 PATA Connector
M75_MLB43 12/04/200641 FireWire Ports
M75_MLB42 03/07/200740 FireWire Port Power
M75_MLB41 12/04/200639 FireWire PHY (TSB83AA22)
M75_MLB40 12/04/200638 FireWire Link (TSB83AA22)
M75_MLB39 12/21/200637 Ethernet Connector
T9_NOME38 03/19/200736 Yukon Power Control
T9_NOME37 01/25/200735 Ethernet (Yukon)
(MASTER)34 (MASTER)
Left I/O Board Connector(MASTER)
(MASTER)33 Memory Active TerminationM75_MLB
32 03/19/200732M75_MLB
31 03/19/200731M75_MLB
30 03/19/200730T9_NOME
29 01/25/200729 Clock (CK505)M75_MLB
28 03/19/200728 SB MiscT9_NOME
27 01/25/200727 SB DecouplingT9_NOME
26 01/25/200726 SB Power & GroundM75_MLB
25 04/02/200725 SB Pwr Mgt, GPIO, ClinkT9_NOME
24 01/25/200724 SB PCI, PCIe, DMI, USBT9_NOME
23 01/25/200723 SB Enet, Disk, FSB, LPCM75_MLB
22 03/20/200722 NB Graphics DecouplingT9_NOME
21 12/21/200621 NB Standard DecouplingT9_NOME
20 01/25/200720 NB GroundsT9_NOME
19 01/25/200719 NB Power 2T9_NOME
18 01/25/200718 NB Power 1T9_NOME
17 01/25/200717 NB DDR2 InterfacesT9_NOME
16 01/25/200716 NB Misc InterfacesT9_NOME
15 03/19/200715 NB PEG / Video InterfacesT9_NOME
14 01/25/200714 NB CPU InterfaceT9_NOME
13 01/22/200713 eXtended Debug Port (XDP)M75_MLB
12 12/07/200612 CPU Decoupling & VIDT9_NOME
11 01/25/200711 CPU Power & GroundT9_NOME
10 01/25/200710 CPU FSB(T9_MLB)
9 08/23/20069 Signal Aliases(MASTER)
8 (MASTER)8 Power AliasesMASTER
7 MASTER7 Functional / ICT TestN/A
6 N/A6 Revision HistoryN/A
5 N/A5 BOM ConfigurationN/A
4 N/A4 Power Block Diagram(T9_MLB)
3 08/23/20063 Power Block Diagram(T9_MLB)
2 08/23/20062 System Block Diagram
M75_MLB01/26/200710790 GPU (G84M) Constraints
T9_NOME01/25/200710689 FireWire Constraints
T9_NOME01/25/200710588 Clock & SMC Constraints
T9_NOME01/25/200710487 SB Constraints (2 of 2)
T9_NOME01/25/200710386 SB Constraints (1 of 2)
T9_NOME01/25/200710285 Memory Constraints
T9_NOME01/25/200710184 NB Constraints
T9_NOME01/25/200710083 CPU/FSB Constraints
M75_LIO01/23/20079982 Inverter Control IC
M75_LIO01/23/20079881 Inverter Support
(MASTER)(MASTER)9680 M76 Specific Connectors
M75_MLB03/19/20079579 LVDS Interface Mux
M75_MLB03/19/20079478 DVI Display Connector
M75_MLB03/19/20079077 LVDS Display Connector
M75_MLB03/21/20078976 GPU (G84M) Core Supply
M75_MLB03/19/20078875 NV G84M Video Interfaces
M75_MLB04/02/20078774 GPU Straps
M75_MLB03/19/20078673 NV G84M GPIO/MIO/Misc
M75_MLB04/02/20078572 GDDR3 Frame Buffer B
M75_MLB04/02/20078471 GDDR3 Frame Buffer A
M75_MLB03/19/20078270 NV G84M Frame Buffer I/F
M75_MLB03/19/20078169 NV G84M Core/FB Power
M75_MLB03/19/20078068 NV G84M PCI-E
M75_LIO03/08/20077967 PBus Supply & Batt. Charger
M75_MLB04/02/20077866 3.425V G3Hot Supply & Power Control
M75_MLB12/04/20067765 FW PHY Power Supplies
M75_MLB03/05/20077664 1.5V Power Supply
M75_MLB12/04/20067563 1.8V DDR2 Supply
M75_MLB03/05/20077462 1.25V / 1.05V Power Supply
M75_MLB12/04/20067361 5V / 3.3V Power Supply
M75_MLB03/05/20077260 IMVP6 NB Gfx Core Regulator
(MASTER)(MASTER)7159 IMVP6 CPU VCore Regulator
M75_MLB04/24/20077058 Power FETs
(MASTER)(MASTER)6957 DC-In & Battery Connectors
T9_NOME01/25/20076156 SPI BootROM
M75_MLB12/04/20065955 Sudden Motion Sensor (SMS)
M75_MLB12/04/20065854
(MASTER)(MASTER)5753 Current & Thermal Sensors
M75_MLB12/04/20065652 Fan Connectors
M75_MLB03/19/20075551 Thermal Sensors
M75_MLB03/19/20075450 Current Sensing
M75_MLB03/19/20075349 Current & Voltage Sensing
(MASTER)(MASTER)5248 SMBus Connections
M75_MLB12/04/20065147 LPC+ Debug Connector
02/02/2007M76_MLB92 109
PVT Release
A.0.0
SCHEM,MLB,MBP17
051-726192
? ??
1
N/A1 N/A1 Table of Contents
02/02/2007M76_MLB91 108
SCHEM,MLB,MBP17051-7261 1 SCH CRITICAL
ABBREV=DRAWINGTITLE=MLB
Page ContentsDate
Sync(.csa)
M75_MLB04/25/20075046 SMC Support
(.csa) Date
SyncPage Contents
PCBF,MLB,MBP17820-2132 CRITICALPCB1
SyncPage(.csa) Date
Contents
LAST_MODIFIED=Mon May 7 19:12:36 2007
Page 2
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
PG 23
CAMERA
PG 44
LEFT CLUTCH BARREL INTERCONN
Supply
Power
PG 67
U5570
Pg 51
Pg 51
U5500
Temp Sense
PG 54 ALS SENS
J6990/50
DC/Batt
U5805
CPU
GPU
ConnPG 57
PG 30
TERMSClocks
PG 29
CK 505
U2900
J3200J3100
DIMM
PG31,32
ITP/XDP CONN
DDR2 - Dual Channel
1.8V - 64 Bits
533/667/800? MHz
U1000
CPU
PG 13
J1300
PG 16/17
Main Memory
2.? GHz
PG 10
Core ~1.2V
PG 11,12
FSB
64-Bit
Core
1.05 - 1.25V
NB-GMCH
PG 14
TV
PCI-E
U1400
U5550 Pg 51Right Side
LPC Conn
PG 47
J5100
PG 44
WWAN
J4731
PG 80
GeyserTrackpad/Keyboard
J9600
U5900
PG 55
PG 52
FAN CONN
POWER SENSE PG 49-50
J5650/60
SUDDEN MOTION SENSOR
Ser
Prt
FanADC
Pg 46
SMC
BSBB,0 BSA
U4900
A
PG 80
Bluetooth
J9660
PG 80
IR
J9610
LEFT I/O
J3400
CLK CHIP
U2900
SPI
PG 56
Boot ROM
USB
J4600
PG 43
EXT-A
CONNPG 25
GPIOs
LPC
02
14
3
USB
5
PG 24
76
98
U6100
Misc
CLnk 0
PG 16
PG 16PG 16
DMI
PG 18~22
x4 DMI
2.5 GHz
DMI SPICLnk 0
PG 25 PG 24
SB-ICH8Core 1.05V
U2300
SATA
PG 24
PG 23
IDE
PG 23
PCI-E
PG 24
DIMM’s
J3200
J3100
PG 25
SMB
AZALIA
PG 23
TSB83BA22
FW-Link
U4000
32-Bit
33 MHz
TSB83AA22
Pg 38
Pg 39
FW-PHY
8-Bit
U4000
100 MHz
J4310
Conn
Pg 41
FireWire
J4300
PCI
PG 24PG 25
CLnk 1
PG 23
Pg 25
Core
E-NET
ETHERNET
Pg 35
(YUKON ULTRA)
J3900
U3700
E-NET
Pg 37
Conn
Pg 59
AudioCodec
U6200
PG 15
RGB
LVDS
800/1066? MHz
PG 15
LIO BOARD
Mini PCI-EAirPort
Out
x16 PCI-E
SDVO
PG 68
PCI-EBUS INTERFACE
GDDR3 FRAME BUFFER A/B
PG 71,72
U8400,U8450,U8500,U8550
PG 70
DVI-INTERFACE
Core1.25V - 0.96V
VIDEO INTERFACES
U8000NV G84M
NV G84M FRAME BUFFER I/F
PG 75
PG 78
DVI DISPLAY CONNJ9400
PG 79
LVDS INTERFACE MUX
U9550
PG 75
MUX
SATA-0
SATA-2
SATA-1
Ln1
Ln3
Ln2
1.2 V / 1.5 GHz
100 MHz
3.3 V
LVDS DISP
PG 77
J9000/10
Conn
PATA
Pg 42
Conn
Conn
J4400
J9660
PG 80
SATA
Ln4
Ln5
Ln6
3 - X1
2.5 GHz
PG 34
EXT-B
CONNSUSB
EXT-C
PG 34
EXPRESS CARD
PG 34 SYNC_MASTER=(T9_MLB)
A.0.0
922
051-7261
System Block DiagramSYNC_DATE=08/23/2006
Page 3
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
PPDCIN_G3H
PPBUS_G3H
(PAGE 62)(PAGE 64)
(PAGE 59)
(PAGE 60)
(PAGE 79)
(PAGE 79)
(PAGE 66)
(PAGE 65)
(PAGE 65)
(PAGE 62)
(PAGE 63)
(PAGE 61)
(PAGE 76)
(PAGE 57)
Q6950
U5705
INRUSH LIMITER
87438-0832
PGOOD
PPBUS_FW_FWPWRSW_F
P1V25_S0GPU_IOUT
U5430
PP1V25_ENET
418.1UF
TPS51117
LIO_DCIN_ISENSE
PP5V_S3
0.02UF 27
26
28
10
PM_PWRBTN_L
PLT_RST_L
PM_RSMRST_L
IMVP_VR_ON
FSB_CPURST_L
CPU_PWRGD
(10A MAX CURRENT)
SMC_RESET_LVOUT
U5000
PP1V05_S0
1175.81UF
PP3V42_G3H
RN5VD30A-F
PPVCORE_S0_NB_R
(0.2A MAX CURRENT)
(PAGE 46)
SMC RESET "BUTTON"
VOUT
536.54UF
(PAGE 66)U7800LT3470
NBCORE_IOUT
3.425V"G3HOT"
VIN
SHDN*
U5420
APGOOD
VOUT1.05V
TPS51117U7450
VIN
P1V5P1V05S0_PGOOD
SMC_CPU_VSENSE
EN_PSVPM_SLP_S3_L
(8A MAX CURRENT)PP1V5_S0
352.31UF
Q5315V
VOUT
PGOOD
TPS51117U7600
1.5VVIN
EN_PSV
SMC_PBUS_VSENSE
PM_SLP_S3_L
PWRBTN*
PLTRST*
RSMRST*
U2300
ICH8M
PWRGOOD
CPUPWRGD(GPIO49)
CPU
CLPWROK
VRMPWRGD
PWROK
PM_SB_PWROK
MCH
U1000
HCPURST*
RESET*
PLT_RST*
IMVP_VR_ON(P16)
99ms DLY
RSMRST_OUT(P15)
U1400
SMC
CL_PWROKPWROK
PWRGD(P12)
RSMRST_IN(P13)
SMC_ONOFF_L
RSMRST_PWRGD
ALL_SYS_PWRGD
VR_PWRGD_CLKENU2830
U2840
1720UF
PPVCORE_SO_CPU
1323.67UF
U7880
PM_ALL_GFX_PGOOD
PM_ALL_S0_PWRGD
4A
S
PWR_BUTTON(P90)
RST*
P17(BTN_OUT)
(PAGE 45)U4900
PM_SLP_S5_L(P95)
PM_SLP_S4_L(P94)
PM_SLP_S3_L(P93)
05
08-1
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
POWER ON SEQUENCE LIST
10-13
01-0401,05-09
STEP 06 (S5 POWER STATUS)TRUTH TABLE
L(S5 OFF)L(S5 OFF)
ADAPTER IN :
BATTERY ONLY:
25-2717,19-2414-18
H(S5 ON)H(S5 ON)
STEP
99ms200ms7ms
S0_PGOOD_PWROK
PWR/RST STATUSG3H POWER ONS5 POWER ONS3 POWER ON
SIGNAL DELAY TIME
IMVP_VR_ON
S0 SYSTEM POWER ON
S0PWRGD_OKVR_PWRGOOD_DELAY
U7885
RST*
S0 CPU POWER ON
BATTERY ONLY,PRESS PWR BUTTON
NO AC/BATTERY
ACIN WITH/WITHOUT BATTERYBATTERY ONLY
PLATFORM,CPU RESET
PM_ALL_NBGFX_PGOOD
74CBTLV3257U9560
LVDSCTRLMUX_SEL_GPU_L
(0.2A MAX CURRENT)
PANEL/BACKLIGHT CONTROL MUX
LTC2900U7870
NBGFXCORE_IOUT
(10A MAX CURRENT)PPVCORE_SO_NB_GFX
(44A MAX CURRENT)
V
CPUVCORE_IOUTA
A
U5410
VOUT
U5400
VR_PWRGD_CLKEN_L
VR_PWRGOOD_DELAY
CLKEN#
VOUT
U7100
VIN
PGOOD
ISL6263
VIN
U7200
VR_ON
4B1
4B2
PM_ALL_GPU_PGOOD
RST*
PGOOD
V2(3.3V)
V3(1.8V)
V4(1.25V)
V1(3.3V)
GFX_VR_EN
CPUVCOREISL9504
VR_ONIMVP_VR_ON
5.9UF
PP5V_S0
165UF
PP3V3_S5
PP3V3_S0
3.4UF
7.2UF
PP3V3_S3
PP3V3_GPU
3.91UF
V1(5V)
V2(3.3V)
V3(1.8V)
V4(1.25V)
U9590LTC2900
81.3UF
4.2UF
27.11UF
PP1V95_FW
PP3V3_FW
VOUT
TPS799195
U7720
PP1V25_GPU
PP1V9_ENET
1UF
VOUT
(PAGE 36)TPS79501
VOUT
U3850EN
IN
P1V25GPU_SS
Q7090
PP3V3_ENET
6.102UF
22.1UF
U7700
LT3470SHDN*
VIN
VIN
ENPPVIN_FW_3.3VFW
PPVP_FW
P3V3ENET_SS
P3V3GPU_SS
P1V25S0_SS
P3V3S0_SS
P5VS0_SS
P5VS3_SS
P3V3S3_SS
PP5V_S5
PP1V25_S0
384.1UF
M76 POWER SYSTEM ARCHITECTURE
AU5705
PPVBAT_G3H_CHGR_OUT
VOUT
FET(PAGE 67)
U7900
(PAGE 67)
CHGR_EN
PBUS SUPPLY /BATTERY CHARGER
BATTERY CHARGE
ISL6255A
VIN
ENABLES
PPVBATT_G3H_FET
LIO_DCIN_ISENSE
A
8A FUSE
PP18V5_G3H_CHGRVOUT
BATT_POS
VIN
PP18V5_DCIN
87438-1043CRITICALJ6950
518S0456
CRITICALJ6990
Q7000
Q7020
PPVCORE_GPU(18A MAX CURRENT)
675UF
SMC_GPU_VSENSE
V
A
Q7010
Q7030
Q7070
2.7UF
PP0V9_S0
PP1V8_S3
PP5V_S5
RSMRST_PWRGD
PP3V3_S5
CURRENT)
(8A MAX CURRENT)
(5.5A MAX
GPUVCORE_IOUT
U8995
VOUT
U8900
VIN
EN_PSV
VOUT1
GPUVCORE_PGOOD
PGOOD
5VVIN
ENA1
PM_GPUVCORE_EN
SMC_PM_G2_EN
VOUT2
TPS51120
3.3V
U7300
VOUT1
0.9V
VIN
1.8VS5_EN
S3_VTT_EN
ENA2
PM_SLP_S3_L
PM_SLP_S4_L
728.6UF
Q3810
2.1UF
159.36UF
PP1V8_S0
P1V8S0_SS
PP1V8_GPU
P1V8GPU_SS
Q7050
Q7080
A
Q7095345.203UF
1.5A FUSE
A
U5440
PP1V8_S3_ISNS
P1V8_S3_IOUT
(8A MAX CURRENT)
VOUT2
TPS511160U7500
TP1V8S3_PGOOD
PGOOD
(UNUSED)
VIN
VOUTEN_PSV
P3V3ENET_SS
TP1V25ENET_PGOOD
U7400TPS51117
(UNUSED)
PGOOD
Q4260
P3V3ENET_SS
P1V8GPU_SS
PM_ENET_EN
PM_GPUVCORE_EN
P3V3GPU_SS
P1V25GPU_SS
P5VS3_SS
P3V3S3_SS
DELAY
R=100K
C=68NF
R=100K
C=68NF
DELAY
518S0457
Q7002
Q7012
C=1UF
C=1UF
R=100K
DELAY
R=100K
DELAY
PM_SLP_S4_L
Q7091
Q7851
Q7072
Q7851
PM_SLP_S3_LS5V
EXTGPU_PWR_EN
PM_SLP_S3_L
Q7091
GPUVCORE_PGOOD
SLP_S3*
GPIO23
SLP_S4*
U2300ICH8M
R=100K
PM_GPUP1V8FET_EN
DELAY
C=1UF
PM_ENET_EN
C=1UF
DELAY
R=100K
Q3800Q3801
Q7081Q7081
Q7850
Q3801
SMC_ADAPTER_EN
R=100K P1V8S0_SS
DELAY
P1V25S0_SS
DELAY
R=100K
C=1UF
C=1UF
P3V3S0_SS
P5VS0_SS
DELAY
C=1UF
Q7051
R=100K
R=100K
C=1UF
DELAY
Q7096
Q7002
Q7012
Q7051
Q7096
Q7850
SYNC_MASTER=(T9_MLB)
3 92
A.0.0051-7261
SYNC_DATE=08/23/2006
Power Block Diagram
Page 4
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Power Block Diagram
051-7261 A.0.0
924
SYNC_MASTER=N/A SYNC_DATE=N/A
Page 5
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
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TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD
BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM Variants
Bar Code Labels / EEE #’s
Module Parts
M76 BOM Groups
Alternate Parts
630-8733 M76_COMMON,CPU_2_4GHZ,FB_256_HYNIX,M76_CTO,EEE_XZ7PCBA,2.4GHZ,CTO,VRAM-HY,MBP17
M76_COMMON COMMON,ALTERNATE,M76_COMMON1,M76_COMMON2,M76_DEBUG,M76_PROGPARTS,ISL6257H
EXTGPU_RST_HW,ISL9504B,LVDS_SEL_RESUME,ONEWIRE_PU,CPU_NTC_A,GPU_XW1M76_COMMON1
SYNC_DATE=N/A
92
A.0.0051-7261
5
BOM ConfigurationSYNC_MASTER=N/A
M76_COMMON2 P1V8S3_1V825_GPUFB,SLG2AP101,SMS_MOT_DIS,YUKON_ULTRA,VGA_TERM_CONN
M76_CTO INV_SPLIT,INV_17INCH
U80001 CRITICAL338S0388 IC,GPU,NV G84M,BGA
M76_COMMON,CPU_2_4GHZ,FB_256_HYNIX,INV_BYPASS,EEE_XWUPCBA,2.4GHZ,BTR,VRAM-HY,MBP17630-8549
M76_DEBUG SMC_DEBUG_NO,XDP,LPCPLUS
LBL,P/N LABEL,PCB,28MM X 6 MM EEE_XZ7[EEE:XZ7]1826-4393 CRITICAL
LBL,P/N LABEL,PCB,28MM X 6 MM EEE_XZ6[EEE:XZ6] CRITICAL826-4393 1
EEE_XWU[EEE:XWU] CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM1826-4393
VRAM_256,VRAM_HYNIX,VRAM_256_HYNIXFB_256_HYNIX
U14001 CRITICAL338S0432 IC,NB,CRESTLINE,GM,C0,PRQ,965PM
U2300 CRITICAL1338S0434 IC,SB,ICH8M,B1,PRQ,BGA
CRITICAL SLG2AP101U29001359S0130 IC,SLG2AP101,LW PWR CLK GEN,CK505,QFN68
SLG8LP537U2900 CRITICAL1359S0127 IC,68 PIN,CK505,LOW POWER CLOCK GENER
ISL9504BCRITICALU7100353S1651 1 IC,ISL9504B,2PH IMVP6 REG,PMON,QFN48
SMC_BLANKU4900 CRITICAL1338S0274 IC,SMC,HS8/2116
BOOTROM_PROG1 U6100 CRITICALIC,EFI ROM,DEVELOPMENT,M75341S2002
BOOTROM_BLANKU6100 CRITICAL1 IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8335S0384
VRAM_256_SAMSUNG4 U8400,U8450,U8500,U8550 CRITICAL333S0382 IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA
CRITICAL SMC_PROG1 U4900IC,SMC,DEVELOPMENT,M76341S2050
4 CRITICAL VRAM_256_HYNIXU8400,U8450,U8500,U8550333S0401 IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA
CPU_2_4GHZU1000 CRITICAL1337S3465 IC,MDC,SR,E1,PRQ,2.4G,35W,800FSB,4M,BGA
FB_256_SAMSUNG VRAM_256,VRAM_SAMSUNG,VRAM_256_SAMSUNG
EEE_X6P[EEE:X6P]LBL,P/N LABEL,PCB,28MM X 6 MM1 CRITICAL826-4393
M76_PROGPARTS BOOTROM_PROG,SMC_PROG
ALL152S0276152S0476 Inductor alternate
376S0543 376S0466 AOS alternate to Siliconix Si4413ALL
353S1294 TI alternate to National353S1681 ALL
376S0526 Fairchild FDW252P alternate to IRF7707376S0451 ALL
138S0602 ALL138S0603 Murata alt to Samsung 22uF acoustic caps
CRITICALU37001338S0386 IC,88E8058,GIGABIT ENET XCVR,64P QFN
U7100 CRITICAL1 ISL9504A353S1461 IC,ISL9504,SYNC REG CTRL,2PHAS,QFN48,LF
E&E alt to TDK/BiTech magnetics157S0011 157S0030 ALL
630-8732 M76_COMMON,CPU_2_4GHZ,FB_256_SAMSUNG,M76_CTO,EEE_XZ6PCBA,2.4GHZ,CTO,VRAM-SAM,MBP17
M76_COMMON,CPU_2_4GHZ,FB_256_SAMSUNG,INV_BYPASS,EEE_X6PPCBA,2.4GHZ,BTR,VRAM-SAM,MBP17630-7943
Page 6
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
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NONE
- Thermal Sensors: Updated topology of EMC1033 sensors (removed shorts, changed connector caps to 18pF)- Power Supplies: Replaced APN 152S0511 with 152S0368 (duplicate APNs for same part - rdar://5009109)
- Left Clutch IC: Updated both I-PEX connectors to new APN (part update for shell plating)Changes since previous major release (12.2.0):
Changes since previous major release (12.3.0):Change 46833 by cerickso@m75_mlb_051-7225_12.5.0_tmp.Ecad on 2007/03/02 09:49:13
13.1.0:
DVT
- NB GFX Decoupling/Power Aliases: Connected VCCD_CRT of NB to GND per CRT disable guidelines
Quick submit of T9 noME branch. Major release will follow once changes are properly documented in Radar and revision history.
- Thermal Sensors: Moved remote sensor U5500 to SMC SMBus A and S3 power rail to clear I2C addr clash
- Thermal Sensors/Aliases: Changed mounting pads of Th2H sensor connector to left clutch chassis gnd
3/14/07 -- Moved =PP1V8_GPU_P1V8GPUFET from PP1V8_S3_ISNS to PP1V8_S3. This is to remove the current sense resistor from the GPU 1.8V path.
3/08/07 -- Changed BOM option on R9960 511K from NOSTUFF to INV_SPLIT to improve current and voltage asymmetry ratio.
3/08/07 -- Changed R9811 from 15.0K to 14.0K. This is so that M57 inverter and split inverter can use same backlight table.
3/08/07 -- Removed =PP1V5_S0_NB_VCCD_CRT alias to PP1V5_S0 since VCCD_CRT is GNDed per CRT disable guidelines.
Deleted R7420 and R7470 and made C7420 and C7470 0603 size, still 0.1uF (132S0100).Deleted R7364 and made C7364 0603 size, still 0.1uF (132S0100).<rdar://problem/5070179> BOM update: boost circuit open causes MLB & SIMM damage (see 5064997)
3/19/07 -- SMBus: moved Remote Temps from SMC B to SMC A in order to use EMC1043-5.3/19/07 -- Added BOM table with 0 Ohm 0603 resistors at L4731,L4741.3/19/07 -- Added OMIT BOM option to L4731 and L4741.Page 38: Changed Yukon crystal load caps to 18pF per radar://4946795 (really radar://4945362).Page 15: Sync from main-line (renamed LVDS_VREFx nets).
Change 48372 by wferry@wferry_projects.Ecad on 2007/03/16 09:11:013/19/07 --Integrated t9/mlb_noME CSA pgs. 15 & 38 through:
Changes since previous major release (13.2.0):Change 48405 by cerickso@m75_mlb_051-7225_13.3.0_tmp.Ecad on 2007/03/16 12:18:46Integrated m75/mlb CSA pgs. 28,30-32,50,53-55,80-82,84-88,90,94,95 through:
3/15/07 -- Changes to low voltage inverter for M76 piezo.
3/14/07 -- Moved =PP1V8_S0_P1V8S0FET from PP1V8_S3_ISNS to PP1V8_S3.
- Power Control: Corrected alias connections for 5V/3V3 S5 enable signals
Change 48122 by cerickso@cerickso_m75.Ecad on 2007/03/14 15:27:363/14/07 -- Integrated m75/mlb CSA pages 55 & 78 through:3/14/07 -- Constraints: Constrained WWAN_SIM signals to 50 ohms
3/14/07 -- Removed BOM option for HDCP as feature is removed.
Changed BOM options for R7520 to choose between 1.8V or 1.825V 0.1% resistors.Removed OMIT BOM option from R7521.3/12/07 -- Modified R7520 and R7521 to use symbols for 0.1% resistors.3/12/07 -- Added BOM option P1V8S3_1V825 to M76_COMMON2 BOM group.
Changed Charger PWM limit resistor according to MARC K.’S M70 valuesChange 47440 by xyang@m75_lio_051-7226_7.9.0_tmp.Ecad on 2007/03/08 10:25:463/08/07 -- Integrated CSA pg. 79 through:- Thermal Sensors: Added R5515/R5516 in case low pass filter is needed for EMC1033Changes since previous major release (12.7.0):Change 47450 by cerickso@m75_mlb_051-7225_12.8.0_tmp.Ecad on 2007/03/08 10:49:263/08/07 -- Integrated CSA pg. 55 through:
3/08/07 -- Changed R9950 from 220K to NOSTUFF to improve current and voltage asymmetry ratio.
3/08/07 -- Battery charge current limit circuit changes.
3/07/07 -- Q7080 PP1V8_GPU FET changed for lower Rds on from FDM6296 to RJK0301DPB
Changes since previous major release (12.6.0):
3/07/07 -- Integrated m75/mlb pages 25,42,70 through:
3/5/07 -- ODD Conn: Changed ODD power FET to FDC606P (from FDC638P) for reduced Rds(on)3/5/07 -- FireWire: Changed to Rev C of TI FireWire MCM (APN: 338S0435)
3/5/07 -- Added GPU Vcore VFB resistor BOM table and GCORE_M76 BOM Option to M76_COMMON BOM group.
- SB GPIOs: Sync’d page25.csa to T9_MLB to get pullup updates- GPU Vcore: Updated voltage setpoints to 1.000/1.070/1.125V- GPU Vcore: NO STUFFed all PWRCTL related components (feature not to be supported)- Power Sequencing: Removed U7885/C7885 to take GFX_PGOOD out of PWR_OK chain (rdar://4974927)
- GPU FB: Changed cal resistors per NVidia PUN (R8290 to 45.3 ohm and R8291 to 24.9 ohm)Changes since previous bom release (12.0.0):
3/19/07 --
3/19/07 --14.5.0
14.2.0
14.1.0
Cleaned up unused aliases.
14.0.0
13.4.0
13.2.0
3/5/07 -- Removed RX3920-RX3927.
3/19/07 -- Integrated m75/mlb CSA pgs. 22 & 78 through:3/19/07 -- Battery charge current limit circuit changes for max charge current of 4.5A.3/19/07 -- Added three 0603 0 ohm resistors R4740-R4742 for EMC return current path.
3/19/07 -- Deleted R7324 and made C7324 0603 size, still 0.1uF (132S0100).3/19/07 -- Updated SMC A SMBus information for Left I/O Board and Top-Case.- Power Control: Added U7858 to level shift PM_G2_EN to 3.42V to 5V- Thermal Sensors: Updated U5500 power alias to indicate device should be on S3 rail
Change 48590 by cerickso@m75_mlb_051-7225_13.4.0_tmp.Ecad on 2007/03/19 14:26:143/19/07 -- Integrated m75/mlb CSA pgs. 55 & 78 through:
L9950 changed from 152S0527 (15uH, 2.8A, 115mOhm) to 152S0585 (22uH, 2.8A, 129mOhm).3/19/07 -- Changes to low voltage inverter for M76 piezo.Deleted R8915 and made C8915 0603 size, still 0.1uF (132S0100).Deleted R7615 and made C7615 0603 size, still 0.1uF (132S0100).Deleted R7525 and made C7525 0805 size, still 0.1uF (132S0201).
14.7.0
Changes since previous major release (13.3.0):
14.6.0
3/05/07 -- Integrated m75/mlb pages 22,25,28,30-32,50,53-55,72,74,76,78,80-82,84-90,94,95 through:
Change 47192 by cerickso@m75_mlb_051-7225_12.7.0_tmp.Ecad on 2007/03/06 18:36:54
- SB GPIOs: Changed R2514 from pulldown to pulldown to correct auto power-on issue (Linda card detect GPIO)- FireWire Ports: Changed D4260 to PDS540 for higher current capacity
- Thermal Sensors: Updated topology of EMC1033 filter caps (added C5515 next to IC, moved other caps to connectors)
- GPU FB: Changed unterminated-mode reference voltage to 40% (R8297 -> 1.02k, R8432/82, R8532/82 -> 2.21K)
- NB GFX Core: Changed Vcore controller to ISL6263B (part consolidation effort between Apple/Intersil - rdar://5009109)
- NB GFX Decoupling: Added R2260 (0.3 ohm, 0603) to bring ESR of regulator output cap in spec (rdar://5000272)- LVDS Connector: Changed pin 5 of connector from NC to PP3V3_SW_LCD (in case we add extra cable for power - rdar://5024882)
- Power Control: Tied all 4 5V/3.3V enables (EN1, EN2, EN3 and EN5) together as part of PM_G2_EN
Change 48885 by cerickso@m75_mlb_051-7225_14.0.0_tmp.Ecad on 2007/03/20 21:27:14
Change BOM option on L4764 to OMIT and added BOM table entry for 0 ohm resistor at L4764.
Changed resistors for M76 Vcore setpoints (i.e. 1.05V, 1.05V, 1.125V, 1.25V)
3/22/07 -- Items relating to <rdar://problem/5061583> Task: Current Surge When Insert Battery Without AC Plugged-In3/22/07 -- Added D7903 for voltage ripple on ISL6257 BOOT and PHASE pins.
3/28/07 -- Change BOM option for 1.8V regulator feedback to 1.8V GPU FET input.3/28/07 -- Added XW7580 and R7580 for option to tie 1.8V S3 regulator feedback point to input of 1.8V GPU FET.
3/31/97 -- Changed C9950 from 22uF to 10uF for acoustic noise per Flo Kim.3/31/97 --Added C9951 B2 case size as placeholder for new cap for acoustic noise per Flo Kim.
14.8.0
This fab release is for DVT!
3/21/07 -- Integrated m75/mlb CSA pgs. 84,85 & 89 through:
3/21/07 -- <rdar://problem/4838347> EMC - M76 MLB changes
Removed NOSTUFF BOM option from R8924.Changed R8924 to 28K.Changed R8925 to 16.9K.Changed table text notes.
3/28/07 -- Integrated m75/mlb CSA pg. 87 through
Changes since previous fab release (14.0.0):- GPU Straps: Added PCI_DEVID<3..0> pullup straps
3/29/07-- Moved XW7580 to XW0980, and R7580 to R0980.
3/21/07 -- <rdar://problem/5073301> M76: Change GPU Vmin
3/22/07 -- Added Q7970 for potential battery inrush current.
3/26/07 -- Removed C7930 and R7903 for space reasons.
Change 49919 by cerickso@cerickso_m75.Ecad on 2007/03/28 14:28:29
15.0.0
15.2.0
15.3.0
15.4.013.3.0
Change 48660 by cerickso@m75_mlb_051-7225_13.5.0_tmp.Ecad on 2007/03/19 20:17:1Changes since previous major release (13.4.0):
Changes since previous major release (13.5.0):- GPU Vcore: Updated setpoints for GPU Vcore based upon Nvidia Vmin (i.e. 1.05V, 1.05V, 1.05V, 1.125V)- FB: Changed FB VREF caps to 2x0.0047uF as required by Nvidia PUN 02736-001-v07 (which requests 1x0.01uF)
3/5/07 -- Changed 1.8V supply feedback resistors R7520 to 21.5K 0.1% and R7521 15.0K 0.1%.%
6 92
A.0.0051-7261
Revision HistorySYNC_MASTER=N/A SYNC_DATE=N/A
Page 7
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
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NONE
NO_TEST
ICT Test Points
CPU FSB NO_TESTs
GPU NO_TESTs
FUNC_TEST
LPC+ Debug Connector
NB NO_TESTs
NO_TEST
BASEMAKE_
NO_TESTMAKE_BASE
Functional Test Points
Battery Digital Connector
Left Clutch Barrel Connector
Other Func Test Points
FUNC_TEST
FUNC_TEST
Left ALS
Thermal Diode Connectors
FUNC_TEST
6 TPs, 2 with each of above TP pairs
FUNC_TEST
Inverter ConnectorCurrent Sense Calibration
NOTE: 10 additional GND test points are
2 TPsper
FUNC_TEST
Request for at least 10 GND test points
FUNC_TEST
System Validation TPs
Fan Connectors
Request for 2 test points
Request for 3 test points
FUNC_TEST
FUNC_TEST
FUNC_TEST
FUNC_TEST
FUNC_TEST
called out separately in these notes.
IR & Sleep LED Connector
FUNC_TEST
(HOST_DETECT_L)
RTC Battery Connector
Left I/O Power Connector
FUNC_TEST
I404
I405
I406
I407
I408
I409
I410
I411
I412
I413
I414
I415
I416
I417
I418
I419
I420
I421
I422
I423
I424
I426
I427
I428
I430
I431
I432
I433
I436
I442
I443
I447
I448
I490
I491
I492
I493
I494
I495
I496
I497
I498
I506
I507
I509
I515
I516
I517
I519
I520
I521
I522
I523
I524
I529
I530
I531
I533
I534
I535
I536
I539
I540
I541
I542
I544
I545
I546
I547
I548
I549
I550
I551
I552
I553
I554
I555
I556
I557
I558 I559
I561
I562
I563
I564
I565
I566
I567
I568
I569
I570
I571I576
I577
Functional / ICT Test
051-7261 A.0.0
927
SYNC_MASTER=MASTER SYNC_DATE=MASTER
NC_GPUVCORE_VFB_PC1TRUE
TRUE NC_GPUVCORE_VFB_PC0TP_GPU_MIOB_CTL3TRUE
TRUE TP_GPU_MIOB_CLKOUT_PTRUE TP_GPU_MIOB_CLKIN
NC_NB_NC<1..16>TRUETRUE FSB_A_L<31..3>
TRUE FSB_ADSTB_L<1..0>
FSB_DBSY_LTRUE
TRUE FSB_DRDY_L
LVDS_L_CLK_PTRUE
TRUE SMC_BS_ALRT_L
FAN_LT_TACHTRUENC_NB_RSVD<26..27>TRUETRUE
TRUE NC_NB_RSVD<24>TRUE
TRUE LVDS_L_DATA_P<0>
TP_NB_RSVD<26..27>
TP_NB_NC<1..16>
FSB_BNR_LTRUE
TP_NB_RSVD<24>
FSB_REQ_L<4..0>TRUE
TRUE FSB_HIT_L
TRUE FSB_DSTB_L_N<3..0>
FSB_DINV_L<3..0>TRUE
TRUE PM_CLKRUN_L
LPC_FRAME_LTRUE
LPC_AD<1>TRUE
NC_CPU_RSVD5TRUETRUE TP_CPU_RSVD5
FSB_BREQ0_LTRUE
FSB_ADS_LTRUE
FSB_HITM_LTRUE
FAN_RT_PWMTRUE
TRUE BOOT_LPC_SPI_L
LPC_AD<2>TRUE
TRUE ISENSE_CAL_EN
=PP5V_S0_ISENSECALTRUE=PPVCORE_S0_NBGFX_REGTRUE=PPVCORE_S0_CPU_REGTRUE
TRUE FSB_LOCK_L
FSB_D_L<63..0>TRUE
TRUE FSB_DSTB_L_P<3..0>
=SMBUS_BATT_SCLTRUE
PP5V_S3_WWAN_FTRUEUSB_WWAN_F_NTRUE
LCDBKLT_PWMTRUE
TRUE PP5V_SW_LCDBKLTTRUE =GND_CHASSIS_INVERTERTRUE PPBUS_S0_LCDBKLT_FUSED
=PP3V3_S5_LPCPLUSTRUE
TRUE SMC_TMS
SMC_TRST_LTRUE
SMC_MD1TRUE
HSTHMSNS_D_NTRUE
HSTHMSNS_D_PTRUE
TRUE RSFSTHMSNS_D_P
TRUE RSFSTHMSNS_D_N
TRUE CPUTHMSNS_D2_N
CPUTHMSNS_D2_PTRUE
TRUE SMC_RESET_L
TRUE SMC_NMI
LINDACARD_GPIOTRUE
=PPVCORE_GPU_REGTRUE
=PP5V_S3_IRTRUEUSB_IR_NTRUE
TRUE NB_CLK100M_PCIE_P
FSB_CLK_NB_NTRUETRUE NB_CLKREQ_L
TRUE NB_CLK100M_PCIE_NNB_CLK96M_DOT_PTRUE
CPU_THERMTRIP_RTRUETRUE NB_CLK100M_DPLLSS_NTRUE NB_CLK100M_DPLLSS_P
NB_CLK96M_DOT_NTRUE
TRUE GPU_RESET_LTRUE NB_RESET_L
PP5V_S3_CAMERA_FTRUE
TRUE SMC_TCK
TRUE CPU_PWRGD
TRUE PM_DPRSLPVRCPU_DPSLP_LTRUE
P1V5P1V05S0_PGOODTRUECPU_DPRSTP_LTRUE
TRUE PM_ENET_ENPM_SLP_S5_LTRUE
TRUE PM_S4_STATE_L
TRUE CPU_DPSLP_L
PM_BMBUSY_LTRUENB_SB_SYNC_LTRUEFSB_DPWR_LTRUEFSB_CPUSLP_LTRUEFSB_CPURST_LTRUE
TRUE VR_PWRGOOD_DELAYVR_PWRGD_CLKENTRUE
PM_STPCPU_LTRUESB_RTC_RST_LTRUEPM_SB_PWROKTRUE
PCI_RST_LTRUE
TRUE LTALS_OUT
TRUE PM_SUS_STAT_L
SMC_TX_LTRUE
FAN_LT_PWMTRUE=SMBUS_BATT_SDATRUE
TRUE SYS_LED_ANODE
CPU_STPCLK_LTRUEFSB_CLK_NB_PTRUE
TRUE USB_CAMERA_F_P
USB_CAMERA_F_NTRUE
SMC_LRESET_LTRUE
PM_STPPCI_LTRUE
TRUE PM_LAN_ENABLE
TRUE ALS_GAIN
TRUE SMC_TDI
INT_SERIRQTRUE
LPC_AD<3>TRUE
TRUE FWH_INIT_L
TRUE SMC_TDO
LPC_AD<0>TRUE
FAN_RT_TACHTRUE
TRUE PLT_RST_L
TRUE SMC_RX_L
PM_SLP_S3_LTRUE
PM_RSMRST_LTRUE
FSB_CLK_CPU_NTRUE
TRUE PCI_CLK33M_LPCPLUS
USB_WWAN_F_PTRUE
TRUE USB_IR_P
=PP5V_S0_LPCPLUSTRUE
TRUE DEBUG_RESET_L
TRUE IMVP_VR_ONTRUE IMVP_DPRSLPVR
TRUE FSB_CLK_CPU_P
=PP5V_S0_FAN_LTTRUE
TRUE IMVP6_VID<6..0>
TRUE PP18V5_DCIN
=BATT_NEGTRUE
=BATT_POSTRUE
TRUE =PPBUS_G3H_LIO_CONN
TRUE PM_SYSRST_L
TRUE SMC_ONOFF_L
PPVBATT_G3_RTCTRUE
TRUE GND
TRUE GND
TRUE GND
TRUE GND
GNDTRUE
TRUE GND
GNDTRUE
83
66
83
83
83
59
83
83
59
47
47
79
47
45
83
83
83
83
90
57
90
83
83
83
83
83
47
47
47
83
83
83
47
59
83
83
83
47
47 76
86
88
88
88
88
88
47
23
59
23
23
46
66
23
83
83
14
28
30
28
46
46
83
88
30
54
47
47
47
47
47
28
46
40
88
88
86
88
83
45
80
14
14
14
14
79
46
79
14
14
14
14
14
45
45
45
14
14
14
47
45
49
49
60
49
14
14
14
57
91
82
82
82
47
46
47
47
91
91
91
46
47
47
49
80
80
30
30
29
30
30
30
68
28
46
13
25
10
16
66
45
45
10
25
25
14
14
13
16
28
29
28
25
28
54
45
45
57
80
23
30
91
91
45
29
45
45
46
45
45
46
45
24
45
36
45
30
47
91
80
47
47
59
83
30
52
59
67
67
57
28
46
76
76
74
74
74
10
10
10
10
75
45
52
75
16
16
10
16
10
10
10
10
25
23
23
10
10
10
10
52
24
23
45
8
8
8
10
10
10
48
44
44
81
81
9
82
8
45
45
45
51
51
51
51
51
51
45
45
25
8
8
24
16
14
16
16
88
23
22
22
88
28
16
44
45
10
16
7
66
10
36
25
25
7
16
16
10
10
10
9
25
25
23
9
24
34
25
43
52 48
46
10
14
44
44
28
25
25
34
45
25
23
47
45
23
52
9
43
25
25
10
30
44
24
8
28
45
59
10
8
12
57
57
57
8
25
45
28
Page 8
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
3.3V-2.5V Rails"G3Hot" (Always-Present) Rails 1.8V-0.9V Rails
"GPU" Rails
5V Rails
"FW" (FireWire) Rails
Chipset "VCore" Rails
MAX I = ?.??A
"ENET" Rails
MAX I = 0.36A
Yukon EC will not be supported
Power Aliases
051-7261 A.0.0
928
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
=PP3V3_S5_SB_USB=PPBUS_S5_FWPWRSW
MAKE_BASE=TRUEVOLTAGE=3.42VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPP3V42_G3H
=PPVIN_S0_P1V05S0
=PPVIN_S0_P1V5S0=PPBUS_S0_LCDBKLT
=PPVBATT_G3H_LIO_CONN
=PPBUS_S5_P1V25S0FET
VOLTAGE=12.6V
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mm
PPBUS_G3H
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
PP3V3_S5
MAKE_BASE=TRUE
=PP3V3_S5_SB_GPIO
=PPBUS_G3H_LIO_CONN=PPVIN_GPU_GPUVCORE
=PPVIN_S0_GFXIMVP6
=PPDCIN_G3H PPDCIN_G3HMIN_NECK_WIDTH=0.2 mmVOLTAGE=18.5V
MIN_LINE_WIDTH=0.4 mm
MAKE_BASE=TRUE=PPVIN_G3H_P3V42G3H
=PP3V42_G3H_REG
=PP3V42_G3H_SB_RTC
=PP3V42_G3H_PWRCTL
=PP3V3_S5_LPCPLUS=PP3V3_S5_SMC=PP3V42_G3H_LIDSWITCH=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_ACIN=PP3V42_G3H_SMCUSBMUX
=PPVIN_S5_SMCVREF
=PP5V_S5_PWRCTL
=PP3V3_S0_FAN_RT=PP3V3_S0_FAN_LT=PP3V3_S0_GPUTHMSNS=PP3V3_S0_CPUTHMSNS=PP3V3_S0_NBGFXCOREISNS
MAKE_BASE=TRUEVOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmPP1V05_S0
=PPVP_FW_P3V3FW
=PP3V3_GPU_VIDEOMUX=PP3V3_GPU_TMDS
=PP3V3_GPU_LVDS_DDC=PP3V3_GPU_DVI
=PP1V5_S0_NB_TVDAC=PP1V5_S0_CPUMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25mmMIN_LINE_WIDTH=0.6mm
VOLTAGE=1.5V
PP1V5_S0
=PP1V5_S0_LIO
=PP1V5_S0_REG
=PP1V5_S0_SB
=PP1V5_S0_SB_VCC1_5_A
=PP1V5_S0_SB_VCC1_5_A_ARX=PP1V5_S0_SB_VCC1_5_A_ATX
=PP1V5_S0_SB_VCC1_5_A_USB_CORE=PP1V5_S0_SB_VCCUSBPLL
VOLTAGE=1.8VMIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mmPP1V8_S3
PP1V8_S3_ISNSMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.8VMAKE_BASE=TRUE
=PP3V3_S5_SMBUS_SB_ME
=PP3V3_S5_REG
=PPVCORE_S0_NB_FOLLOW
=YUKON_EC_PP2V5_ENET
=PP3V3_S5_SB_3V3_VCCSUSHDA
=PP3V3_S0_FET
=PP3V3_S0_P3V3S0FET
=PPVIN_S5_CPU_IMVP_VIN
=PPVIN_ENET_P1V25ENET
=PP1V8_GPU_FBIO=PP1V8_GPU_FBVDDQ=PP1V8_GPU_FB_VDDQ=PP1V8_GPU_FB_VDD
=PP3V3_GPU_IFPCD_IOVDD
MIN_LINE_WIDTH=0.4 mm
MAKE_BASE=TRUE
PP3V3_GPU_TMDS
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mm
=PP3V3_GPU_HDCP=PP3V3_GPU_VCORELOGIC=PP3V3_GPU_PWRCTL
=PP2V5_GPU_LTC2900
=PP3V3_GPU_VGASYNC
MIN_NECK_WIDTH=0.2 mm
PP3V3_GPUMIN_LINE_WIDTH=0.4 mm
VOLTAGE=3.3VMAKE_BASE=TRUE
=PP1V8_FW_PHYOSC=PP1V95_FW_PHY
PP1V95_FWMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.95VMAKE_BASE=TRUE
=PPVIN_FW_P1V95FW=PP3V3_FW_LATEVG=PP3V3_FW_LATEVG_ACTIVE=PP3V3_FW_PHY
=PP1V25_S0_FET
PP3V3_ENET
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm
VOLTAGE=3.3V
=PP5V_S5_SB
=PP5V_S5_P1V05S0
=PP5V_S5_GPUVCORE
VOLTAGE=1.25V
PP1V25_S0MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
=PPVOUT_ENET_AVDDLDO
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUEVOLTAGE=1.25V
PP1V25_ENET
=PP5V_S5_REG
=PP1V25_ENET_ISNS
=PP3V3_GPU_SMBUS_SMC_0_S0
=PP1V2_GPU_PEX_PLLXVDD
=PP3V3_GPU_MIO=PP3V3_GPU_VDD33
=PPVP_FW_PORT0
=PPVP_FW_CPS
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.3 mmVOLTAGE=33V
PPVP_FW
=PP5V_S3_WWAN
=PP5V_S0_P5VS0FET=PP5V_S3_P5VS3FET
=PP5V_S5_P1V8GPUFET
=PP5V_S5_P1V25GPUFET=PP5V_S5_P1V8S0FET
=PP5V_S3_CAMERA
=PP5V_S5_P1V5S0
=PP5V_S0_CPU_IMVP
MAKE_BASE=TRUEPPBUS_FW_FWPWRSW_F =PPBU_S0_P3V3FW
=PP3V3_GPU_DAC
=PP3V3_FW_REG
PPVP_FW_PORTB_UFMAKE_BASE=TRUE
=PPVP_FW_PORT1
PPVP_FW_PORTA_UFMAKE_BASE=TRUE
=PPVP_FW_SUMNODE
=PPBUS_S5_FW_FET
MIN_LINE_WIDTH=0.4 mm
MAKE_BASE=TRUE
PP3V3_FWMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V
=PPVCORE_GPU_REG
=PP3V3_GPU_TMDSBIAS
=PP5V_S0_LCDBKLT
VOLTAGE=1.25V
MIN_LINE_WIDTH=0.6 mmPPVCORE_S0_CPUMIN_NECK_WIDTH=0.3 mm
MAKE_BASE=TRUE
=PP5V_S0_DVI_DDC
=PPVCORE_S0_NBGFX_REG
=PPVCORE_S0_NB_GFX
=PP5V_S3_IR=PP5V_S3_TOPCASE
=PP5V_S5_P1V25ENET
=PPVCORE_S0_CPU_REG
=PP1V2_GPU_PEX_IOVDD
=PP1V2_GPU_PLLVDD
=PP1V2_GPU_VID_PLLVDD
VOLTAGE=1.25V
PP1V25_GPUMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
=PP1V2_GPU_FBPLLAVDD
=PP1V25_GPU_P1V25GPUFET
=PP1V05_S0M_NB_VCCAXM
=PP1V05_S0_REG
=PP0V9_S3M_MEM_DIMMVREFB
=PP1V2_ENET_PHY
=PP1V8_S3_REG
=PP5V_S3_FET
=PPVCORE_S0_CPU
PPVCORE_S0_NB_GFXMIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUEVOLTAGE=1.25VMIN_NECK_WIDTH=0.25 mm
PP1V25_ENET_ISNS
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=1.25VMIN_NECK_WIDTH=0.2 mm
=PP1V25_S0_P1V25S0FET
=PP1V25_ENET_REG
=PP3V3_GPU_FET
=PP1V25_S0M_NB_PLL
=PP3V3_S5_SB_CLINK1=PP3V3_S5_SB
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S5_PWRCTL
=PP3V3_S0_SB_PCI
=PPVIN_S5_P5VP3V3
=PP5V_S0_FET
PP5V_S3MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUEVOLTAGE=5VMIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUEVOLTAGE=5V
PP5V_S5MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
=PP5V_S0_SB
=PP5V_S0_FAN_RT
=PP5V_S0_ISENSECAL=PP5V_S0_LPCPLUS
=PP5V_S0_HDD
MIN_LINE_WIDTH=0.6 mmPP5V_S0
VOLTAGE=5VMIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
=PP5V_S0_PCIREQFIX
=PP5V_S0_SB_HPD
=PP5V_S0_ODDPWREN
=PP5V_S0_FAN_LT
=PP5V_S0_GFXIMVP6
=PP3V3_S0_SB_VCC3_3_PCI=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S3_P3V3S3FET
=PP3V3_S5_SB_VCCSUS3_3_USB
=PP3V3_S0_LCD=PP3V3_GPU_P3V3GPUFET
=PP3V3_S3_RTALS
=PP3V3_S3_P1V8ISNS
=PP3V3_S3_TOPCASE=PP3V3_S3_BT=PP3V3_S3_SMS
=PP3V3_S5_P1V5P1V05PG=PP3V3_S5_ROM
=PP3V3_S5_S5PWRGD
=PP3V3_S5_SB_PM
=PP1V25_ENET_ISNS_R
=PP1V8R2V5_ENET_PHY
PP1V9_ENETMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.9VMAKE_BASE=TRUE
=PP3V3_ENET_PHY
=PP0V9_S0M_MEM_TERM
=PP0V9_S3M_MEM_DIMMVREFA
=PP1V05_S0_CPU
=PP1V25_S0_NB_VCC=PP1V25_S0_NB_PLL=PP1V25_S0_NB_VCCDMI=PP1V25_S0M_NB_VCCA=PP1V25_S0M_NB_VCC
=PP1V25_GPU_FET
=PPVCORE_GPU
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
PPVCORE_GPU
VOLTAGE=1.2VMAKE_BASE=TRUE
=PP1V2_GPU_VCOREPWRCTL
=PP1V2_GPU_H_PLLVDD
=PP1V2_GPU_PEX_IOVDDQ
=PP1V8_GPU_IFPX
PP1V8_GPU
VOLTAGE=1.8VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
=PP1V05_S0_NB_FOLLOW
=PP0V9_S3_VTTR_BUF
=PPVCORE_S0_NB_R
=PP0V9_S3M_MEM_NBVREFB
PPVCORE_S0_NB_RMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm
MAKE_BASE=TRUEVOLTAGE=0.9V
=PP1V25R1V05_S0_FSB_NB
=PP1V8_GPU_FET
=PP3V3_GPU_TMDS_FET
=PP1V95_FW_LDO
=PP3V3_S0_SB_VCC3_3_VCCPCORE
=PP3V3_S0_SMBUS_SMC_B_S0=PP3V3_S0_SMBUS_SB
=PP3V3_S0_SMC
=PP3V3_S0_RSTBUF=PP3V3_S0_SB_PM=PP3V3_S0_SB
=PP3V3_S0_SB_VCCGLAN3_3
=PP3V3_S0_SB_VCC3_3_DMI
=PP3V3_S0_SB_GPIO=PP3V3_S0_NB_FOLLOW=PP3V3_S0_NB_VCCA_PEG_BG=PP3V3_S0_NB_VCCHV
=PP3V3_S3_SMBUS_SMC_MGMT
=PPVIN_S5_CPU_IMVP
=PP1V25_S0_SB_DMI
=PP1V05_S0_NB_PCIE=PP1V05_S0_SB_CPU_IO=PP1V05_S0_SMC_LS
=PP1V25R1V05_S0_NB_VTT=PPVCORE_S0_NBCOREISNS
=PPVCORE_S0_SB
=PPVCORE_S0_NB
PP0V9_S3_MEM_VREFMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0.9VMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
PP0V9_S0
VOLTAGE=0.9V
=PP3V3_ENET_AVDDLDO
=PP0V9_S3M_MEM_NBVREFA
=PP0V9_S0_VTT_LDO
=PP1V8_S3M_MEM_NB
=PP5V_S5_P1V8DDRREG
=PP3V3_ENET_FET
=PPVIN_S5_P3V3S5=PPVIN_S5_P5VS5
=PP1V8_S3_FW=PP1V8_S3M_MEM_A=PP1V8_S3M_MEM_B=PP1V8_S3_ISNS_R=PP1V8_GPU_P1V8GPUFET=PP1V8_S0_P1V8S0FET
=PP1V8_S3_ISNS
=PPBUS_S5_P1V8GPUFET
=PP1V8_S0_NB_LVDS
=PP1V8_S3M_NB_VCC
=PPVIN_S3_P1V8S3
=PPVBAT_G3H_CHGR_REG
=PPVIN_S0_NB_DPLL
PP1V8_S0
MAKE_BASE=TRUEVOLTAGE=1.8VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm
=PP1V8_S0_FET
=PP5V_S5_P1V25S0FET
=PP5V_S3_RTUSB
=PP5V_S0_ODD
=PP5V_S0_KBDLED
=PPVCORE_S0_NBGFX_VSEN
=PP3V3_S0_SB_VCC3_3_SATA
=PP3V3R1V5_S0_SB_VCCHDA
=PP3V3_S3_P1V25ISNS
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_FET
=PP5V_S3_SYSLED
=PP3V3_S3_REMTHMSNS
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
PP3V3_S3
VOLTAGE=3.3V
=PP3V3_S3_PCI=PP3V3_S3_FW=PP3V3_S3_P3V3ENETFET
=PP3V3_S0_NBCOREISNS=PP3V3_S0_ALLSYSPG
=PP3V3_S0_LVDS_MUX=PP3V3R5V_GPU_GPUISENS
=PPSPD_S0M_MEM_A=PP3V3_S0_GPUCLKGATE
=PPSPD_S0M_MEM_B=PP3V3_S0MWOL_SB_CLINK0=PP3V3_S0MWOL_SB_VCCCL3_3=PP3V3_S0MWOL_SB_VCCLAN3_3=PP3V3_S0_PBATTISENS=PP3V3_S0_PDCISENS
=PP3V3_S0_PWRCTL=PP3V3_S0_TMPSNSR
=PP3V3_S0_CK505=PP3V3_S0_IDE
=PP3V3_S0_LPCPLUS
=PP3V3_S0_CPUCOREISNS
=PP3V3_S0_IMVP=PP3V3_S0_GFXIMVP6
=PP3V3_S0_DDC_LCD=PP3V3_S0_LCDBKLT
=PP3V3_S0_XDP=PP3V3_S0M_CK505
PP3V3_S0MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3VMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mm
13
76
59
49
12
21
27
22
21
57
47
46
67
12
27
27
27
27
27
72
72
41
74
49
60
22
80
49
21
12
27
27
49
47
52
27
27
27
11
21
30
27
25
21
19
27
26
21
27
21
18
91
91
58
27
27
27
27
30
30
91
24
40
62
64
82
67
58
49 91
25
7
76
60
57
66
66
28
66
7
45
80
48
57
43
46
66
52
52
51
51
50
65
74
74
79
78
22
11
91
34
64
27
26
26
26
26
26
48
61
21
35
26
58
58
59
62
70
69
71
71
75
74
76
66
79
78
79
39
39
65
41
40
39
58
27
62
76
66
36
61
50
48
68
73
73
41
39
44
58
58
58
58
58
44
64
59
40 65
75
65
40 41
40
40
40
7
78
81
78
7
18
7
80
62
7
68
73
73
79
70
58
18
62
32
35
63
58
11
58
62
58
21
25
25
26
66
24
61
58
27
52
7
7
80
66
42
78
42
7
60
26
26
58
26
77
58
54
50
80
80
55
66
56
46
28
50
35
35
33
31
10
21
21
19
21
21
58
69
76
73
68
75
79
21
63
50
16
14
58
74
65
26
48
48
46
28
28
27
26
26
23
21
19
16
48
59
26
21
23
46
19
50
26
18
36
16
63
16
63
36
61
61
38
31
32
50
9
58
50
58
22
21
63
67
22
66 58
58
43
42
54
60
26
26
50
48
58
46
51
38
38
36
50
66
79
76
31
30
32
25
26
26
53
53
66
53
29
42
47
50
59
60
77
81
13
29
66
Page 9
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
Stuff either R7520 or R0980.
Q7080 pin 5Place next to
Thermal Module HolesTop Right GPU
Chassis connection to be made at the mounting hole east of the LVDS connector
All holes are plated through holes with two exceptions:
GND_CHASSIS_RIGHT_FAN_NOTCH (to the left of small well on lower board edge near USB)
GND_CHASSIS_BATTCONN_HOLE (to the left of DIMM cutout near board edge)
Bottom Left GPU
Chassis GNDs
TM Hole
TM Hole
TM Hole
Frame holes
Right CPULeft CPU
Add 8 blind vias per side to GND
Top CPU TM "Hole"
RAM door (Torx) holes
Digital Ground
TM Hole
195R106
OMIT
195R106
OMIT
235R126
OMIT
235R126
OMIT
SHLD-SM-LFOG-503040
195R106
OMIT
195R106OMIT
OMIT
195R106
195R106
OMIT
195R106
OMIT
195R106
OMIT
SM
402MF-LF1/16W
P1V8S3_1V825_GPUFB
0.1%21.5K
RES,MTL FILM,21K,0.1,0402,SM,LF103S0192 CRITICAL1 R7580 P1V8S3_1V8_GPUFB
051-7261 A.0.0
929
SYNC_MASTER=(T9_MLB)
Signal AliasesSYNC_DATE=08/23/2006
=GND_BATT_CHGNDMAKE_BASE=TRUEGND_CHASSIS_BATTCONN_HOLE
VOLTAGE=0V
MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mm
GND_CHASSIS_BATTCONN_HOLE
VOLTAGE=0V
MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mm
GND_CHASSIS_DIMM_NOTCH
VOLTAGE=0V
MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mm
GND_CHASSIS_LIOFLEX_HOLE
VOLTAGE=0V
MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mm
GND_CHASSIS_LNDACARD_HOLE
GND_CHASSIS_RAMDOOR_HOLE_0MIN_NECK_WIDTH=0.25mmMIN_LINE_WIDTH=0.6mm
VOLTAGE=0V
GND_CHASSIS_RAMDOOR_HOLE_1MIN_NECK_WIDTH=0.25mmMIN_LINE_WIDTH=0.6mm
VOLTAGE=0V
VOLTAGE=0V
MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mm
GND_CHASSIS_RIGHT_FAN_HOLE
VOLTAGE=0V
MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mm
GND_CHASSIS_RIGHT_FAN_NOTCH
PLT_RESET_L
PBUS_LDO_EN
=GND_CHASSIS_ENET
=GND_CHASSIS_FW_PORT0U
MAKE_BASE=TRUEPEG_CLK100M_GPU_N
MAKE_BASE=TRUEGFX_VR_EN
PM_ALL_NBGFX_PGOODMAKE_BASE=TRUE
SMC_ENRGYSTR_LDO_EN
PEG_CLK100M_GPU_PMAKE_BASE=TRUE
=SMC_SMS_INT
PLT_RST_L
=GND_CHASSIS_RTUSB
SMC_SMS_INTMAKE_BASE=TRUE
=SB_CLINK_MPWROK
=NB_CLINK_MPWROK
MEM_A_A<15>
MEM_B_A<15>
TP_MEM_A_A<15>MAKE_BASE=TRUE
=GND_CHASSIS_INVERTER
PEG_CLK100M_P
PEG_CLK100M_N
VR_PWRGOOD_DELAYMAKE_BASE=TRUE
PM_SB_PWROKMAKE_BASE=TRUE
GFXIMVP6_VID<4..0>MAKE_BASE=TRUE
GND_CHASSIS_RTIOMIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUEVOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
=GND_CHASSIS_DVI_TOP
=GND_CHASSIS_LEFTCLUTCH=GND_CHASSIS_J5590
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=0VMAKE_BASE=TRUE
GND_CHASSIS_INVERTERMIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mm
GND_CHASSIS_LVDS
MAKE_BASE=TRUE
=PP1V8_GPU_P1V8GPUFET
P1V8GPU_FBVOLTAGE=1.8V
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
=GND_CHASSIS_FW_PORT0L
=GND_CHASSIS_DVI_BOT
=GND_CHASSIS_FW_PORT1
TP_MEM_B_A<15>MAKE_BASE=TRUE
GFX_VID<4..0>
GFXIMVP6_PGOOD
=GFX_VR_EN
P1V8S3_FB
VOLTAGE=0V
MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mm
GND
ZT09551
ZT09651
ZT0930
ZT09351
SH09251
2
3
ZT09001
ZT09011
ZT09851
ZT09751
ZT09701
ZT09801
XW0980
1
2
R09801
279
59
28
28
28
68
68
24
82
16
25
80
58
67 9
9
81
67
37
41
30
60
79
46
30
45
7
43
55
25
16
31
32
7
88
88
7
7
60
78
44
51
8
41
78
41
16
60
16
63
Page 10
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
OUT
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
BI
BI
BI
BI
LOCK*
INIT*
A20M*
A6*
A3*
A4*
A14*
A16*
REQ0*
REQ1*
REQ2*
REQ3*
REQ4*
BCLK1
BCLK0
THERMTRIP*
THERMDA
PROCHOT*
DBR*
TRST*
TMS
TDO
TDI
TCK
PREQ*
PRDY*
BPM3*
BPM2*
BPM1*
BPM0*
HITM*
HIT*
TRDY*
RS2*
RS1*
RS0*
RESET*
IERR*
BR0*
DBSY*
DRDY*
DEFER*
BNR*
RSVD9
RSVD8
RSVD7
RSVD6
RSVD5
RSVD4
RSVD3
RSVD2
RSVD1
RSVD0
SMI*
LINT1
LINT0
STPCLK*
FERR*
ADSTB1*
A35*
A34*
A33*
A32*
A31*
A30*
A29*
A28*
A19*
A18*
A17*
ADSTB0*
A13*
A12*
BPRI*
A20*
A21*
A22*
A23*
A24*
A26*
A27*
A9*
A8*
A7*
A11*
A25*
THERMDC
IGNNE*
ADS*
A10*
A15*
A5*
NC
1 OF 4
CONTROL
THERMAL
XDP/ITP SIGNALS
H CLK
RESERVED
ADDR GROUP0
ADDR GROUP1
ICH
DINV1*
D31*
D30*
D25*
D11*
D12*
D13*
D14*
DSTBP0*
DINV0*
D9*
D8*
D7*
D6*
D19*
D18*
DATBP1*
D0* D32*
D1*
D2*
D5*
D16*
D20*
D21*
D22*
D23*
D24*
D26*
D27*
D28*
D29*
DSTBN1*
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
BSEL0
BSEL1
BSEL2
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2*
DSTBP2*
DINV2*
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3*
DSTBP3*
DINV3*
COMP0
COMP1
COMP2
COMP3
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
D17*
D4*
D3*
DSTBN0*
D15*
D10*
2 OF 4
DATA GRP 3
DATA GRP 2
MISC
DATA GRP 0
DATA GRP 1
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
PIN. MAKE SURE CPU_TEST4 ISPLACE C1000 CLOSE TO CPU_TEST4
REFERENCED TO GND
0.5" MAX LENGTH FOR CPU_GTLREF
FSB_IERR_L WITH A GNDPLACE TESTPOINT ON
0.1" AWAY
GMCH WITHOUT T (NO STUB)SHOULD CONNECT TO ICH ANDPM_THRMTRIP#
COMP1,3 CONNECT WITH ZO=55OHM,MAKE TRACE LENGTH SHORTER THAN 0.5".
COMP0,2 CONNECT WITH ZO=27.4OHM,MAKE TRACE LENGTH SHORTER THAN 0.5".
LAYOUT NOTE:
NC
402MF-LF
54.91/16W1%
MF-LF402
1/16W5%68
402
1K
MF-LF
1%1/16W
402
1/16W
2.0K
MF-LF
1%
402
54.9
1/16WMF-LF
1%
402
1%
MF-LF1/16W
27.4402
54.9
1/16WMF-LF
1%
402
27.4
1/16WMF-LF
1%
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 16 23 59 83
7 23 83
7 14 83
7 14 83
28
7 13 23 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
30 83
30 83
30 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
14 83
14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
7 14 83
13 83
13 83
13 83
13 83
13 83
13 83
10 13 83
13 28
46 59 83
51
16 23 46 83
23 47 83
7 13 14 83
14 83
14 83
14 83
14 83
10 13 83
10 13 83
10 13 83
10 13 83
51 91
7 30 88
7 30 88
23 83
23 83
23 83
23 83
7 23 83
23 83
23 83
402
NOSTUFF
5%
MF-LF1/16W
0
402
NOSTUFF
1K
MF-LF
5%1/16W
402
54.9
MF-LF
1%1/16W
402
54.9
1/16WMF-LF
1%
402
1%
MF-LF1/16W
54.9
402
1%
MF-LF1/16W
54.9
14 83
14 83
14 83
14 83
402
1%
MF-LF1/16W
649402
MF-LF
NOSTUFF
1K5%
1/16W
402
16V10%0.1uF
NOSTUFF
X5R
FCBGAMEROM
OMIT
FCBGAMEROM
OMIT
402
PLACEMENT_NOTE=Place R1024 near ITP connector (if present)
54.9
1/16WMF-LF
1%
CPU FSB
10
A.0.0051-7261
92
SYNC_MASTER=T9_NOME SYNC_DATE=01/25/2007
TP_CPU_TEST5
FSB_DINV_L<1>
FSB_D_L<31>FSB_D_L<30>
FSB_D_L<25>
FSB_D_L<11>FSB_D_L<12>FSB_D_L<13>FSB_D_L<14>
FSB_DSTB_L_P<0>FSB_DINV_L<0>
FSB_D_L<9>FSB_D_L<8>FSB_D_L<7>FSB_D_L<6>
FSB_D_L<19>FSB_D_L<18>
FSB_DSTB_L_P<1>
FSB_D_L<0> FSB_D_L<32>FSB_D_L<1>FSB_D_L<2>
FSB_D_L<5>
FSB_D_L<16>
FSB_D_L<20>FSB_D_L<21>FSB_D_L<22>FSB_D_L<23>FSB_D_L<24>
FSB_D_L<26>FSB_D_L<27>FSB_D_L<28>FSB_D_L<29>
FSB_DSTB_L_N<1>
CPU_GTLREFCPU_TEST1CPU_TEST2TP_CPU_TEST3CPU_TEST4
TP_CPU_TEST6
CPU_BSEL<0>CPU_BSEL<1>CPU_BSEL<2>
FSB_D_L<33>FSB_D_L<34>FSB_D_L<35>FSB_D_L<36>FSB_D_L<37>FSB_D_L<38>FSB_D_L<39>FSB_D_L<40>FSB_D_L<41>FSB_D_L<42>FSB_D_L<43>FSB_D_L<44>FSB_D_L<45>FSB_D_L<46>FSB_D_L<47>FSB_DSTB_L_N<2>FSB_DSTB_L_P<2>FSB_DINV_L<2>
FSB_D_L<48>FSB_D_L<49>FSB_D_L<50>FSB_D_L<51>FSB_D_L<52>FSB_D_L<53>FSB_D_L<54>FSB_D_L<55>FSB_D_L<56>FSB_D_L<57>FSB_D_L<58>FSB_D_L<59>FSB_D_L<60>FSB_D_L<61>FSB_D_L<62>FSB_D_L<63>FSB_DSTB_L_N<3>FSB_DSTB_L_P<3>FSB_DINV_L<3>
CPU_COMP<0>CPU_COMP<1>CPU_COMP<2>CPU_COMP<3>
CPU_DPRSTP_LCPU_DPSLP_LFSB_DPWR_LCPU_PWRGDFSB_CPUSLP_LCPU_PSI_L
FSB_D_L<17>
FSB_D_L<4>FSB_D_L<3>
FSB_DSTB_L_N<0>FSB_D_L<15>
FSB_D_L<10>
FSB_LOCK_L
CPU_INIT_L
CPU_A20M_L
FSB_A_L<6>
FSB_A_L<3>FSB_A_L<4>
FSB_A_L<14>
FSB_A_L<16>
FSB_REQ_L<0>FSB_REQ_L<1>FSB_REQ_L<2>FSB_REQ_L<3>FSB_REQ_L<4>
FSB_CLK_CPU_NFSB_CLK_CPU_P
PM_THRMTRIP_L
CPU_THERMD_PCPU_PROCHOT_L
XDP_DBRESET_LXDP_TRST_LXDP_TMSXDP_TDOXDP_TDI
XDP_BPM_L<4>XDP_BPM_L<3>
XDP_BPM_L<1>XDP_BPM_L<0>
FSB_HITM_LFSB_HIT_L
FSB_TRDY_LFSB_RS_L<2>FSB_RS_L<1>FSB_RS_L<0>FSB_CPURST_L
CPU_IERR_L
FSB_BREQ0_L
FSB_DBSY_LFSB_DRDY_LFSB_DEFER_L
FSB_BNR_L
TP_CPU_RSVD9TP_CPU_RSVD8TP_CPU_RSVD7TP_CPU_RSVD6TP_CPU_RSVD5TP_CPU_RSVD4TP_CPU_RSVD3TP_CPU_RSVD2TP_CPU_RSVD1TP_CPU_RSVD0
CPU_SMI_LCPU_NMICPU_INTRCPU_STPCLK_L
CPU_FERR_L
FSB_ADSTB_L<1>FSB_A_L<35>FSB_A_L<34>FSB_A_L<33>FSB_A_L<32>FSB_A_L<31>FSB_A_L<30>FSB_A_L<29>FSB_A_L<28>
FSB_A_L<19>FSB_A_L<18>FSB_A_L<17>
FSB_ADSTB_L<0>
FSB_A_L<13>FSB_A_L<12>
FSB_BPRI_L
FSB_A_L<20>FSB_A_L<21>FSB_A_L<22>FSB_A_L<23>FSB_A_L<24>
FSB_A_L<26>FSB_A_L<27>
FSB_A_L<9>FSB_A_L<8>FSB_A_L<7>
FSB_A_L<11>
FSB_A_L<25>
CPU_IGNNE_L
FSB_ADS_L
FSB_A_L<10>
FSB_A_L<15>
FSB_A_L<5>
XDP_TCK
XDP_TDO
XDP_TMS
XDP_TDI
XDP_TRST_L
=PP1V05_S0_CPU
=PP1V05_S0_CPU
=PP1V05_S0_CPU
=PP1V05_S0_CPU
CPU_THERMD_N
XDP_TCKXDP_BPM_L<5>
XDP_BPM_L<2>
R10021
2
R10041
2
R10051
2
R10061
2
R1019
R1018
R1017
R1016
R1030
R10071
2
R10031
2
R1020
R1021
R1022
R1023R10121
2
C10001
2
U1000
N3
P5
P2
L2
P4
P1
R1
Y2
U5
R3
W6
A6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
J4
U2
V4
W3
AA4
AB2
AA3
L5
L4
K5
M3
N2
J1
H1
M1
V1
A22
A21
E2
AD4
AD3
AD1
AC4
G5
F1
C20
E1
H5
F21
A5
G6
E4
D20
C4
B3
C6
B4
H4
B1
AC2
AC1
D21
K3
H2
K2
J3
L1
C1
F3
F4
G3
M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
A3
D5
AC5
AA6
AB3
A24
B25
C7
AB5
G2
AB6
U1000
B22
B23
C21
R26
U26
AA1
Y1
E22
F24
J24
J23
H22
F26
K22
H23
N22
K25
P26
R23
E26
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
G22
T25
N25
Y22
AB24
V24
V26
V23
T22
U25
U23
F23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
AE24
AD24
G25
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
E25
AC22
AD23
AF22
AC23
E23
K24
G24
M26
H25
N24
U22
AC20
E5
B5
D24
J26
L26
Y26
AE25
H26 AA26
AF24
AD26
AE6
D6
D7
C23
D25
C24
AF26
AF1
A26
R1024
13
13
13
13
12
12
12
12
83
83
83
83
83
11
11
11
11
13
13
13
13
13
10
10
10
10
83 83
83
83
83
83
7
10
10
10
10
10
8
8
8
8
Page 11
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
VCC
VSSSENSE
VCCSENSE
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCCA
VCCP
VCC
3 OF 4
VSS VSS
4 OF 4
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
11.5 A (Deeper Sleep)
25.0 A (Deep Sleep HFM)
27.4 A (Sleep HFM)
17.0 A (Auto-Halt/Stop-Grant SuperLFM)27.4 A (Auto-Halt/Stop-Grant HFM)
30.4 A (LFM)25.5 A (SuperLFM)
9.4 A (Enhanced Deeper Sleep)
2500 mA (after VCC stable) 4500 mA (before VCC stable)
16.0 A (Deep Sleep SuperLFM)
16.8 A (Sleep SuperLFM)
41.0 A (HFM)
44.0 A (Design Target)
Standard Voltage:
(CPU CORE POWER)
130 mA
(CPU IO POWER 1.05V)
(CPU INTERNAL PLL POWER 1.5V)
Low Voltage: Ultra Low Voltage:17.0 A (Design Target)23.0 A (Design Target)
21.0 A (HFM)18.7 A (LFM)TBD A (SuperLFM)
TBD A (Auto-Halt/Stop-Grant HFM)TBD A (Auto-Halt/Stop-Grant SuperLFM)
TBD A (Sleep HFM)TBD A (Sleep SuperLFM)
TBD A (Deep Sleep HFM)TBD A (Deep Sleep SuperLFM)
TBD A (Deeper Sleep)
TBD A (Enhanced Deeper Sleep) TBD A (Enhanced Deeper Sleep)
TBD A (Deeper Sleep)
TBD A (Deep Sleep HFM)
TBD A (Sleep HFM)
TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (HFM)TBD A (LFM)
Current numbers from Merom for Santa Rosa EMTS, doc #22221.
TBD A (Auto-Halt/Stop-Grant LFM)
TBD A (Sleep LFM)
TBD A (Deep Sleep LFM)
12 83
12 83
12 83
12 83
12 83
12 83
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
MF-LF402
1001%1/16W
12 83
59 83
59 83
FCBGAMEROM
OMIT
FCBGAMEROM
OMIT
MF-LF402
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
1/16W1%100
SYNC_DATE=01/25/2007SYNC_MASTER=T9_NOME
CPU Power & Ground
051-7261 A.0.0
11 92
=PP1V05_S0_CPU
=PP1V5_S0_CPU
CPU_VID<4>
CPU_VID<6>
=PPVCORE_S0_CPU
CPU_VID<1>CPU_VID<0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
=PPVCORE_S0_CPU
CPU_VID<5>
CPU_VID<3>CPU_VID<2>
R11011
2
U1000
A7
A9
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
A10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
A12
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
A13
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
A15
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
A17
AC10
AB10
AB12
AB14
AB15
AB17
AB18
AB20
AB7
AC7
A18
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
A20
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
B7
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
B26
C26
G21
V6
R21
R6
T21
T6
V21
W21
J6
K6
M6
J21
K21
M21
N21
N6
AF7
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AE7
U1000
A4
A8
B11
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
B13
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
B16
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
B19
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
B21
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
B24
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
C5
AF21
A25
AF25
C8
C11
C14
A11
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
A14
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
A16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
A19
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
A23
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
AF2
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
B6
P3
P6
P21
P24
R2
R5
R22
R25
T1
T4
B8 T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
R11001
2
13
49
49
12
12
12
10
12
11
11
8
8
8
8
Page 12
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
WF: Consider sharing bulk cap with NB Vtt?
VCCA (CPU AVdd) DECOUPLING1x 10uF, 1x 0.01uF
VCCP (CPU I/O) DECOUPLING1x 470uF, 6x 0.1uF 0402
CPU VCORE HF AND BULK DECOUPLINGCPU VCORE VID CONNECTIONS4x 330uF, 20x 22uF 0805
CERM-X5R805
6.3V20%22UF
CRITICAL
2.5VTANTD2T
20%470UF
CERM-X5R805
6.3V20%22UF
20%6.3V
805CERM-X5R
22UF20%6.3V
805CERM-X5R
22UF
CERM-X5R805
6.3V20%22UF
CERM-X5R805
6.3V20%22UF
CERM-X5R805
6.3V20%22UF
CERM-X5R805
20%22UF6.3V
CERM-X5R805
6.3V20%22UF
20%6.3V
805CERM-X5R
22UF6.3V
805
20%
CERM-X5R
22UF20%6.3V
805CERM-X5R
22UF
805
6.3V20%
CERM-X5R
22UF
CERM-X5R
22UF6.3V
805
20%
805
6.3V20%
CERM-X5R
22UF
0.1UF20%
CERM402
10V
CERM-X5R805
6.3V20%22UF
CERM-X5R805
6.3V20%22UF
20%6.3V
805CERM-X5R
22UF20%6.3V
805CERM-X5R
22UF
20%
CERM402
0.1UF10V
20%
CERM402
0.1UF10V
20%
CERM402
0.1UF10V
20%
CERM402
0.1UF10V
20%
CERM402
0.1UF10V
6.3V
805
20%
CERM-X5R
22UF
PLACEMENT_NOTE=Place near CPU pin B26.
CERM402
16V10%0.01UF
X5R6.3V20%
10uF
603
10%2.0V
330UF
TANTD2T
PLACEMENT_NOTE=Place in CPU center cavity.
CRITICAL
10%2.0V
330UF
CRITICAL
TANTD2T
PLACEMENT_NOTE=Place in CPU center cavity.
2.0V
330UF
CRITICAL
TANTD2T
10%
PLACEMENT_NOTE=Place in CPU center cavity.
2.0V
330UF10%
TANTD2T
CRITICAL
PLACEMENT_NOTE=Place in CPU center cavity.
CPU Decoupling & VIDSYNC_MASTER=M75_MLB
9212
A.0.0
SYNC_DATE=12/07/2006
051-7261
=PPVCORE_S0_CPU
CPU_VID<0..6>MAKE_BASE=TRUE
IMVP6_VID<0..6>
=PP1V5_S0_CPU
=PP1V05_S0_CPU
C12081
2
C12071
2
C12191
2
C12181
2
C12061
2
C12041
2
C12161
2
C12141
2
C12031
2
C12021
2
C12011
2
C12131
2
C12121
2
C12111
2
C12001
2
C12101
2
C12361
2
C12051
2
C12091
2
C12151
2
C12171
2
C12371
2
C12381
2
C12391
2
C12401
2
C12411
2
C12811
2
C1280 1
2
C1250 1
2 3
C1251 1
2 3
C1252 1
2 3
C1253 1
2 3
C1235 1
2 3
13
49
83
11
11
83 59
11
10
8
11 7
8
8
Page 13
IN
BI
BI
OUT
OUT
IN
BI
IN
IN
IN
OUT
IN
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
IN
BI
IN
IN
IN
IN
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
SB OC[6]#
NOTE: This is not the standard XDP pinout.
OBSDATA_A2
PWRGD/HOOK0
Direction of XDP modulePlease avoid any obstructionson even-numbered side of J1300
ITPCLK/HOOK4
OBSDATA_D2
XDP_PRESENT#
OBSDATA_A0
OBSFN_A0
OBSDATA_B2OBSDATA_B3
OBSDATA_A3
OBSDATA_D0OBSDATA_D1
TMS
HOOK1VCC_OBS_AB
HOOK2HOOK3
TRSTn
OBSFN_A1
OBSDATA_A1
OBSDATA_B1
SDASCL
TCK1
SB OC[7]#
SB OC[5]#
SB OC[2]#
SB OC[1]#
OBSDATA_C3
SB OC[0]#
DBR#/HOOK7RESET#/HOOK6
ITPCLK#/HOOK5
TDI
TDO
OBSDATA_C2
OBSDATA_C0
OBSFN_C1
NC
(OBSDATA_A3)
TCK0
(OBSDATA_A2)
SB OC[4]#
NB CFG[2]NB CFG[0]NB CFG[1]
NB CFG[4]NB CFG[5]
NB CFG[6]NB CFG[7]
NB CFG[3]
NB CFG[8]SB GPIO[8]
OBSDATA_D3
(VCC_OBS_CD)
Mini-XDP Connector
Use with 920-0451 adapter board to support CPU, NB & SB debugging.
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
OBSFN_C0
SB OC[3]#
OBSDATA_C1
(OBSDATA_A0)(OBSDATA_A1)
OBSDATA_B0
998-1571
7 10 23 83
402MF-LF1/16W5%
1K
XDP
15
15
XDP
1/16W
402MF-LF
1%54.9
402
16V10%
0.1uF
X5R
XDP
MF-LF
10K5%
XDP
1/16W
402402MF-LF
10K5%
1/16W
XDP
402
16V10%0.1uF
X5R
XDP
10 28
10 83
10 83
10 83
10 83
10 83
10 83
10 83
7 10 14 83
10 83
10 83
10 83
10 83
30 83 88
30 83 88
24 34
24
24 79
24
24 36
24
24
24 43
1/16W
402MF-LF
5%
1K
XDP
LTH-030-01-G-D-NOPEGS
CRITICAL
F-ST-SM
XDP_CONN
16 30 83
16 30 83
16
16
16
16
25 45
16
16 30 83
16
eXtended Debug Port (XDP)SYNC_DATE=01/22/2007SYNC_MASTER=T9_NOME
13
A.0.0
92
051-7261
NB_CFG<6>
NB_CFG<5>NB_CFG<4>
LVDS_CTRL_DATA
XDP_BPM_L<1>
LVDS_CTRL_CLK
XDP_BPM_L<4>XDP_BPM_L<5>
SB_GPIO40
USB_EXTD_OC_L
EXTGPU_LVDS_EN
XDP_DBRESET_L
XDP_TDI
XDP_CLK_N
=PP1V05_S0_CPU
NB_CFG<3>NB_BSEL<2>
CPU_PWRGD XDP_PWRGD
NB_CFG<7>
NB_BSEL<1>NB_BSEL<0>
XDP_BPM_L<0>
XDP_BPM_L<2>
XDP_OBS20
WOW_EN
TP_XDP_HOOK2
USB_EXTB_OC_L
XDP_CLK_P
SB_GPIO30
USB_EXTA_OC_L
TP_XDP_HOOK3
XDP_BPM_L<3>
XDP_TCK
XDP_TRST_LXDP_TDO
FSB_CPURST_L
PM_LATRIGGER_L
XDP_CPURST_L
XDP_TMS
NB_CFG<8>SMC_WAKE_SCI_L
=PP3V3_S0_XDP
R13991 2
R13151
2
C1300 1
2
R13311
2
R13301
2
C13011
2
R13031 2
J1300
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
4142
4344
4546
4748
49
5
50
5152
5354
5556
5758
59
6
60
78
9
12 11 10 8
83
8
Page 14
BI
BI
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OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
H_D0*
H_D3*
H_D2*
H_D33*
H_D34*
H_D35*
H_D1*
H_D4*
H_D10*
H_A4*
H_A5*
H_A6*
H_A7*
H_A8*
H_A9*
H_A10*
H_A11*
H_A12*
H_A13*
H_A14*
H_A15*
H_A16*
H_A17*
H_A18*
H_A19*
H_A20*
H_A21*
H_A22*
H_A23*
H_A24*
H_A25*
H_A26*
H_A27*
H_A28*
H_A29*
H_A30*
H_A31*
H_A32*
H_A33*
H_A34*
H_A35*
H_ADS*
H_ADSTB0*
H_ADSTB1*
H_A3*
H_D7*
H_D8*
H_D9*
H_D11*
H_D12*
H_D13*
H_D14*
H_D15*
H_D16*
H_D17*
H_D18*
H_D19*
H_D20*
H_D21*
H_D22*
H_D23*
H_D25*
H_D26*
H_D27*
H_D28*
H_D29*
H_D30*
H_D32*
H_D36*
H_D37* H_BNR*
H_D38* H_BPRI*
H_D39*
H_D40* H_DEFER*
H_D41* H_DBSY*
H_D42*
H_D43*
H_D44* H_DPWR*
H_D45* H_DRDY*
H_D46* H_HIT*
H_D47* H_HITM*
H_D48* H_LOCK*
H_TRDY*
H_D51*
H_D52*
H_D53*H_DINV0*
H_D54*H_DINV1*
H_D55*H_DINV2*
H_D56*H_DINV3*
H_D57*
H_D58*H_DSTBN0*
H_D59*H_DSTBN1*
H_D60*H_DSTBN2*
H_D61*H_DSTBN3*
H_D62*
H_D63* H_DSTBP0*
H_DSTBP1*
H_DSTBP2*
H_SWING
H_RCOMP
H_REQ0*
H_SCOMP H_REQ1*
H_SCOMP* H_REQ2*
H_REQ3*
H_CPURST* H_REQ4*
H_CPUSLP*
H_RS0*
H_RS1*
H_AVREF H_RS2*
H_DVREF
H_D5*
H_D6*
H_D31*
H_BREQ*
H_D24*
H_D49*
H_D50*
H_DSTBP3*
HPLL_CLK
HPLL_CLK*
HOST
(1 OF 10)
BI
BI
BI
BI
BI
IN
IN
IN
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
7 10 83
7 10 83
7 10 83
10 83
10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
X5R
0.1uF10%16V
402
2.0K
MF-LF
1%1/16W
402
1K
MF-LF
1%1/16W
402
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
10 83
7 10 83
10 83
10 83
10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
54.9
MF-LF
1%1/16W
402
24.9
MF-LF
1%1/16W
402
221
MF-LF
1%1/16W
402
100
MF-LF
1%1/16W
402 X5R
0.1uF10%16V
402
7 10 83
OMIT
CRESTLINEFCBGA
10 83
10 83
10 83
10 83
7 10 83
54.9
MF-LF
1%1/16W
402
7 10 83
7 30 88
7 30 88
7 10 13 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
7 10 83
SYNC_DATE=01/25/2007
NB CPU Interface
051-7261 A.0.0
9214
SYNC_MASTER=T9_NOME
FSB_RS_L<2>
FSB_RS_L<0>FSB_RS_L<1>
FSB_REQ_L<4>FSB_REQ_L<3>FSB_REQ_L<2>FSB_REQ_L<1>FSB_REQ_L<0>
FSB_DSTB_L_P<3>FSB_DSTB_L_P<2>FSB_DSTB_L_P<1>FSB_DSTB_L_P<0>
FSB_DSTB_L_N<3>FSB_DSTB_L_N<2>FSB_DSTB_L_N<1>FSB_DSTB_L_N<0>
FSB_DINV_L<3>FSB_DINV_L<2>FSB_DINV_L<1>FSB_DINV_L<0>
FSB_LOCK_LFSB_TRDY_L
FSB_HITM_LFSB_HIT_LFSB_DRDY_L
FSB_CLK_NB_NFSB_CLK_NB_P
FSB_DPWR_L
FSB_DBSY_LFSB_DEFER_LFSB_BREQ0_L
FSB_BNR_LFSB_BPRI_L
FSB_ADSTB_L<1>FSB_ADSTB_L<0>FSB_ADS_L
FSB_A_L<35>FSB_A_L<34>FSB_A_L<33>
FSB_A_L<31>FSB_A_L<30>
FSB_A_L<32>
FSB_A_L<29>FSB_A_L<28>FSB_A_L<27>FSB_A_L<26>FSB_A_L<25>FSB_A_L<24>FSB_A_L<23>FSB_A_L<22>FSB_A_L<21>FSB_A_L<20>FSB_A_L<19>FSB_A_L<18>FSB_A_L<17>FSB_A_L<16>FSB_A_L<15>FSB_A_L<14>FSB_A_L<13>FSB_A_L<12>
FSB_A_L<10>FSB_A_L<11>
FSB_A_L<9>FSB_A_L<8>FSB_A_L<7>
FSB_A_L<5>FSB_A_L<4>
FSB_A_L<6>
FSB_A_L<3>
NB_FSB_VREF
NB_FSB_RCOMPNB_FSB_SWING
FSB_D_L<59>
FSB_D_L<41>
FSB_D_L<38>
FSB_D_L<0>
FSB_D_L<4>FSB_D_L<5>
FSB_D_L<43>
FSB_D_L<12>
FSB_D_L<50>FSB_D_L<49>
FSB_D_L<24>
FSB_D_L<31>
FSB_D_L<6>
FSB_CPUSLP_LFSB_CPURST_L
NB_FSB_SCOMP_LNB_FSB_SCOMP
FSB_D_L<63>FSB_D_L<62>FSB_D_L<61>FSB_D_L<60>
FSB_D_L<58>FSB_D_L<57>FSB_D_L<56>FSB_D_L<55>FSB_D_L<54>FSB_D_L<53>FSB_D_L<52>FSB_D_L<51>
FSB_D_L<48>
FSB_D_L<46>FSB_D_L<45>FSB_D_L<44>
FSB_D_L<42>
FSB_D_L<40>FSB_D_L<39>
FSB_D_L<37>FSB_D_L<36>
FSB_D_L<32>
FSB_D_L<30>FSB_D_L<29>FSB_D_L<28>FSB_D_L<27>FSB_D_L<26>FSB_D_L<25>
FSB_D_L<23>FSB_D_L<22>FSB_D_L<21>FSB_D_L<20>FSB_D_L<19>FSB_D_L<18>FSB_D_L<17>FSB_D_L<16>FSB_D_L<15>FSB_D_L<14>FSB_D_L<13>
FSB_D_L<11>
FSB_D_L<9>FSB_D_L<8>FSB_D_L<7>
FSB_D_L<10>
FSB_D_L<1>
FSB_D_L<35>FSB_D_L<34>FSB_D_L<33>
FSB_D_L<2>FSB_D_L<3>
FSB_D_L<47>
=PP1V25R1V05_S0_FSB_NB
C14251
2
R14261
2
R14251
2
R14201
2
R14151
2
R14101
2
R14111
2
C14101
2
U1400
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
J13
B15
E17
C18
A19
B19
N19
B11
C11
M11
C15
F16
L13
G12
H17
G20
B9
C8
E8
F12
B6
E5
E2
G2
M10
N12
N9
H5
P13
K9
M2
W10
Y8
V4
G7
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
M6
W3
N1
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
H7
AB2
AD7
AB1
Y3
AC6
AE2
AC5
AG3
AJ9
AH8
H3
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
G4
AE5
AJ3
AH2
AH13
F3
N8
H2
C10
D6
K5
L2
AD13
AE13
H8
K7
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
A9
E4
C6
G10
C2
M14
E13
A11
H13
B12
E12
D7
D8
W1
W2
B3
B7
AM5
AM7
R14211
2
30 8
Page 15
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
BI
L_BKLT_CTRL
L_VDD_EN
PEG_TX15*
PEG_TX14*
PEG_TX13*
PEG_TX12*
PEG_TX11*
PEG_TX10*
PEG_TX9*
PEG_TX8*
PEG_TX7*
PEG_TX6*
PEG_TX5*
PEG_TX4*
PEG_TX3*
PEG_TX2*
PEG_TX1*
PEG_TX0*
PEG_TX15
PEG_TX14
PEG_TX13
PEG_TX12
PEG_TX11
PEG_TX10
PEG_TX9
PEG_TX8
PEG_TX7
PEG_TX6
PEG_TX5
PEG_TX4
PEG_TX3
PEG_TX2
PEG_TX1
PEG_TX0
PEG_RX14
PEG_RX15*
PEG_RX14*
PEG_RX13*
PEG_RX12*
PEG_RX11*
PEG_RX15
PEG_RX13
PEG_RX12
PEG_RX11
PEG_RX10
PEG_RX9
PEG_RX8
PEG_RX7
PEG_RX6
PEG_RX5
PEG_RX4
PEG_RX3
PEG_RX2
PEG_RX1
PEG_RX0
PEG_RX10*
PEG_RX9*
PEG_RX8*
PEG_RX7*
PEG_RX6*
PEG_RX5*
PEG_RX4*
PEG_RX3*
PEG_RX2*
PEG_RX1*
PEG_RX0*
PEG_COMPI
PEG_COMPO
CRT_DDC_DATA
L_CTRL_DATA
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA0
LVDSB_DATA2*
LVDSB_DATA1*
LVDSB_DATA0*
LVDSA_DATA2
LVDSA_DATA0
LVDSA_DATA1
LVDSB_CLK*
LVDS_VREFL
LVDS_IBG
TVC_RTN
TVA_RTN
TVB_RTN
TVC_DAC
TVB_DAC
TVA_DAC
CRT_RED*
CRT_RED
CRT_GREEN*
CRT_GREEN
CRT_BLUE*
CRT_BLUE
CRT_VSYNC
CRT_TVO_IREF
CRT_HSYNC
CRT_DDC_CLK
L_BKLT_EN
L_DDC_CLK
TV_DCONSEL0
TV_DCONSEL1
LVDSA_DATA2*
L_DDC_DATA
LVDSA_DATA1*
LVDSA_DATA0*
LVDSB_CLK
LVDSA_CLK
LVDSA_CLK*
LVDS_VREFH
L_CTRL_CLK
LVDS_VBG
VGA
TV
LVDS
(3 OF 10)
PCI-EXPRESS GRAPHICS
BI
BI
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
rails must be filtered except for VCCA_CRT.
Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).
S-Video: DACB & DACC only
share filtering with VCCA_CRT_DAC.
Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.
Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,
CRT & TV-Out Disable
All CRT/TVDAC rails must be powered. All
VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,VCCD_CRT, VCCD_QDAC and VCC_SYNC.
NOTE: Must keep VDDC_TVDAC powered and filtered at all times!
Internal Graphics DisableFollow instructions for LVDS and CRT & TV-Out Disable above.
TV_DCONSELx to GND.Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and
Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.
Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).Tie VCC_AXG and VCC_AXG_NCTF to GND.Leave GFX_VID<3..0> and GFX_VR_EN as NC.
Tie TVx_DAC and TVx_RTN to GND. Must power all
TV-Out Disable / CRT Enable
CRT Disable / TV-Out Enable
VSYNC and CRT_TVO_IREF to GND.Can tie the following rails to GND:
TV-Out Signal Usage:
Composite: DACA only
Component: DACA, DACB & DACC
TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can
LVDS Disable
SDVOC_REDSDVOC_GREENSDVOC_BLUESDVOC_CLKP
SDVOB_BLUESDVOB_CLKP
SDVOB_RED#SDVOB_GREEN#SDVOB_BLUE#SDVOB_CLKNSDVOC_RED#SDVOC_GREEN#SDVOC_BLUE#SDVOC_CLKN
SDVOB_REDSDVOB_GREEN
SDVO_FLDSTALLSDVO_INTSDVO_TVCLKIN
SDVO_INT#SDVO_TVCLKIN#
SDVO Alternate Function
SDVO_FLDSTALL#
Tie VCC_TX_LVDS and VCCA_LVDS to GND.
decoupling. Otherwise, tie VCCD_LVDS to GND also.
Can leave all signals NC if LVDS is not implemented.
Unused DAC outputs must remain powered, but canomit filtering components. Unused DAC outputsshould connect to GND through 75-ohm resistors.
If SDVO is used, VCCD_LVDS must remain powered with proper
Note: SR DG says to tie LVDS_VREFH/L to GND. This causesa glitch during wake-up on LVDS DATA/CLK pairs. Newrecommendation is to float both signals, see Radar #5067636.
68 84
68 84
402MF-LF1/16W1%24.9
79
68 84
22
22
22
22
22
22
22
68 84
22
22
22 84
OMIT
CRESTLINEFCBGA
13
13
22
22
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
68 84
79
79
68 84
79
79
79 84
79 84
79 84
79 84
79 84
79 84
68 84
79 84
79 84
79 84
79 84
79 84
79 84
79 84
79 84
79 84
79 84
68 84
22
22
22
22
22
22
22
22
SYNC_DATE=03/19/2007
15 92
A.0.0051-7261
NB PEG / Video InterfacesSYNC_MASTER=T9_NOME
LVDS_BKLT_CTL
LVDS_VDD_EN
PEG_R2D_C_N<15>PEG_R2D_C_N<14>PEG_R2D_C_N<13>PEG_R2D_C_N<12>PEG_R2D_C_N<11>PEG_R2D_C_N<10>PEG_R2D_C_N<9>PEG_R2D_C_N<8>PEG_R2D_C_N<7>PEG_R2D_C_N<6>PEG_R2D_C_N<5>PEG_R2D_C_N<4>PEG_R2D_C_N<3>PEG_R2D_C_N<2>PEG_R2D_C_N<1>PEG_R2D_C_N<0>
PEG_R2D_C_P<15>PEG_R2D_C_P<14>PEG_R2D_C_P<13>PEG_R2D_C_P<12>PEG_R2D_C_P<11>PEG_R2D_C_P<10>PEG_R2D_C_P<9>PEG_R2D_C_P<8>PEG_R2D_C_P<7>PEG_R2D_C_P<6>PEG_R2D_C_P<5>PEG_R2D_C_P<4>PEG_R2D_C_P<3>PEG_R2D_C_P<2>PEG_R2D_C_P<1>PEG_R2D_C_P<0>
PEG_D2R_P<14>
PEG_D2R_N<15>PEG_D2R_N<14>PEG_D2R_N<13>PEG_D2R_N<12>PEG_D2R_N<11>
PEG_D2R_P<15>
PEG_D2R_P<13>PEG_D2R_P<12>
PEG_D2R_P<8>PEG_D2R_P<7>PEG_D2R_P<6>PEG_D2R_P<5>PEG_D2R_P<4>PEG_D2R_P<3>PEG_D2R_P<2>PEG_D2R_P<1>PEG_D2R_P<0>
PEG_D2R_N<10>PEG_D2R_N<9>PEG_D2R_N<8>PEG_D2R_N<7>
PEG_D2R_N<5>PEG_D2R_N<4>PEG_D2R_N<3>PEG_D2R_N<2>
PEG_D2R_N<0>
PEG_COMP
CRT_DDC_DATA
LVDS_B_DATA_P<1>LVDS_B_DATA_P<2>
LVDS_B_DATA_P<0>
LVDS_B_DATA_N<0>
LVDS_A_DATA_P<2>
LVDS_A_DATA_P<0>LVDS_A_DATA_P<1>
LVDS_B_CLK_N
TP_LVDS_VREFL
LVDS_IBG
=TV_C_RTN
=TV_A_RTN
=TV_C_DAC
=TV_A_DAC
=CRT_RED_L=CRT_RED=CRT_GREEN_L=CRT_GREEN=CRT_BLUE_L=CRT_BLUE
=CRT_VSYNC_R=CRT_TVO_IREF=CRT_HSYNC_R
CRT_DDC_CLK
LVDS_BKLT_EN
LVDS_DDC_CLK
TV_DCONSEL<0>TV_DCONSEL<1>
LVDS_A_DATA_N<2>
LVDS_DDC_DATA
LVDS_A_DATA_N<1>LVDS_A_DATA_N<0>
LVDS_B_CLK_P
LVDS_A_CLK_PLVDS_A_CLK_N
TP_LVDS_VREFH
PEG_D2R_N<6>
PEG_D2R_N<1>
PP1V05_S0_NB_VCCPEG
PEG_D2R_P<10>PEG_D2R_P<11>
PEG_D2R_P<9>
TP_LVDS_VBG
LVDS_CTRL_CLKLVDS_CTRL_DATA
LVDS_B_DATA_N<1>LVDS_B_DATA_N<2>
=TV_B_DAC
=TV_B_RTN
R15101
2U1400
H32
G32
K33
G35
K29
J29
F33
F29
E29
C32
E33
J40
H39
E39
E40
C37
D35
K40
L41
L43
N41
N40
C45
D46
G50
G51
E50
E51
F48
F49
E42
D44
E44
G44
A47
B47
A45
B45
N43
M43
J50
J51
L50
L51
AC45
AD44
AC41
AD40
AH47
AG46
AG49
AH49
AH45
AG45
AG42
AG41
M47
N47
U44
T45
T49
T50
T41
U40
W45
Y44
W41
Y40
AB50
AB51
Y48
W49
M45
N45
T38
U39
AD47
AC46
AC50
AC49
AD43
AC42
AG39
AH39
AE50
AE49
AH43
AH44
T46
U47
N50
N51
R51
R50
U43
T42
W42
Y43
Y47
W46
Y39
W38
AC38
AD39
M35
P33
E27
F27
G27
J27
K27
L27
21
22
22
19
Page 16
IN
IN
CLKREQ*
NC1
NC8
CL_CLK
CL_PWROK
CL_RST*
RSVD6
THERMTRIP*
PM_BM_BUSY*
RSVD4
RSVD3
RSVD7
SM_CKE1
SM_CK0*
SM_CKE0
SM_ODT0
SM_ODT2
SM_RCOMP
SM_RCOMP*
SM_VREF0
SM_VREF1
SM_RCOMP_VOL
SM_CS1*
SM_CS0*RSVD14
RSVD11
RSVD10
RSVD9
RSVD5
RSVD8
RSVD2
DPLL_REF_CLK*
DPLL_REF_SSCLK
PEG_CLK
DMI_RXN1
DMI_RXN0
DMI_RXN3
DMI_RXN2
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_TXN0
DMI_RXP3
DMI_TXN2
DMI_TXN1
DMI_TXP0
DMI_TXN3
DMI_TXP1
DMI_TXP2
DMI_TXP3
PEG_CLK*
RSVD12
CL_DATA
CL_VREF
SDVO_CTRL_CLK
SDVO_CTRL_DATA
ICH_SYNC*
TEST1
TEST2
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VR_EN
GFX_VID3
RSVD20
RSVD21
RSVD24
RSVD25
RSVD27
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD41
RSVD42
RSVD40
RSVD43
RSVD44
RSVD45
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG16
CFG15
CFG14
CFG17
CFG18
CFG19
CFG20
PM_DPRSTP*
PM_EXT_TS0*
PWROK
PM_EXT_TS1*
RSTIN*
DPRSLPVR
NC2
NC4
NC3
NC5
NC7
NC6
NC10
NC9
NC12
NC11
NC13
NC14
NC15
NC16
DPLL_REF_CLK
SM_RCOMP_VOH
SM_ODT3
SM_ODT1
RSVD13
SM_CS2*
SM_CS3*
SM_CK3
SM_CK4
SM_CK4*
SM_CKE3
RSVD1
SM_CKE4
DPLL_REF_SSCLK*
SM_CK3*
SM_CK1*
SM_CK1
SM_CK0
SA_MA14
RSVD22
RSVD23
RSVD26
SB_MA14
SM_CK2
SM_CK2*
SM_CK5
SM_CK5*
(2 OF 10)
RSVD
DDR MUXING
CLK
CFG
DMI
PM
GRAPHICS VID
ME
MISC
NC
OUT
OUT
OUT
OUT
OUT
BI
BI
IN
OUT
BI
BI
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
BI
OUT
BI
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NB CFG<13:12> require ICT access
IPU
IPU
RESERVED
RESERVED
Low = DMIx2
NB_CFG<3>
NB_CFG<8>
IPU
IPU
IPU
IPU
IPU
IPU
IPUIPUIPUIPUIPD
IPDIPD
Clk used for PEG and DMI
IPU
RESERVED
NB_CFG<6>
High = DMIx4
NB_CFG<7> RESERVED
RESERVED
RESERVED
High = Normal
Low = Reversed
NB_CFG<10>
NB_CFG<9>PCIe GraphicsLane Reversal
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
See Below
See Below
Low = Disabled
High = Enabled
10 = All-Z Mode Enabled01 = XOR Mode Enabled
Low = Normal
High = Both active
NB_CFG<13:12>
Low = Only SDVO
High = Reversed
11 = Normal Operation
or PCIe x16
00 = RESERVED
NB_CFG<19>
NB_CFG<20>ConcurrentSDVO/PCIe x1
ReversalDMI Lane
NB_CFG<13>
NB_CFG<12>
NB_CFG<11>
NB_CFG<16>
NB_CFG<14>
NB_CFG<17>
ODTFSB Dynamic
NB_CFG<15>
NB_CFG<18>
PP1V05_S0M, PP0V9_S3M and PP0V9_S0M. If ME/AMT is not used, short CL_PWROK to PWROK.
PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,NOTE: GMCH CL_PWROK input must be PWRGD signal for
DMI x2 Select
NB_CFG<5>
NB_CFG<4>
IPUIPU
NB CFG<8:0> used for debug access
7 28
8
402CERM
20%0.1uF10V
402CERM
20%0.1uF
10V
CRESTLINEFCBGA
OMIT
9
9
9
9
9
25 87
25 87
9
25 87
22
22
7 29
7 25
402
20K
MF-LF1/16W
5%
402
0
MF-LF1/16W5%
7 25 59 83
32 45
402
10K
MF-LF
5%1/16W
0.01UF10%16V
CERM402 603
2.2UF6.3VCERM1
20%
1K
MF-LF
1%1/16W
402
402
1%1/16WMF-LF
3.01K603
6.3VCERM1
2.2UF20%
0.01UF10%16V
CERM402
1K
402
1/16W1%
MF-LF
402
392
MF-LF1/16W1%
402MF-LF1/16W
1K1%
402
20%10V
CERM
0.1uF
402
5%3.9K
MF-LF1/16W
NBCFG_DMI_X2
402
5%1/16WMF-LF
3.9K
NBCFG_PEG_REVERSE
402
NBCFG_DYN_ODT_DISABLE
3.9K1/16W5%
MF-LF
402
3.9K
MF-LF1/16W5%
NBCFG_DMI_REVERSE
402
5%1/16WMF-LF
3.9K
NBCFG_SDVO_AND_PCIE
9
31 33 85
32 33 85
13 30 83
13 30 83
13 30 83
13
13
13
13
13 16
7 25
13
10 23 46 83
31 45
7 10 23 59 83
7 9 28 59
31 85
32 85
32 85
31 85
31 85
32 85
32 85
31 85
31 33 85
31 33 85
32 33 85
31 33 85
32 33 85
31 33 85
32 33 85
32 33 85
31 33 85
31 33 85
32 33 85
32 33 85
MF-LF1/16W
1%20
402
1/16W1%
MF-LF
20
402
8
7 30 88
7 30 88
22
22
22
22
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
402MF-LF1/16W
5%10K
051-7261 A.0.0
9216
SYNC_MASTER=T9_NOME SYNC_DATE=01/25/2007
NB Misc Interfaces
GFX_VID<0>
MEM_RCOMP_VOH
=PP1V8_S3M_MEM_NB
MEM_RCOMP
MEM_RCOMP_VOL
=PP0V9_S3M_MEM_NBVREFA
MEM_CKE<3>MEM_CKE<1>
NB_CFG<4>
TP_NB_RSVD<44>TP_NB_RSVD<43>
MEM_RCOMP_L
NB_CFG<5>
NB_CFG<9>NB_CFG<8>NB_CFG<7>NB_CFG<6>
NB_CFG<3>
NB_BSEL<1>NB_BSEL<2>
NB_CLINK_VREF
PP1V25_S0M_NB_VCCAXD
CLINK_NB_CLK
GFX_VID<1>
TP_NB_CFG<17>=PP3V3_S0_NB_VCCHV
=GFX_VR_EN
GFX_VID<3>
TP_NB_CFG<13>
TP_NB_CFG<11>
=PP3V3_S0_NB_VCCHV
NB_CFG<20>
NB_CFG<19>
=PP3V3_S0_NB_VCCHV
NB_CFG<16>
NB_CFG<9>
PM_EXTTS_L<1>
NB_RESET_L
PM_DPRSLPVR
TP_NB_RSVD<14>
DMI_S2N_N<1>
DMI_S2N_N<3>
TP_NB_RSVD<42>
TP_NB_RSVD<45>
TP_LVDS_B_DATAN3
TP_NB_RSVD<36>TP_NB_RSVD<35>
DMI_S2N_N<0>
MEM_A_A<14>
TP_LVDS_B_DATAP3
TP_LVDS_A_DATAN3
TP_MEM_CLKP2
TP_NB_RSVD<24>
TP_NB_RSVD<5>
=PP0V9_S3M_MEM_NBVREFB
DMI_S2N_N<2>
DMI_S2N_P<3>
GFX_VID<4>
TP_NB_NC<4>
TP_NB_RSVD<12>
TP_NB_RSVD<6>
MEM_ODT<1>MEM_ODT<0>
MEM_CS_L<3>
=NB_CLK96M_DOT_N
MEM_ODT<3>MEM_ODT<2>
MEM_CS_L<2>
PM_THRMTRIP_L
VR_PWRGOOD_DELAY
CPU_DPRSTP_LPM_BMBUSY_L
TP_MEM_CLKN5TP_MEM_CLKP5TP_MEM_CLKN2
NB_SB_SYNC_LNB_CLKREQ_LSDVO_CTRLDATASDVO_CTRLCLK
CLINK_NB_RESET_L=NB_CLINK_MPWROKCLINK_NB_DATA
GFX_VID<2>
DMI_N2S_P<3>DMI_N2S_P<2>DMI_N2S_P<1>DMI_N2S_P<0>
DMI_N2S_N<2>DMI_N2S_N<3>
DMI_N2S_N<1>DMI_N2S_N<0>
DMI_S2N_P<2>DMI_S2N_P<1>DMI_S2N_P<0>
NB_CLK100M_PCIE_NNB_CLK100M_PCIE_P
=NB_CLK96M_DOT_P
TP_NB_NC<1>
TP_NB_NC<8>
TP_NB_RSVD<4>TP_NB_RSVD<3>
TP_NB_RSVD<7>
MEM_CLK_N<0>
MEM_CLK_P<1>
MEM_CLK_N<1>
MEM_CKE<0>
MEM_CS_L<1>MEM_CS_L<0>
TP_NB_RSVD<11>TP_NB_RSVD<10>TP_NB_RSVD<9>TP_NB_RSVD<8>
TP_NB_RSVD<2>
NB_TEST1NB_TEST2
TP_NB_RSVD<20>TP_NB_RSVD<21>TP_NB_RSVD<22>TP_NB_RSVD<23>
TP_NB_RSVD<41>
TP_NB_CFG<10>
TP_NB_CFG<12>
NB_CFG<16>TP_NB_CFG<15>TP_NB_CFG<14>
TP_NB_CFG<18>NB_CFG<19>NB_CFG<20>
PM_EXTTS_L<0>
TP_NB_NC<2>TP_NB_NC<3>
TP_NB_NC<5>
TP_NB_NC<7>TP_NB_NC<6>
TP_NB_NC<10>TP_NB_NC<9>
TP_NB_NC<12>TP_NB_NC<11>
TP_NB_NC<13>TP_NB_NC<14>TP_NB_NC<15>TP_NB_NC<16>
TP_NB_RSVD<13>
MEM_CLK_P<3>MEM_CLK_P<4>
MEM_CLK_N<3>MEM_CLK_N<4>
MEM_CLK_P<0>TP_NB_RSVD<1>
MEM_CKE<4>
NB_CFG<5>
NB_BSEL<0>
=NB_CLK100M_DPLLSS_N=NB_CLK100M_DPLLSS_P
TP_NB_RSVD<25>TP_NB_RSVD<26>TP_NB_RSVD<27>
MEM_B_A<14>TP_NB_RSVD<34>
TP_LVDS_A_DATAP3
R16101
2
R16111
2
R16301
2
C16161
2
C1615 1
2
U1400
P27
N27
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
N24
L35
C21
C23
F23
N23
G23
J20
C20
AM49
AK50
AT43
AN49
AM50
G39
AN47
AJ38
AN42
AN46
AM47
AJ39
AN41
AN45
AJ46
AJ41
AM40
AM44
AJ47
AJ42
AM39
AM43
B42
C42
H48
H47
G36
E35
A39
C38
B39
E36
G40
BJ51
E1
A5
C51
B50
A50
A49
BK2
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
K44
K45
G41
L39
L36
J36
AW49
AV20
P36
AR37
AM36
AL36
AM37
D20
P37
H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
R35
BH39
AW20
BK20
C48
D47
B44
N35
C44
A35
B37
B36
B34
C34
AR12
AR13
AM12
AN13
J12
BJ29
BE24
H35
K36
AV29
AW30
BB23
BA23
BF23
BG23
BA25
AW25
AV23
AW23
BC23
BD24
BE29
AY32
BD39
BG37
BG20
BK16
BG16
BE13
BH18
BJ15
BJ14
BE16
BL15
BK14
BK31
BL31
AR49
AW4
A37
R32
N20
R16911
2
R16901
2
R16311
2
C1625 1
2
C16241
2
R16241
2
R16221
2
C16221
2
C1623 1
2
R16201
2
R16411
2
R16401
2
C1640 1
2
R16551
2
R16591
2
R16661
2
R16691
2
R16701
2
21
21
21
21
19
19
19
18
21
16
16
16
16
8
16
87
19
8
8
16
16
8
16
16
7
7
7
7
16
16
16
7
7
7
7
7
7
7
7
7
7
7
7
7
13
7
7
Page 17
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OUT
OUT
OUT
OUT
OUT
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OUT
OUT
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BI
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BI
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ4
SA_DQ6
SA_DQ14
SA_CAS*
SA_BS2
SA_DQ63
SA_DQ62
SA_DQ61
SA_DQ60
SA_DQ59
SA_DQ58
SA_DQ57
SA_DQ56
SA_DQ55
SA_DQ54
SA_DQ53
SA_DQ52
SA_DQ51
SA_DQ50
SA_DQ49
SA_DQ48
SA_DQ47
SA_DQ46
SA_DQ44
SA_DQ43
SA_DQ42
SA_DQ41
SA_DQ40
SA_DQ39
SA_DQ38
SA_DQ37
SA_DQ36
SA_DQ34
SA_DQ35
SA_DQ33
SA_DQ32
SA_DQ31
SA_DQ30
SA_DQ28
SA_DQ29
SA_DQ27
SA_DQ26
SA_DQ25
SA_DQ24
SA_DQ23
SA_DQ22
SA_DQ21
SA_DQ20
SA_DQ19
SA_DQ18
SA_DQ17
SA_DQ16
SA_DQ15
SA_DQ13
SA_DQ11
SA_DQ12
SA_DQ10
SA_DQ9
SA_DQ8
SA_DQ7
SA_DQ5
SA_DQ3
SA_BS1
SA_BS0
SA_DQ45
SA_DM0
SA_DM1
SA_DM3
SA_DM2
SA_DM5
SA_DM4
SA_DM7
SA_DM6
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS1*
SA_DQS0*
SA_DQS2*
SA_DQS4*
SA_DQS3*
SA_DQS5*
SA_DQS6*
SA_DQS7*
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA9
SA_MA8
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_RAS*
SA_RCVEN*
SA_WE*
DDR SYSTEM MEMORY A
(4 OF 10)SB_DQ2
SB_DQ1
SB_DQ5SB_DM0
SB_DQ0
SB_DQ4
SB_DQ6
SB_DQ7
SB_CAS*
SB_BS2
SB_BS0
SB_BS1
SB_DQ63
SB_DQ62
SB_DQ59
SB_DQ58
SB_DQ56
SB_DQ55
SB_DQ54
SB_DQ53
SB_DQ52
SB_DQ51
SB_DQ50
SB_DQ49
SB_DQ48
SB_DQ47
SB_DQ45
SB_DQ46
SB_DQ44
SB_DQ43
SB_DQ42
SB_DQ41
SB_DQ40
SB_DQ39
SB_DQ38
SB_DQ37
SB_DQ36
SB_DQ34
SB_DQ35
SB_DQ33
SB_DQ32
SB_DQ31
SB_DQ30
SB_DQ28
SB_DQ29
SB_DQ27
SB_DQ26
SB_DQ25
SB_DQ24
SB_DQ23
SB_DQ22
SB_DQ21
SB_DQ20
SB_DQ19
SB_DQ18
SB_DQ17
SB_DQ16
SB_DQ15
SB_DQ14
SB_DQ13
SB_DQ11
SB_DQ12
SB_DQ10
SB_DQ9
SB_DQ8
SB_DQ3
SB_DQ57
SB_DQ61
SB_DQ60
SB_WE*
SB_RCVEN*
SB_RAS*
SB_MA13
SB_MA12
SB_MA11
SB_MA10
SB_MA8
SB_MA9
SB_MA7
SB_MA6
SB_MA5
SB_MA4
SB_MA3
SB_MA2
SB_MA1
SB_MA0
SB_DQS7*
SB_DQS6*
SB_DQS5*
SB_DQS3*
SB_DQS4*
SB_DQS2*
SB_DQS0*
SB_DQS1*
SB_DQS7
SB_DQS6
SB_DQS5
SB_DQS4
SB_DQS3
SB_DQS2
SB_DQS1
SB_DQS0
SB_DM6
SB_DM7
SB_DM4
SB_DM5
SB_DM2
SB_DM3
SB_DM1
(5 OF 10)
DDR SYSTEM MEMORY B
BI
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OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
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OUT
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OUT
OUT
BI
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DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
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B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
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31 85
32 33 85 FCBGA
CRESTLINE
OMIT
FCBGACRESTLINE
OMIT
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SYNC_DATE=01/25/2007SYNC_MASTER=T9_NOME
NB DDR2 Interfaces
051-7261 A.0.0
9217
MEM_A_DQ<63>MEM_A_DQ<62>MEM_A_DQ<61>MEM_A_DQ<60>MEM_A_DQ<59>MEM_A_DQ<58>MEM_A_DQ<57>MEM_A_DQ<56>MEM_A_DQ<55>MEM_A_DQ<54>MEM_A_DQ<53>MEM_A_DQ<52>MEM_A_DQ<51>MEM_A_DQ<50>MEM_A_DQ<49>MEM_A_DQ<48>MEM_A_DQ<47>MEM_A_DQ<46>MEM_A_DQ<45>MEM_A_DQ<44>MEM_A_DQ<43>MEM_A_DQ<42>MEM_A_DQ<41>MEM_A_DQ<40>MEM_A_DQ<39>MEM_A_DQ<38>MEM_A_DQ<37>MEM_A_DQ<36>
MEM_A_DQ<34>MEM_A_DQ<33>MEM_A_DQ<32>MEM_A_DQ<31>MEM_A_DQ<30>MEM_A_DQ<29>MEM_A_DQ<28>MEM_A_DQ<27>MEM_A_DQ<26>MEM_A_DQ<25>MEM_A_DQ<24>MEM_A_DQ<23>MEM_A_DQ<22>MEM_A_DQ<21>MEM_A_DQ<20>MEM_A_DQ<19>MEM_A_DQ<18>MEM_A_DQ<17>MEM_A_DQ<16>MEM_A_DQ<15>MEM_A_DQ<14>MEM_A_DQ<13>MEM_A_DQ<12>MEM_A_DQ<11>MEM_A_DQ<10>MEM_A_DQ<9>
MEM_A_WE_L
MEM_A_RAS_L
MEM_A_A<13>MEM_A_A<12>MEM_A_A<11>MEM_A_A<10>
MEM_A_A<8>MEM_A_A<9>
MEM_A_A<7>MEM_A_A<6>MEM_A_A<5>MEM_A_A<4>MEM_A_A<3>MEM_A_A<2>MEM_A_A<1>MEM_A_A<0>
MEM_A_DQS_N<7>MEM_A_DQS_N<6>MEM_A_DQS_N<5>
MEM_A_DQS_N<3>MEM_A_DQS_N<4>
MEM_A_DQS_N<2>
MEM_A_DQS_N<0>MEM_A_DQS_N<1>
MEM_A_DQS_P<7>MEM_A_DQS_P<6>MEM_A_DQS_P<5>MEM_A_DQS_P<4>MEM_A_DQS_P<3>MEM_A_DQS_P<2>MEM_A_DQS_P<1>MEM_A_DQS_P<0>
MEM_A_DM<6>MEM_A_DM<7>
MEM_A_DM<4>MEM_A_DM<5>
MEM_A_DM<2>MEM_A_DM<3>
MEM_A_DM<1>MEM_A_DM<0>
MEM_A_BS<0>MEM_A_BS<1>
MEM_A_DQ<3>
MEM_A_DQ<5>
MEM_A_DQ<7>MEM_A_DQ<8>
MEM_A_BS<2>
MEM_A_CAS_L
MEM_A_DQ<6>
MEM_A_DQ<4>
MEM_A_DQ<2>MEM_A_DQ<1>MEM_A_DQ<0>
MEM_B_DQ<63>MEM_B_DQ<62>MEM_B_DQ<61>MEM_B_DQ<60>MEM_B_DQ<59>MEM_B_DQ<58>MEM_B_DQ<57>MEM_B_DQ<56>MEM_B_DQ<55>MEM_B_DQ<54>MEM_B_DQ<53>MEM_B_DQ<52>MEM_B_DQ<51>MEM_B_DQ<50>MEM_B_DQ<49>MEM_B_DQ<48>MEM_B_DQ<47>MEM_B_DQ<46>MEM_B_DQ<45>MEM_B_DQ<44>MEM_B_DQ<43>MEM_B_DQ<42>MEM_B_DQ<41>MEM_B_DQ<40>
MEM_B_DQ<38>MEM_B_DQ<37>MEM_B_DQ<36>MEM_B_DQ<35>MEM_B_DQ<34>MEM_B_DQ<33>MEM_B_DQ<32>MEM_B_DQ<31>MEM_B_DQ<30>MEM_B_DQ<29>MEM_B_DQ<28>MEM_B_DQ<27>MEM_B_DQ<26>MEM_B_DQ<25>MEM_B_DQ<24>MEM_B_DQ<23>MEM_B_DQ<22>MEM_B_DQ<21>MEM_B_DQ<20>MEM_B_DQ<19>MEM_B_DQ<18>MEM_B_DQ<17>MEM_B_DQ<16>MEM_B_DQ<15>MEM_B_DQ<14>MEM_B_DQ<13>MEM_B_DQ<12>MEM_B_DQ<11>MEM_B_DQ<10>MEM_B_DQ<9>
MEM_B_WE_L
MEM_B_A<13>
MEM_B_RAS_L
MEM_B_A<12>MEM_B_A<11>MEM_B_A<10>MEM_B_A<9>MEM_B_A<8>MEM_B_A<7>MEM_B_A<6>MEM_B_A<5>MEM_B_A<4>MEM_B_A<3>MEM_B_A<2>MEM_B_A<1>MEM_B_A<0>
MEM_B_DQS_N<7>
MEM_B_DQS_N<5>MEM_B_DQS_N<6>
MEM_B_DQS_N<4>
MEM_B_DQS_N<2>MEM_B_DQS_N<3>
MEM_B_DQS_N<0>MEM_B_DQS_P<7>
MEM_B_DQS_N<1>
MEM_B_DQS_P<5>MEM_B_DQS_P<6>
MEM_B_DQS_P<2>MEM_B_DQS_P<3>MEM_B_DQS_P<4>
MEM_B_DQS_P<0>MEM_B_DQS_P<1>
MEM_B_DM<7>MEM_B_DM<6>MEM_B_DM<5>MEM_B_DM<4>MEM_B_DM<3>
MEM_B_DQ<8>MEM_B_DQ<7>MEM_B_DQ<6>MEM_B_DQ<5>MEM_B_DQ<4>MEM_B_DQ<3>MEM_B_DQ<2>MEM_B_DQ<1>MEM_B_DQ<0>
MEM_B_DM<2>MEM_B_DM<1>
MEM_B_CAS_L
MEM_B_DM<0>
MEM_B_BS<2>MEM_B_BS<1>MEM_B_BS<0>
MEM_B_DQ<39>
TP_MEM_B_RCVEN_LTP_MEM_A_RCVEN_L
MEM_A_DQ<35>
U1400BB19
BK19
BF29
BL17
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
AR43
AW44
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BA45
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AY46
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
AR41
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AR45
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT42
AT9
AN9
AM9
AN11
AW47
BB45
BF48
AT46
AT47
BE48
BD47
BB43
BC41
BC37
BA37
BB16
BA16
BH6
BH7
BB2
BC1
AP3
AP2
BJ19
BD20
BC19
BE28
BG30
BJ16
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BE18
AY20
BA19
U1400AY17
BG18
BG36
BE17
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
AP49
AR51
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
AW50
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
AW51
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
AN51
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
AN50
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AV50
AY2
AY3
AU2
AT2
AV49
BA50
BB50
AT50
AU50
BD50
BC50
BK46
BL45
BK39
BK38
BJ12
BK12
BL7
BK7
BE2
BF2
AV2
AV3
BC18
BG28
BG17
BE37
BA39
BG13
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
AV16
AY18
BC17
Page 18
VCC_SM20
VCC_AXG_NCTF42
VCC_SM9
VCC_SM10
VCC_SM17
VCC_SM16
VCC3
VCC_SM5
VCC_SM8
VCC_AXG_NCTF1
VCC_AXG_NCTF2
VCC_AXG_NCTF3
VCC_AXG_NCTF4
VCC_AXG_NCTF5
VCC_AXG_NCTF6
VCC_AXG_NCTF8
VCC_AXG_NCTF7
VCC_AXG_NCTF10
VCC_AXG_NCTF9
VCC_AXG_NCTF11
VCC_AXG_NCTF12
VCC_AXG_NCTF13
VCC_AXG_NCTF14
VCC_AXG_NCTF15
VCC_AXG_NCTF16
VCC_AXG_NCTF18
VCC_AXG_NCTF17
VCC_AXG_NCTF20
VCC_AXG_NCTF19
VCC_AXG_NCTF21
VCC_AXG_NCTF22
VCC_AXG_NCTF25
VCC_AXG_NCTF26
VCC_AXG_NCTF28
VCC_AXG_NCTF27
VCC_AXG_NCTF29
VCC_AXG_NCTF20
VCC_AXG_NCTF31
VCC_AXG_NCTF32
VCC_AXG_NCTF33
VCC_AXG_NCTF34
VCC_AXG_NCTF35
VCC_AXG_NCTF36
VCC_AXG_NCTF38
VCC_AXG_NCTF37
VCC_AXG_NCTF40
VCC_AXG_NCTF39
VCC_AXG_NCTF41
VCC_AXG_NCTF43
VCC_AXG_NCTF44
VCC_AXG_NCTF45
VCC_AXG_NCTF46
VCC_AXG_NCTF48
VCC_AXG_NCTF47
VCC_AXG_NCTF49
VCC_AXG_NCTF50
VCC_AXG_NCTF51
VCC_AXG_NCTF55
VCC_AXG_NCTF58
VCC_AXG_NCTF57
VCC_AXG_NCTF59
VCC_AXG_NCTF61
VCC_AXG_NCTF60
VCC_AXG_NCTF62
VCC_AXG_NCTF63
VCC_AXG_NCTF64
VCC_AXG_NCTF66
VCC_AXG_NCTF65
VCC_AXG_NCTF67
VCC_AXG_NCTF68
VCC_AXG_NCTF69
VCC_AXG_NCTF71
VCC_AXG_NCTF70
VCC_AXG_NCTF72
VCC_AXG_NCTF73
VCC_AXG_NCTF74
VCC_AXG_NCTF76
VCC_AXG_NCTF75
VCC_AXG_NCTF77
VCC_AXG_NCTF78
VCC_AXG_NCTF79
VCC_AXG_NCTF81
VCC_AXG_NCTF80
VCC_AXG_NCTF82
VCC_AXG_NCTF83
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC_AXG_NCTF56
VCC_AXG_NCTF54
VCC_AXG_NCTF53
VCC_AXG_NCTF52
VCC_AXG1
VCC_AXG2
VCC_AXG3
VCC_AXG4
VCC_AXG5
VCC_AXG6
VCC_AXG7
VCC_AXG8
VCC_AXG9
VCC_AXG10
VCC_AXG11
VCC_AXG12
VCC_AXG13
VCC_AXG14
VCC_AXG15
VCC_AXG16
VCC_AXG17
VCC_AXG18
VCC_AXG19
VCC_AXG20
VCC_AXG21
VCC_AXG22
VCC_AXG23
VCC_AXG24
VCC_AXG25
VCC_AXG26
VCC_AXG27
VCC_AXG28
VCC_AXG29
VCC_AXG30
VCC_AXG31
VCC_AXG32
VCC_AXG33
VCC_AXG34
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM6
VCC_SM7
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM18
VCC_SM19
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM25
VCC_SM24
VCC1
VCC2
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC_AXG_NCTF24
VCC_AXG_NCTF23
VCC6
VCC5
VCC4
VCC GFX
VCC SM
VCC SM LF
(6 OF 10)
VCC CORE
POWER
VCC GFX NCTF
VCC_NCTF49
VCC_NCTF15
VCC_NCTF2
VCC_NCTF10
VCC_AXM7
VCC_AXM5
VCC_AXM4
VCC_AXM3
VCC_AXM2
VCC_AXM1
VSS_SCB6
VSS_SCB5
VSS_SCB4
VSS_SCB3
VSS_SCB2
VSS_SCB1
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF12
VSS_NCTF11
VSS_NCTF13
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VCC_NCTF22
VCC_NCTF27
VCC_NCTF50
VCC_NCTF47
VCC_NCTF48
VCC_NCTF44
VCC_NCTF43
VCC_NCTF39
VCC_NCTF40
VCC_NCTF38
VCC_NCTF37
VCC_NCTF34
VCC_NCTF35
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF29
VCC_NCTF28
VCC_NCTF26
VCC_NCTF24
VCC_NCTF25
VCC_NCTF23
VCC_NCTF21
VCC_NCTF18
VCC_NCTF19
VCC_NCTF16
VCC_NCTF17
VCC_NCTF3
VCC_NCTF4
VCC_NCTF41
VCC_NCTF42
VCC_NCTF45
VCC_NCTF46VCC_AXM6
VCC_AXM_NCTF1
VCC_AXM_NCTF2
VCC_AXM_NCTF3
VCC_AXM_NCTF4
VCC_AXM_NCTF5
VCC_AXM_NCTF6
VCC_AXM_NCTF7
VCC_AXM_NCTF8
VCC_AXM_NCTF9
VCC_AXM_NCTF10
VCC_AXM_NCTF11
VCC_AXM_NCTF12
VCC_AXM_NCTF13
VCC_AXM_NCTF14
VCC_AXM_NCTF15
VCC_AXM_NCTF16
VCC_AXM_NCTF17
VCC_AXM_NCTF18
VCC_AXM_NCTF19
VCC_NCTF8
VCC_NCTF20
VCC_NCTF1
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF36
VCC_NCTF30
VCC_NCTF9
VCC AXM NCTF
VCC NCTF
VSS SCB
VCC AXM
VSS NCTF
(7 OF 10)
POWER
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONECurrent numbers from Crestline EDS, doc #21749.
NCTF balls are Not Critical To FunctionThese connections can break without
impacting part performance.
5 mA (standby)
7700 mA (Int Graphics)
1310 mA (Ext Graphics)1573 mA (Int Graphics)
540 mA
3300 mA (2 ch, 667MHz)2700 mA (2 ch, 533MHz)1700 mA (1 ch, 667MHz)1395 mA (1 ch, 533MHz)
FCBGA
CRESTLINE
OMIT
FCBGACRESTLINE
OMIT
20%
CERM10V
0.1uF
402
20%
CERM10V
0.1uF
402
20%6.3V
0.22UF
X5R402
20%6.3V
0.22UF
X5R402
6.3V
1uF
CERM
10%
402CERM-X5R
6.3V
0.47UF10%
402
6.3V
1uF
CERM
10%
402
SYNC_MASTER=T9_NOME SYNC_DATE=01/25/2007
NB Power 1
051-7261 A.0.0
9218
=PP1V8_S3M_MEM_NB
=PPVCORE_S0_NB_GFX=PPVCORE_S0_NB
=PPVCORE_S0_NB_GFX
NB_VCCSM_LF6
NB_VCCSM_LF4NB_VCCSM_LF3NB_VCCSM_LF2NB_VCCSM_LF1
=PP1V05_S0M_NB_VCCAXM
=PPVCORE_S0_NB
NB_VCCSM_LF7
NB_VCCSM_LF5
=PP1V05_S0M_NB_VCCAXM
U1400AT35
AH31
AH29
AF32
R30
AT34
AH28
AC31
AC32
AK32
AJ31
AJ28
AH32
R20
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
T14
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
W13
AH24
AH26
AD31
AJ20
AN14
W14
Y12
AA20
AA23
AA26
AA28
T17
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
T18
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
T19
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
T21
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
T22
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
T23
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
T25
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
U15
V26
V28
V29
Y31
U16
AU32
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
AU33
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
AU35
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
AV33
AW33
AW35
AY35
BA32
BA33
AW45
BC39
BE39
BD17
BD4
AW8
AT6
U1400
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
AL24
AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33
AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33
AB33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AB36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AB37
AP36
AR35
AR36
Y32
Y33
Y35
Y36
Y37
T30
T34
AC33
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
AC35
V37
AC36
AD35
AD36
AF33
T27
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
T37
AR19
AR28
U24
U28
V31
V35
AA19
AB17
AB35
A3
B2
C1
BL1
BL51
A51
C1806 1
2
C1807 1
2
C1804 1
2
C1805 1
2
C1802 1
2
C1803 1
2
C1801 1
2
22
22
21
22 21
22 21
21
21
16
18 18
18 18
18
18
8
8 8
8 8
8
8
Page 19
VCCA_CRT_DAC1
VTT7
VTT8
VCC_AXD_NCTF
VCCD_CRT
VCC_RXR_DMI1
VCC_RXR_DMI2
VTT1
VCCA_SM_CK2 VCC_TX_LVDS
VCC_HV2
VCC_PEG1
VCC_PEG2
VCC_PEG3
VCC_AXF2
VCC_AXD1
VCC_AXD2
VSSA_LVDS
VCCA_SM5
VCCA_PEG_PLL
VCCA_MPLL
VCCA_HPLL VTT16
VTT17
VTT15
VCCD_LVDS2
VCCD_LVDS1
VCCD_PEG_PLL
VCCD_HPLL
VCCD_QDAC
VCCD_TVDAC
VCCA_TVC_DAC1
VCCA_TVC_DAC2
VCCA_TVB_DAC2
VCCA_TVB_DAC1
VCCA_TVA_DAC2
VCCA_TVA_DAC1
VCCA_SM_CK1
VCCA_SM2
VCCA_SM1
VCCA_SM_NCTF2
VCCA_SM_NCTF1
VCCA_SM11
VCCA_SM10
VCCA_SM9
VCCA_SM8
VCCA_SM7
VCCA_SM4
VCCA_SM3
VSSA_PEG_BG
VCCA_PEG_BG
VCCA_LVDS
VCCA_DPLLB
VCCA_DPLLA
VSSA_DAC_BG
VCCA_DAC_BG
VCC_AXF3
VCC_HV1
VCC_PEG5
VTTLF1
VTTLF3
VTTLF2
VCC_PEG4
VCC_SM_CK3
VCC_SM_CK2
VCC_SM_CK1
VCC_SM_CK4
VCC_DMI
VCC_AXF1
VTT22
VCC_AXD6
VCC_AXD5
VCC_AXD4
VCC_AXD3
VTT19
VTT2
VTT6
VTT5
VTT11
VTT10
VTT9
VTT13
VTT12
VTT14
VTT18
VTT21
VTT20
VTT3
VTT4VCCA_CRT_DAC2
VCC_SYNC
CRT
AXD
PEG
HV
AXF
VTTLF
VTT
SM CK
DMI
TV/CRT
DLVDS
A SM
A CK
CRT
A LVDS
A PEG
PLL
(8 OF 10)
POWER
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
100 mA
100 mA
100 mA
200 mA
5 mA
50 mA
100 mA
10 mA
40 mA
40 mA
40 mA
60 mA
250 mA
150 mA
5 mA
S0 or S3M is acceptable
S0 or S3M is acceptable
TBD mA @ 1067MHz FSB (1.25V)
150 mA
770 mA @ 667MHz FSB (1.05V)
1260 mA
260 mA
0.4 mA
80 mA
30 mA
60 mA
100 mA
35 mA
850 mA @ 800MHz FSB (1.05V)
495 mA
515 mA
Current numbers from Crestline EDS, doc #21749.
640 mA (667MHz DDR)550 mA (533MHz DDR)
6.3V
402CERM-X5R
10%0.47UF
402CERM-X5R6.3V10%0.47UF
402CERM-X5R6.3V10%0.47UF
CRESTLINEFCBGA
OMIT
SYNC_MASTER=T9_NOME SYNC_DATE=01/25/2007
NB Power 2
19 92
A.0.0051-7261
=PP3V3_S0_NB_VCCA_PEG_BG
PP1V25_S0M_NB_VCCA_SM
PP1V8_S3M_NB_VCCSMCK
PP1V25_S0_NB_PEGPLL
PP1V25_S0M_NB_VCCA_SM_CK
=PP3V3_S0_NB_VCCSYNC
PP3V3_S0_NB_VCCA_CRTDAC
PP1V8_S0_NB_VCCTXLVDS
=PP1V25R1V05_S0_NB_VTT
PP3V3_S0_NB_VCCA_TVDACB
PP1V25_S0_NB_VCCA_DPLLB
PP3V3_S0_NB_VCCA_TVDACC
PP1V25_S0M_NB_VCCAXD
PP1V25_S0_NB_VCCAXF
PP1V05_S0_NB_VCCRXRDMI
=PP3V3_S0_NB_VCCHV
PP1V05_S0_NB_VCCPEG
PP1V8_S0_NB_VCCTXLVDS
=GND_NB_VSSA_PEG_BG
=GND_NB_VSSA_DAC_BG
=PP1V25_S0_NB_VCCDMI
NB_VTTLF_CAP3
NB_VTTLF_CAP1
PP1V25_S0M_NB_VCCA_MPLL
PP3V3_S0_NB_VCCA_DAC_BG
=GND_NB_VSSA_LVDS
=PP1V25_S0M_NB_VCCD_HPLL
PP1V5_S0_NB_VCCD_QDAC
PP1V5_S0_NB_VCCD_TVDAC=PP1V5_S0_NB_VCCD_CRT
PP3V3_S0_NB_VCCA_TVDACA
PP1V25_S0M_NB_VCCA_HPLL
PP1V25_S0_NB_VCCA_DPLLA
=PP1V8_S0_NB_VCCD_LVDS
NB_VTTLF_CAP2
U1400
AT23
AU28
AU24
AT29
AT25
AT30
AR29
B23
B21
A21
AJ50
C40
B40
AD51
W50
W51
V49
V50
AH50
AH51
BK24
BK23
BJ24
BJ23
J32
A43
A33
B33
A30
B49
H49
AL2
A41
AM2
K50
U51
AW18
AT18
AT17
AV19
AU19
AU18
AU17
AT22
AT21
AT19
BC29
BB29
AR17
AR16
C25
B25
C27
B27
B28
A28
M32
AN2
J41
H42
U48
N28
L29
B32
B41
K49
U13
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
U12
R3
R2
R1
U11
U9
U8
U7
U5
U3
U2
A7
F2
AH1
C19111
2
C19131
2
C19121
2
21
21
22
21
21
16
21
22
21
8
21
21
21
21
22
22
19
8
22
22
22
16
21
21
8
15
19
21
22
8
21
22
22
21
22
22
22
22
21
22
22
Page 20
VSS198VSS99
VSS197VSS98
VSS196VSS97
VSS195VSS96
VSS194VSS95
VSS193VSS94
VSS192VSS93
VSS191VSS92
VSS190VSS91
VSS189VSS90
VSS188VSS89
VSS187VSS88
VSS186VSS87
VSS185VSS86
VSS184VSS85
VSS183VSS84
VSS182VSS83
VSS181VSS82
VSS180VSS81
VSS179VSS80
VSS178VSS79
VSS177VSS78
VSS176VSS77
VSS175VSS76
VSS174VSS75
VSS173VSS74
VSS172VSS73
VSS171VSS72
VSS170VSS71
VSS169VSS70
VSS168VSS69
VSS167VSS68
VSS166VSS67
VSS165VSS66
VSS164VSS65
VSS163VSS64
VSS162VSS63
VSS161VSS62
VSS160VSS61
VSS159VSS60
VSS158VSS59
VSS157VSS58
VSS156VSS57
VSS155VSS56
VSS154VSS55
VSS153VSS54
VSS152VSS53
VSS151VSS52
VSS150VSS51
VSS149VSS50
VSS148VSS49
VSS147VSS48
VSS146VSS47
VSS145VSS46
VSS144VSS45
VSS143VSS44
VSS142VSS43
VSS141VSS42
VSS140VSS41
VSS139VSS40
VSS138VSS39
VSS137VSS38
VSS136VSS37
VSS135VSS36
VSS134VSS35
VSS133VSS34
VSS132VSS33
VSS131VSS32
VSS130VSS31
VSS129VSS30
VSS128VSS29
VSS127VSS28
VSS126VSS27
VSS125VSS26
VSS124VSS25
VSS123VSS24
VSS122VSS23
VSS121VSS22
VSS120VSS21
VSS119VSS20
VSS118VSS19
VSS117
VSS116VSS17
VSS115VSS16
VSS114VSS15
VSS113VSS14
VSS112VSS13
VSS111VSS12
VSS110VSS11
VSS109VSS10
VSS108VSS9
VSS107VSS8
VSS106VSS7
VSS105VSS6
VSS104VSS5
VSS103VSS4
VSS102
VSS101
VSS100VSS1
VSS18
VSS2
VSS3
VSS
(9 OF 10)
VSS202
VSS289
VSS290
VSS291
VSS292
VSS295
VSS199 VSS287
VSS200 VSS288
VSS201
VSS203
VSS204
VSS293
VSS294
VSS208 VSS296
VSS209 VSS297
VSS210 VSS298
VSS211 VSS299
VSS212 VSS300
VSS213 VSS301
VSS214
VSS215
VSS216 VSS302
VSS217
VSS218
VSS219 VSS303
VSS220
VSS221
VSS222 VSS304
VSS223
VSS224
VSS225 VSS305
VSS226
VSS227
VSS228
VSS229 VSS306
VSS230 VSS307
VSS231 VSS308
VSS232 VSS309
VSS233 VSS310
VSS234 VSS311
VSS235 VSS312
VSS236 VSS313
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS207
VSS206
VSS205
(10 OF 10)
VSS
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TDE_SENSE
TDE_FORCE
TDB_FORCE
alias these nets directly to GND.Mainly for investigation. If not used,
NOTE: TDB = _N
TDB_SENSE
Crestline Thermal Diode Pins
NOTE: TDE = _P
CRESTLINE
OMIT
FCBGACRESTLINE
OMIT
FCBGA
SYNC_DATE=01/25/2007SYNC_MASTER=T9_NOME
NB Grounds
20 92
A.0.0051-7261
=NB_TDE_SENSE
=NB_TDE_FORCE
=NB_TDB_FORCE
=NB_TDB_SENSE
U1400A13
AB26
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AB28 AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
AB31
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
AC10
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
AC13
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
AC3
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
AC39
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
AC43
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
AC47
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
AD1
BL47
C12
C16
C19
C28
C29
C33
C36
C41
A15
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
A17
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
A24
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AA21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AA24
AK31
AK51
AL1
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AA29
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AB20
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AB23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
U1400C46
C50
C7
D13
D24
D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36
F4
F40
F50
G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48
G8
H24
H28
H4
H45
J11
J16
J2
J24
J28
J33
J35
J39
K12
K47
K8
L1
L17
L20
L24
L28
L3
L33
L49
M28
M42
M46
M49
M5
M50
M9
N11
N14
N17
N29
N32
N36
N39
N44
N49
N7
P19
P2
P23
P3
P50
R49
T39
T43
T47
U41
U45
U50
V2
V3
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
51
51
51
51
Page 21
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
GMCH Core Power
1573mA (Int Graphics)
WF: Matanzas has 2-pin 270uF bulk cap
GMCH ME Core Power
540 mA
850 mA (800MHz FSB)
GMCH Memory I/O Rail
770 mA (667MHz FSB)
and DDR2 taps." (C2135)Placeholder for 3.9nH, 1A, 32mOhm
1310mA (Ext Graphics)
GMCH FSB I/O Rail
Current numbers from Crestline EDS, doc #21749.
260 mA
1520 mA 1260 mA
495 mA495 mA
550 mA (533MHz DDR2)640 mA (667MHz DDR2)
35 mA
0.4 mA
515 mA515 mA
585 mA (533MHz DDR2)675 mA (667MHz DDR2)
3300 mA (2ch 667MHz)2700 mA (2ch 533MHz)1700 mA (1ch 667MHz)1395 mA (1ch 533MHz) 5 mA (standby)
Layout Note: Route to caps, then GND
NOTE: This follower is redundant if VCORE is always 1.05V.
100 mA100 mA
100 mA
200 mA 200 mA
on opposite side.be close to MCH
Layout Note:
on opposite side.be close to MCH
450 mA
150 mA
50 mA
250 mA
100 mA
10uF caps should
Placeholder for 2.2nH, 1.4A, 17mOhm
Layout Note:Place L and Cclose to MCH
WF: "Place where LVDS
Layout Note:10uF caps should
Placeholder for 5.6nH, 0.9A, 45mOhm max
402
6.3V
PLACEMENT_NOTE=Place close to U1400
CERM-X5R
10%0.47UF
6.3V20%
PLACEMENT_NOTE=Place close to U1400
2.2uF
603CERM1
4.7uF
603
PLACEMENT_NOTE=Place close to U1400
CERM
20%6.3V
10V
0.1uF
402CERM
20%10V
0.1uF
402CERM
20%
20%
TANT
CRITICAL
D2T
470UF2.5V
10V
PLACEMENT_NOTE=Place in GMCH cavity
0.1uF
402CERM
20%0.22uF
402
20%6.3VX5R
402
20%6.3VX5R
0.22uF20%
6.3VCERM-X5R
805-3
22UF
CERM
PLACEMENT_NOTE=Place in GMCH cavity
10V
0.1uF
402
20%
PLACEMENT_NOTE=Place in GMCH cavity
10V
0.1uF
402CERM
20%
4.7uF
603
PLACEMENT_NOTE=Place close to U1400
CERM
20%6.3V
6.3V20%
PLACEMENT_NOTE=Place close to U1400
CERM-X5R805-3
22UF6.3V20%
PLACEMENT_NOTE=Place close to U1400
CERM-X5R805-3
22UF0.1uF20%
CERM402
10V
0.51
MF-LF1/16W
1%
402
10V
0.1uF
402CERM
20%
402
1.11%
1/16WMF-LF
0805
FERR-220-OHM
10uF20%
6.3VX5R603
10V
0.1uF
402CERM
20%
PLACEMENT_NOTE=Place C2180 by U1400.AN2
10V
0.1uF
402CERM
20%
D3LPOLY6.3V20%
330uF
CRITICAL
CRITICAL
D3LPOLY6.3V20%
330uF
20%
603
10uF6.3VX5R
CRITICALCASE-B2
2.5V
220UF20%
POLY
91NH
1210
10V
402CERM
20%0.1uF
402MF-LF
1%1/16W
1.1
0805
1.0UH-220MA-0.12-OHM
603
10uF20%
6.3VX5R
6.3V20%
CERM-X5R805-3
22UF
10V
0.1uF
402CERM
20%
X5R10V10%
402
1uF
603X5R
6.3V20%
10uF603
5%
MF-LF1/10W
0
X5R10V10%1uF
4025%1/10WMF-LF
0
603
NO STUFF
0603
FERR-120-OHM-0.2A
6.3V20%
CERM-X5R805-3
22UF6.3V20%
NO STUFF
CERM-X5R805-3
22UF 4.7UF6.3V20%
CERM603
CRITICAL
D3LPOLY6.3V20%
330uF
X5R
1uF
402
10%10V
0
5%1/10WMF-LF603
20%6.3V
CERM-X5R805-3
22UF
0
603MF-LF1/10W5%
CERM
20%
402
0.1uF10V
1/16W1%
MF-LF
10
402BAT54E3
SOT23
10
MF-LF
1%1/16W
402BAT54E3
SOT23
NO STUFF
6.3V20%
CERM-X5R805-3
22UF
NO STUFF
6.3V20%2.2uF
603CERM1
0603
FERR-120-OHM-0.2A
10V
0.1uF
402CERM
20%
PLACEMENT_NOTE=Place in GMCH cavity
603
10uF20%6.3VX5R
0.22uF
PLACEMENT_NOTE=Place in GMCH cavity
402
20%6.3VX5R
0.22uF
PLACEMENT_NOTE=Place in GMCH cavity
402
20%6.3VX5R
10V
PLACEMENT_NOTE=Place C2184 by U1400.AM2
0.1uF
402CERM
20%
PLACEMENT_NOTE=Place C2182 by U1400.AL2
10V
0.1uF
402CERM
20%6.3V20%
22UF
CERM-X5R805-3
0603
FERR-120-OHM-0.2A
6.3V20%
22UF
CERM-X5R805-3
22UF
805-3CERM-X5R
PLACEMENT_NOTE=Place in GMCH cavity
20%6.3V
SYNC_MASTER=T9_NOME
051-7261 A.0.0
21 92
SYNC_DATE=12/21/2006
NB Standard Decoupling
PP1V8_S3M_NB_VCCSMCKMIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.8V
=PP1V8_S3M_NB_VCC
=PP1V25_S0M_NB_VCC
MIN_NECK_WIDTH=0.2 MM
PP1V25_S0_NB_PEGPLL_RCMIN_LINE_WIDTH=0.25 MM
VOLTAGE=1.25V
PP1V25_S0_NB_PEGPLLMIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.25V
=PP1V25_S0_NB_PLL
VOLTAGE=1.25V
PP1V25_S0M_NB_VCCAXDMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM
=PP1V05_S0_NB_PCIE
PP1V25_S0_NB_VCCAXFMIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.25VMIN_NECK_WIDTH=0.2 MM
=PP1V25_S0_NB_VCC
=PP1V05_S0_NB_FOLLOW
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.25 MMPP1V8_S3M_NB_VCCSMCK_RC
VOLTAGE=1.8V
=PP3V3_S0_NB_VCCA_PEG_BG
=PPVCORE_S0_NB_FOLLOW
MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM
PP3V3_S0_NBCORE_FOLLOW_R
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V
PP3V3_S0_NB1V05_FOLLOW_R=PP3V3_S0_NB_FOLLOW
=PP1V25_S0M_NB_VCCD_HPLL
MIN_LINE_WIDTH=0.3 MM
VOLTAGE=1.25VMIN_NECK_WIDTH=0.2 MM
PP1V25_S0M_NB_MPLL_RC
=PP1V25_S0_NB_VCCDMI
=PP1V25_S0M_NB_PLL
MIN_LINE_WIDTH=0.3 MM
VOLTAGE=1.25VMIN_NECK_WIDTH=0.2 MM
PP1V25_S0M_NB_VCCA_MPLL
=PP3V3_S0_NB_VCCHV
=GND_NB_VSSA_PEG_BG
PP1V25_S0M_NB_VCCA_HPLLMIN_LINE_WIDTH=0.25 MM
VOLTAGE=1.25VMIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MMPP1V05_S0_NB_VCCRXRDMIMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V
PP1V25_S0M_NB_VCCA_SM_CKMIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.25VMIN_NECK_WIDTH=0.2 MM
=PP1V25R1V05_S0_NB_VTT
=PP1V25_S0M_NB_VCCA
MAKE_BASE=TRUE
PP1V05_S0_NB_VCCPEGMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V
MIN_LINE_WIDTH=0.5 MM
=PP1V8_S3M_MEM_NB
PP1V25_S0M_NB_VCCA_SMMIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.25VMIN_NECK_WIDTH=0.2 MM
=PP1V05_S0M_NB_VCCAXM
=PPVCORE_S0_NB
L2181
1 2
C21041
2
C21771
2
C21031
2
C21021
2
C21841
2
C21821
2
C2181 1
2
L2183
1 2
C2183 1
2
C21011
2
C21241
2
C2123 1
2
C2121 1
2
C21611
2
C21651
2
C2100 1
2 3
C21131
2
C21121
2
C21111
2
C2110 1
2
C21141
2
C21151
2
C2122 1
2
C21311
2
C21321
2
C21351
2
R21831
2
C21911
2
R21901
2
L2190
1 2
C2190 1
2
C21921
2
C21801
2
C2130 1
2
C2120 1
2
C21741
2
C2173 1
2
L2173
1 2
C21971
2
R21951
2
L2195
1 2
C2195 1
2
C2196 1
2
C21601
2
C21711
2
C2170 1
2
R21701 2
C21511
2
R21501 2
L2150
1 2
C2142 1
2
C2141 1
2
C21431
2
C2140 1
2
C21441
2
R21411 2
C2145 1
2
R21451 2
C21481
2
R21861 2
D21861 3
R21851 2
D21851 3
C2150 1
2
C21461
2
19
18
22
19
19 19
16
19
19
16
18
18
19 8
8
19 8
16
8
19 8
8
8
8
8
19
8
8
19
8
19
19
19
19
8
8
15
8
19
8
8
Page 22
IN
OUTEN NR/FBIN
GND
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
GMCH Graphics Core Power
VCCD_TVDAC also powers internal thermal sensors.
7700 mA
Vout = 1.25V (Factory Programmed)
Layout Note: Route to cap, then GND
65 mA
Crestline LVDS Support
260 mA 110 mA
150 mA
Current numbers from Crestline EDS Addendum, doc #20127.
60 mA
Layout Note:
within 6.35 mm of NB edgeThese 2 caps should be
100 mA
100 mA(1.7V - 5.5V)100 mA
NOTE: This filter is required even if using only external graphics.402
MF-LF1/16W
1%2.37K
15 84
6.3VCERM402
10%1UF
TPS731125SOT23-5
CRITICAL
0.01UF
CERM402
16V10%
5%
FF603
0.3001/10W
1/16WMF-LF
4.7
5%
402
NO STUFF
10V
0.1uF
402CERM
20%
NO STUFF
MF-LF402
4.7
5%1/16W
10V
402CERM
20%0.1uF
603
10UF20%6.3VX5R
0.001UF
402
10%50VCERM
402
10%50VCERM
0.001UF
NFM1816V
22000pF-1000mA
0.1uF10V
402CERM
20%
1.0UH-0.5A
1210
220UF20%
6.3VPOLY
CRITICALCASE-D3L
PLACEMENT_NOTE=Place in GMCH cavity
10V
402CERM
20%0.1uF
CERM402
PLACEMENT_NOTE=Place in GMCH cavity
10V
0.1uF20%
0.47UF
CERM-X5R6.3V
PLACEMENT_NOTE=Place in GMCH cavity
10%
402603
10uF
PLACEMENT_NOTE=Place in GMCH cavity
X5R6.3V20%
805-3CERM-X5R
22UF
PLACEMENT_NOTE=Place in GMCH cavity
20%6.3V
CRITICALCRITICAL
TANT
20%470UF
D2T
2.5V
CRITICAL
470UF
TANTD2T
2.5V20%
6.3VCERM402
10%1UF
402
PLACEMENT_NOTE=Place in GMCH cavity
1UF10%
CERM6.3V
SYNC_MASTER=M75_MLB
22 92
A.0.0051-7261
NB Graphics DecouplingSYNC_DATE=03/20/2007
NC_LVDS_VREFHMAKE_BASE=TRUENO_TEST=TRUE
TP_LVDS_VREFL NC_LVDS_VREFLMAKE_BASE=TRUENO_TEST=TRUE
TP_LVDS_VREFH
NB_CLK100M_DPLLSS_N
=PP1V5_S0_NB_TVDAC
=CRT_BLUE=CRT_BLUE_L
=CRT_GREEN=CRT_GREEN_L
=CRT_HSYNC_R
=CRT_RED=CRT_RED_L
=CRT_TVO_IREF=CRT_VSYNC_R
=GND_NB_VSSA_DAC_BG
=NB_CLK96M_DOT_P
=PP1V5_S0_NB_VCCD_CRT
=PP3V3_S0_NB_VCCSYNC
=TV_A_DAC=TV_A_RTN=TV_B_DAC=TV_B_RTN=TV_C_DAC=TV_C_RTN
CRT_DDC_CLKCRT_DDC_DATA
PP1V5_S0_NB_VCCD_QDAC
PP3V3_S0_NB_VCCA_CRTDAC
PP3V3_S0_NB_VCCA_DAC_BG
PP3V3_S0_NB_VCCA_TVDACAPP3V3_S0_NB_VCCA_TVDACBPP3V3_S0_NB_VCCA_TVDACC
SDVO_CTRLCLKSDVO_CTRLDATATV_DCONSEL<0>TV_DCONSEL<1>
=PPVIN_S0_NB_DPLL
VOLTAGE=0V
MIN_LINE_WIDTH=0.4 MMGND_DPLL_ESRMIN_NECK_WIDTH=0.2 MM
PP1V25_S0_NB_DPLLMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.25V
MIN_LINE_WIDTH=0.4 MM
P1V25S0NBDPLL_NR
PP1V25_S0_NB_VCCA_DPLLBMIN_LINE_WIDTH=0.3 MM
VOLTAGE=1.25VMIN_NECK_WIDTH=0.2 MM
PP1V5_S0_NB_VCCD_TVDACMIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.5V
VOLTAGE=1.25VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.3 MMPP1V25_S0_NB_VCCA_DPLLA
=PP1V8_S0_NB_LVDS
LVDS_IBG
=PPVCORE_S0_NB=NB_CLK96M_DOT_N
=NB_CLK100M_DPLLSS_P
=NB_CLK100M_DPLLSS_N
MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.8V
MIN_LINE_WIDTH=0.2 MMPP1V8_S0_NB_VCCTXLVDS
=GND_NB_VSSA_LVDS
=PP1V8_S0_NB_VCCD_LVDS
NB_CLK100M_DPLLSS_P
=PPVCORE_S0_NB_GFX
R22611 2
C22611
2
R22621 2
C22621
2
C22601
2
C22231
2
C22211
2
C2201
2
1 3
C22001
2
L2220
1 2
C2220 1
2
C22171
2
C22161
2
C22151
2
C22131
2
C22121
2
C2211 1
2 3
C2210 1
2 3
C22261
2
C22141
2
R22991
2
C2265 1
2
U2265
3
2
1
4
5
C2266 1
2
R22601
2
88
21
88
30
18
30
18
15
15
7
8
15
15
15
15
15
15
15
15
15
19
16
19
19
15
15
15
15
15
15
15
15
19
19
19
19
19
19
16
16
15
15
8
19
19
19
8
8
16
16
16
19
19
19
7
8
Page 23
SATA0RXP
SATA0RXN
SATALED*
RTCRST*
HDA_BIT_CLK
DDREQ
RTCX1
RTCX2
DCS1*
DCS3*
IDEIRQ
DDACK*
IORDY
DIOR*
DIOW*
DD11
DD12
DD4
DD2
DD14
DD0
DD15
DD1
DD13
DD5
DD10
DD8
DD3
DD9
LDRQ0*
FWH2/LAD2
FWH3/LAD3
FWH1/LAD1
LDRQ1*/GPIO23
FWH0/LAD0
FWH4/LFRAME*
HDA_SDIN0
HDA_SYNC
SATA1TXN
SATA1TXP
HDA_SDIN1
HDA_SDIN2
RCIN*
SATA0TXP
SATA0TXN
CPUPWRGD/GPIO49
SMI*
A20M*
SATA1RXP
SATA1RXN
SATARBIAS
SATARBIAS*
IGNNE*
DPRSTP*
INTVRMEN
A20GATE
SATA2RXN
SATA2RXP
THRMTRIP*
DPSLP*
INIT*
HDA_RST*
HDA_SDOUT
HDA_DOCK_EN*/GPIO33
SATA2TXN
SATA2TXP
FERR*
NMI
HDA_SDIN3
INTR
SATA_CLKP
SATA_CLKN
DA2
DD6
STPCLK*
TP8
DA0
DA1
HDA_DOCK_RST*/GPIO34
INTRUDER*
LAN_TXD0
LAN100_SLP
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
DD7
LAN_TXD2
LAN_TXD1
GLAN_DOCK*/GPIO13
GLAN_COMPI
GLAN_COMPO
GLAN_CLK
LAN/GLAN
IHDA
CPU
RTC
LPC
(1 OF 6)
SATA
IDE
OUT
IN
IN
IN
BI
BI
BI
BI
BI
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S
INT PU
INT PU
INT PU
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PU INT PD
INTEGRATED PD
INTEGRATED PD
INTEGRATED PDs
ACZ_SYNC
HDA_SDOUT
HDA_SDIN[0-2]
HDA_RST#
HDA_BIT_CLK 24.000MHZ CLOCK W/INTERNAL WEAK PD
HDA
INT PD
INT PU
INT PU
INT PU
ICH8MBGA
OMIT
28
28
7 28
28
7 45 47
7 45 47
7 45 47
7 45 47
28 66
7 45 47
10 83
NO STUFF
2.2K5%
1/16WMF-LF
402
1/16WMF-LF
24.91%
402
1/16W
402MF-LF
332K1%
80 86
80 86
80 86
80 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
30 88
30 88
42
42
7 10 16 59 83
7 10 83
10 83
7 10 13 83
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
42 86
7 10 83
10 83
10 83
10 83
10 47 83
10 83
1/16W5%
402MF-LF
10K
10 16 46 83
402
24.9
1/16WMF-LF
1%PLACEMENT_NOTE=Place R2308 within 50mm of U2300
34 86
MF-LF402
332K1%
1/16W
402MF-LF1/16W
5%8.2K
34 86
34 86
34 86
34 86
8.2K5%
1/16WMF-LF
402
54.9
402MF-LF1/16W
1%
PLACEMENT_NOTE=Place R2309 within 50mm of R2308 (NO STUB)
54.9
402MF-LF1/16W1%
5% 1/16W MF-LF33
402
40233
MF-LF1/16W5%
4025% MF-LF33
1/16W
33402MF-LF1/16W5%
5%10K
MF-LF402
1/16W
42 86
42 86
SB Enet, Disk, FSB, LPCSYNC_DATE=01/25/2007SYNC_MASTER=T9_NOME
051-7261
9223
A.0.0
LAN_ENERGY_DET
=PP3V3_S0_SB_GPIO
PP1V5_S0_SB_VCC1_5_B
GLAN_COMP
PP3V3_G3_SB_RTC
HDA_DOCK_EN_L
SB_INTVRMENSB_LAN100_SLP
SB_SM_INTRUDER_L
SB_RTC_RST_L
SB_RTC_X2SB_RTC_X1
TP_LAN_R2D<2>
LPC_AD<2>
LPC_AD<0>LPC_AD<1>
LPC_AD<3>
LPC_FRAME_L
EXTGPU_PWR_EN
PM_THRMTRIP_LCPU_THERMTRIP_R
CPU_A20M_L
CPU_DPSLP_LCPU_DPRSTP_L
CPU_PWRGD
CPU_IGNNE_L
CPU_INIT_LCPU_INTR
CPU_NMICPU_SMI_L
CPU_STPCLK_L
IDE_PDD<0>
IDE_PDD<2>IDE_PDD<1>
IDE_PDD<3>IDE_PDD<4>IDE_PDD<5>
IDE_PDD<7>IDE_PDD<6>
IDE_PDD<8>
IDE_PDD<10>IDE_PDD<9>
IDE_PDD<12>IDE_PDD<11>
IDE_PDD<13>
IDE_PDD<15>IDE_PDD<14>
IDE_PDA<0>IDE_PDA<1>IDE_PDA<2>
IDE_PDCS3_LIDE_PDCS1_L
IDE_PDIOW_LIDE_PDIOR_L
IDE_PDDACK_LIDE_IRQ14IDE_PDIORDYIDE_PDDREQ
=PP1V05_S0_SB_CPU_IO
=PP3V3_S0_SB_GPIO
CPU_FERR_L
SB_A20GATE
TP_LPC_DRQ0_L
SB_RCIN_L
TP_SB_TP8
TP_LAN_D2R<2>
SATA_A_D2R_P
TP_SB_SATALED_L
SATA_A_R2D_C_PSATA_A_R2D_C_N
SATA_B_D2R_PSATA_B_D2R_N
TP_HDA_DOCK_RST_L
TP_LAN_R2D<0>
TP_LAN_RSTSYNC
TP_LAN_D2R<0>
TP_LAN_R2D<1>
SATA_B_R2D_C_NSATA_B_R2D_C_P
SATA_C_D2R_PSATA_C_D2R_N
SATA_C_R2D_C_NSATA_C_R2D_C_P
SB_CLK100M_SATA_PSB_CLK100M_SATA_N
SATA_RBIAS_PSATA_RBIAS_N
HDA_BIT_CLK_RHDA_SYNC_R
HDA_RST_L_R
HDA_SDOUT_R
HDA_SYNCHDA_BIT_CLK
HDA_RST_L
HDA_SDOUT
SATA_A_D2R_N
TP_HDA_SDIN1
TP_ENET_GLAN_CLK
TP_LAN_D2R<1>
HDA_SDIN0
TP_HDA_SDIN3TP_HDA_SDIN2
U2300
AF13
AG26
AG29
AA4
AA1
AB3
Y6
Y5
V1
U2
T4
V6
V5
U1
V2
U6
V3
T1
V4
T5
AB2
T6
T3
R2
Y2
W5
W4
W3
AF26
AE26
AD24
E5
F5
G8
F6
C4
B24
D25
C25
AH21
AJ16
AE10
AG14
AE14
AJ17
AH17
AH15
AD13
AE13
AJ15
Y3
AF27
AE24
AC20
AD22
AF25
Y1
AD21
D22
C21
B21
C22
D21
E20
C20
G9
E6
AD23
AH14
AF23
AG25
AF24
AF6
AF5
AH5
AH6
AG3
AG4
AJ4
AJ3
AF2
AF1
AE4
AE3
AB7
AC6
AF10
AG2
AG1
AG28
AA24
AE27
AA23 R23041
2
R23021
2
R23011
2
R23061
2
R23081 2
R23001
2
R23031
2
R23101
2
R23051
2
R23091
2
R2313 1 2
R2314 1 2
R2315 1 2
R2316 1 2
R23111
2
25
27
28
27
25
23
26
27
26
23
8
24
87
26
7
8
8
86
86
86
86
Page 24
SPI_CS1*
PETN1
PERP1
OC4*/GPIO43
OC5*/GPIO29
OC6*/GPIO30
OC7*/GPIO31
OC8*
OC9*
SPI_MOSI
OC0*
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
PERN5
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI_CLKN
DMI_CLKP
PETP1
USBP9N
USBP9P
PERN2
USBP7N
USBP7P
USBP8N
USBP8P
PETN2
USBP6N
USBP6P
PERP3
USBP4N
USBP4P
USBP5N
USBP5P
PETN3
PETP3
USBP3N
USBP3P
PERN4
PERP4
USBP1N
USBP1P
USBP2N
USBP2P
PETN4
PETP4
USBP0N
USBP0P
PERP5
SPI_MISO
USBRBIAS
USBRBIAS*
PETP5
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
SPI_CLK
SPI_CS0*
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI_IRCOMP
DMI_ZCOMP
PERN1
PERP2
PETP2
PERN3
PETN5
PCI_EXPRESS
DIRECT MEDIA INTERFACE
SPI
USB
(2 OF 6)
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
OUT
OUT
IN
IN
OUT
OUT
BI
BI
BI
BI
AD4
AD5
AD9
PIRQF*/GPIO3
PIRQE*/GPIO2
AD13
PME*
PCIRST*
GNT2*/GPIO53
C/BE2*
PIRQG*/GPIO4
SERR*
PIRQA*
AD1
REQ1*/GPIO50
C/BE3*
AD11
C/BE1*
AD25
AD26
AD0
AD2
DEVSEL*
AD18
AD21
PAR
GNT0*
AD7
GNT1*/GPIO51
C/BE0*
STOP*
AD20
AD16
GNT3*/GPIO55
TRDY*
IRDY*
AD22
PIRQC*
REQ2*/GPIO52
AD19
PCICLK
PLOCK*
AD15
PIRQB*
PIRQH*/GPIO5
PLTRST*
AD3
AD6
AD8
FRAME*
AD14
AD12
AD10
REQ3*/GPIO54
PIRQD*
AD17
PERR*
REQ0*
AD31
AD27
AD28
AD30
AD29
AD24
AD23
(3 OF 6)
INTERRUPT I/F
PCI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
BI
BI
BI
OUT
IN
BI
BI
IN
IN
IN
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NOTE: USBP[0-9]P/N have internal 15K pull-downs.
IR
Bluetooth
External D / WWAN
External A
Geyser Trackpad/Keyboard
External B
ExpressCard
AirPort (PCIe Mini-Card)
Camera
External C
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
EHCI0
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PU
INT PU
INT PU
INT PU
EHCI1
INT PD
INT PD
INT PD
Spares
ExpressCard
FireWire
(AirPort)
Ethernet
(x2-capable,pull HDA_SYNChigh for x2)
SPI_CS1# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)
GNT0# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
1
GNT0#
0
NOTE:
SPI
PCIe Mini Card
Yukon-PCIENineveh-GLCI
LPC
I/F
SB BOOT BIOS SELECT
selects SPI ROM by default.R2415 pull-down on GNT0#
Provide a pull-down on this GPIO if not used.
INT PU
INT PU
INT PU
INT PU
INT PU
FireWire INT*
rises, or PCIe ports 5 & 6 will be disabled.If used, ensure GNT2# is not low when PWROK
enabled only when PCIRST# = 0 and PWROK = 1NOTE: GNT[0-3]# have internal 20K pull-ups
MF-LF
5%10K
402
1/16W
1/16WMF-LF402
10K5%
10K
402
5%1/16WMF-LF
10K1/16W
402MF-LF
5%
MF-LF402
5%10K1/16W
402
5%1/16WMF-LF
10K
402
1/16W
10K
MF-LF
5%
10K
MF-LF402
1/16W5%
BGA
ICH8M
OMIT
16 84
16 84
16 84
16 84
16 84
16 84
16 84
16 84
16 84
16 84
16 84
16 84
16 84
16 84
16 84
16 84
30 88
30 88
1% 402MF-LF1/16W
24.9
43 86
43 86
34 86
34 86
44 86
44 86
44 86
44 86
7 80 86
7 80 86
80 86
80 86
80 86
80 86
34 86
34 86
34 86
34 86
34 86
34 86
22.6
MF-LF402
1%1/16W
34 87
34 87
34 87
34 87
35 87
35 87
35 87
35 87
56 86
56 86
56 86
56 86
ICH8MBGA
OMIT
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
38 87
24 87
24 87
24 87
24 38 87
24 87
24 38 87
24 87
38 87
38 87
38 87
38 87
24 38 87
38 87
7 28
24 38 87
24 38 87
24 87
24 38 87
24 38 87
24 38 87
24 38 87
7 9 28 79
30 88
24 87
5%
402MF-LF1/16W
10K
402
1/16W5%
MF-LF
10K
402
5%1/16WMF-LF
1K
8.2K8.2K8.2K8.2K8.2K8.2K8.2K8.2K
8.2K8.2K8.2K
8.2K
8.2K8.2K8.2K
8.2K
24 87
8.2K
13 43
13
13 34
34 46
34
24 42
78
38 87
42 86
13
7 47
13 79
8.2K
13
13 36
13
SYNC_DATE=01/25/2007
051-7261
9224
A.0.0
SYNC_MASTER=T9_NOME
SB PCI, PCIe, DMI, USB
WOW_EN
INT_PIRQD_LINT_PIRQC_L
INT_PIRQA_LINT_PIRQB_L
PCI_AD<31>PCI_AD<30>PCI_AD<29>PCI_AD<28>PCI_AD<27>PCI_AD<26>PCI_AD<25>
PCI_AD<23>PCI_AD<24>
PCI_AD<22>PCI_AD<21>PCI_AD<20>PCI_AD<19>
PCI_AD<17>PCI_AD<18>
PCI_AD<16>PCI_AD<15>PCI_AD<14>
PCI_AD<12>PCI_AD<13>
PCI_AD<11>PCI_AD<10>PCI_AD<9>
PCI_AD<7>PCI_AD<8>
PCI_AD<6>PCI_AD<5>PCI_AD<4>PCI_AD<3>
PCI_AD<1>PCI_AD<2>
PCI_AD<0>
ODD_PWR_EN_LDVI_HOTPLUG_DET
INT_PIRQE_LINT_PIRQF_L
PLT_RST_LPCI_CLK33M_SB
PCI_TRDY_LPCI_FRAME_L
PCI_STOP_LPCI_SERR_LPCI_LOCK_L
PCI_DEVSEL_LPCI_PERR_L
PCI_RST_LPCI_PARPCI_IRDY_L
PCI_C_BE_L<3>
PCI_C_BE_L<1>PCI_C_BE_L<0>
PCI_C_BE_L<2>
ODD_RST_5VTOL_L
PCI_REQ2_L
PCI_FW_REQ_L
TP_SB_GPIO55
TP_SB_GPIO51PCI_REQ1_L
TP_SB_GPIO53
TP_PCI_PME_L
BOOT_LPC_SPI_L
PCI_FW_GNT_LMAKE_BASE=TRUE
=PP3V3_S5_SB_USB
SB_GPIO40USB_EXTA_OC_L
EXTGPU_LVDS_EN
USB_EXTC_OC_L
SB_GPIO30
TP_PCIE_A_R2D_C_P
PCI_REQ1_L
PCI_TRDY_L
INT_PIRQE_LINT_PIRQD_L
INT_PIRQB_LINT_PIRQA_L
PCI_REQ2_L
PCI_STOP_L
PCI_IRDY_LPCI_FRAME_L
PCI_FW_REQ_L
PCI_LOCK_L
INT_PIRQF_L
INT_PIRQC_L
ODD_PWR_EN_L
PCI_SERR_LPCI_DEVSEL_LPCI_PERR_L
=PP3V3_S0_SB_PCI
PP1V5_S0_SB_VCC1_5_B
USB_RBIAS
DMI_IRCOMP_R
TP_SPI_CE_R_L<1>
TP_PCIE_A_R2D_C_NTP_PCIE_A_D2R_P
PM_LATRIGGER_L
USB_EXTB_OC_LEXCARD_OC_L
SPI_SI_R
USB_EXTD_OC_L
PCIE_MINI_D2R_N
TP_PCIE_B_D2R_N
TP_PCIE_B_R2D_C_N
TP_PCIE_EXCARD_D2R_PTP_PCIE_EXCARD_R2D_C_NTP_PCIE_EXCARD_R2D_C_P
TP_PCIE_FW_D2R_NTP_PCIE_FW_D2R_PTP_PCIE_FW_R2D_C_NTP_PCIE_FW_R2D_C_P
PCIE_MINI_D2R_P
SPI_SO
PCIE_MINI_R2D_C_P
PCIE_ENET_D2R_NPCIE_ENET_D2R_PPCIE_ENET_R2D_C_NPCIE_ENET_R2D_C_P
SPI_SCLK_RSPI_CE_R_L<0>
TP_PCIE_A_D2R_N
TP_PCIE_B_D2R_P
TP_PCIE_B_R2D_C_P
TP_PCIE_EXCARD_D2R_N
PCIE_MINI_R2D_C_N
USB_EXTC_P
USB_EXCARD_PUSB_EXTC_N
USB_EXCARD_NUSB_EXTB_PUSB_EXTB_NUSB_BT_P
USB_TPAD_PUSB_BT_N
USB_TPAD_NUSB_IR_PUSB_IR_N
USB_CAMERA_NUSB_CAMERA_P
USB_EXTD_PUSB_EXTD_NUSB_MINI_PUSB_MINI_NUSB_EXTA_PUSB_EXTA_N
SB_CLK100M_DMI_PSB_CLK100M_DMI_N
DMI_S2N_P<3>DMI_S2N_N<3>DMI_N2S_P<3>DMI_N2S_N<3>
DMI_S2N_P<2>DMI_S2N_N<2>DMI_N2S_P<2>DMI_N2S_N<2>
DMI_S2N_P<1>DMI_S2N_N<1>DMI_N2S_P<1>DMI_N2S_N<1>
DMI_S2N_P<0>DMI_S2N_N<0>DMI_N2S_P<0>DMI_N2S_N<0>
R24081
2
R24071
2
R24001
2
R24091
2
R24011
2
R24021
2
R24041
2
R24031
2
U2300 V27
V26
U29
U28
Y27
Y26
W29
W28
AB26
AB25
AA29
AA28
AD27
AD26
AC29
AC28
T26
T25
Y24
Y23
AJ19
AG16
AG15
AE15
AF15
AG17
AD12
AJ18
AD14
AH18
P27
M27
K27
H27
F27
D27
P26
M26
K26
H26
F26
D26
N29
L29
J29
G29
E29
C29
N28
L28
J28
G28
E28
C28
C23
B23
E22
F21
D23
G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2
F3
F2
R24131 2
R24141 2
U2300D20
E19
A12
E16
A14
G16
A15
B6
C11
A9
D11
B12
D19
C12
D10
C7
F13
E11
E13
E12
D8
A6
E8
A20
D6
A3
D17
A21
A19
C19
A18
B16 C17
E15
F16
E17
D16
A17
D7
C18
F18
C10
C8
D9
B10
G6
A7
F9
B5
C5
A10
F8
G11
F12
B3
B7
AG24
G7
A4
E18
B19
A11
F10
C16
C9
R24051
2
R24062
1
R24151
2
R2423 1 2R2424 1 2R2425 1 2R2426 1 2R2427 1 2R2428 1 2R2430 1 2R2429 1 2
R2432 1 2R2431 1 2R2433 1 2
R2437 1 2
R2439 1 2
R2438 1 2
R2436 1 2
R2440 1 2R2441 1 2R2442 1 2
87
87
87
87
87
87
87
87
87
27
87
38
87
38
87
87
87
38
38
38
38
87
87
87
42
38
38
38
26
8
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
8
23
86
34
34
34
34
Page 25
OUT
OUT
BI
IN
BI
IN
IN
SMBALERT*/GPIO11
STP_PCI*/GPIO15
BMBUSY*/GPIO0
SYS_RESET*
SUS_STAT*/LPCPD*
QRT_STATE0/GPIO27
THRM*
SMLINK0
GPIO12
SPKR
SDATAOUT1/GPIO48
QRT_STATE1/GPIO28
SLP_S5*
GPIO20
GPIO8
WAKE*
CL_CLK1
BATLOW*
PWROK
SLOAD/GPIO38
SATA2GP/GPIO36
SERIRQ
RI*
CL_DATA1
SLP_S4*
EC_ME_ALERT/GPIO14
TACH0/GPIO17
CLK14
SCLOCK/GPIO22
SATA3GP/GPIO37
SATACLKREQ*/GPIO35
STP_CPU*/GPIO25
WOL_EN/GPIO9
LINKALERT*
SLP_S3*
RSMRST*
TACH3/GPIO7
CLKRUN*/GPIO32
GPIO18
LAN_RST*
CL_VREF1
S4_STATE*/GPIO26
TACH1/GPIO1
TACH2/GPIO6
SATA1GP/GPIO19
SDATAOUT0/GPIO39
SATA0GP/GPIO21
MCH_SYNC*
DPRSLPVR/GPIO16
VRMPWRGD
TP3
TP7
CL_RST*
ME_EC_ALERT/GPIO10
SLP_M*
MEM_LED/GPIO24
PWRBTN*
SUSCLK
CL_VREF0
CK_PWRGD
CLPWROK
CL_DATA0
CL_CLK0
CLK48
SMBCLK
SMBDATA
SMLINK1
MISC
SYS GPIO
SMB
CLOCKS
POWER MGT
CONTROLLER LINKGPIO
SATA
GPIO
(4 OF 6)
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
BI
BI
OUT
IN
IN
IN
IN
IN
OUT
OUT
IN
BI
BI
OUT
BI
BI
BI
IN
IN
OUT
OUT
OUT
IN
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
If ME/AMT is not used, short CLPWROK to PWROK.
PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,
have been up for at least 1ms.
PM_LAN_ENABLE must remain deasseteduntil VccCL3_3, VccLAN3_3 and VccLAN1_05
INT PU
NOTE: ICH CLPWROK input must be PWRGD signal for
INT PD
INT PD
INT PU
Test access required
AT BOOT/RESET FOR STRAPPING FUNCTIONNOTE: DPRSLPVR HAS INT 20K PD ENABLED
INT PU
for XOR chain testing.
PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.
See note below
7 29 30
7 29 30
7 45 47
34 35
7 45 47
45
13 45
5%1/16WMF-LF402
10K
402
05%1/16WMF-LF
ARB_ONLY
MF-LF1/16W5%10K
402
MF-LF1/16W5%0
NOSTUFF
402
5%10K
MF-LF402
1/16W
402
10K5%
MF-LF1/16W
1K5%1/16WMF-LF402
402
8.2K5%
1/16WMF-LF
402
5%10K1/16WMF-LF
402
1/16W
8.2K5%
MF-LF
OMIT
BGAICH8M
30 88
30 88
46
7 36 40 45 66
402
1/16W5%1K
NO_REBOOT_MODE
MF-LF
7 45 46
7 16 59 83
7 9 28
25 45
7 45
45
48 86
48 86
7 45 46 47
7 28 45
7 16
7 28
25 38
7 16
7 45 66
29
9
16 87
16 87
402
3.24K1%1/16WMF-LF
402
4531%1/16WMF-LF
402
16V10%
0.1uF
X5R
402
1/16W1%
MF-LF
4.53K
1%1/16WMF-LF402
32.4K
402
16V10%
X5R
0.1uF
16 87
25
100K1/16W
402MF-LF
5%
48 86
48 86
25
1/16W
10K
MF-LF
1%
402
5%
MF-LF1/16W
8.2K
402
MF-LF
10K
1/16W1%
402
10K
MF-LF1/16W5%
402
7 25 47
25
25 28
29
MF-LF1/16W5%10K
402
402MF-LF1/16W
10K5%
10K
MF-LF
5%1/16W
402
402MF-LF1/16W5%8.2K
1/16W
8.2K5%
MF-LF402
7 45
1%
MF-LF1/16W
10K
402
1%
MF-LF1/16W
10K
402
10K
MF-LF402
5%1/16W
402
1/16W5%
MF-LF
10K1/16WMF-LF
10K
402
5%
79
5%1/16WMF-LF
10K
402
100K
402
5%1/16WMF-LF
10K
1/16WMF-LF
1%
40210K
1/16WMF-LF
1%
402
MF-LF1/16W5%100K
402
MF-LF
10K
1/16W1%
40210K
1/16WMF-LF
1%
402
A.0.0
25 92
051-7261
SYNC_MASTER=M75_MLB SYNC_DATE=04/02/2007
SB Pwr Mgt, GPIO, Clink
ARB_DETECT_L
TP_PM_SLP_M_L
CLINK_NB_CLK
SB_GPIO14_CL2
SB_CLINK_VREF1
=PP3V3_S5_SB_GPIO
SB_SDATAOUT<0>
SB_SCLOCK
SB_GPIO18
PM_STPCPU_L
PM_LAN_ENABLE
PM_RSMRST_L
CLK_PWRGD
PCI_PME_FW_L
=PP3V3_S5_SB
SATA_B_PWR_EN_L
SB_SPKR
SMC_WAKE_SCI_L
TP_SB_TP3
SB_SDATAOUT<1>
SB_SLOADSB_SATA_CLKREQ_LFWH_MFG_MODESATA_B_PWR_EN_L
TP_SB_GPIO20
EXTGPU_RST_LLAN_PHYPC
SMC_RUNTIME_SCI_LSB_GPIO6
TP_SB_TP7
PCI_PME_FW_L
PM_CLKRUN_L
PCIE_WAKE_LINT_SERIRQ
PM_THRM_L
SATA_B_DET_L
TP_CLINK_WLAN_DATA
SB_GPIO10_CL1
WOL_EN
PM_SLP_S3_L
SB_CLK14P3M_TIMER
VR_PWRGD_CLKEN
PM_SUS_STAT_L
NB_SB_SYNC_L
LINDACARD_GPIO
PM_BMBUSY_L
CLINK_NB_DATA
TP_CLINK_WLAN_CLK
PM_BATLOW_L
PM_S4_STATE_L
PM_SB_PWROK
PM_SLP_S5_LTP_PM_SLP_S4_L
PM_SYSRST_L
SMB_ME_DATA
SMB_DATA
=PP3V3_S0MWOL_SB_CLINK0
SB_GPIO14_CL2
LAN_PHYPC
SB_GPIO10_CL1
PM_BATLOW_L
PM_RI_L
PM_DPRSLPVR
SMB_CLK
SMB_ME_CLK
PM_PWRBTN_L
TP_CLINK_WLAN_RESET_L
SUS_CLK_SB
SB_CLK48M_USBCTLR
=PP3V3_S5_SB_CLINK1
CLINK_NB_RESET_L
PM_RI_L
=SB_CLINK_MPWROK
PM_STPPCI_L
RSVD_EXTGPU_LVDS_EN
SB_CRT_TVOUT_MUX_L
=PP3V3_S0_SB_GPIO
SB_GPIO36
SB_CLINK_VREF0
=PP3V3_S5_SB
LINDACARD_GPIO
FWH_MFG_MODEARB_DETECT_L
SB_GPIO6
=PP3V3_S0_SB_GPIO
EXTGPU_RST_L
R25101
2
R25151
2
R25161
2
R25111
2
R25121
2
R25021
2
R25041
2
R25001
2
R25071
2
R25061
2
R25051
2
U2300
AE21
AG12
E1
F23
AE18
F22
AF19
AJ23
D24
AH23
AG9
G5
AH11
E3
AJ14
AF22
AC19
AH12
AE11
AE16
AH20
AG21
AJ13 AJ24
AJ27
C2
AE23
AH25
AD16
AF17
AG27
AH27
AJ12
AJ10
AF11
AG11
AG13
AG10
AJ11
AD10
AF12
AF9
AJ25
AG23
AF21
AD18AG22
AJ26
AD19
AC17
AE19
AD9
AG18
AE20
F4 D3
AD15
AG8
AJ8
AJ9
AH9
AC13
AJ21
AJ22
AJ20
AE17
AG19
R25261
2
R25271
2
C2500 1
2
R25291
2
R25281
2
C2501 1
2
R25231
2
R25361 2
R25441 2
R25451 2
R25251
2
R25342
1
R25521
2
R25501
2
R25531
2
R25511
2
R25981 2
R25461 2
R25322
1
R25332
1
R25352
1
R25472
1
R25241
2
R25301 2
R25311 2
R25142
1
R25961 2
R25971 2
27
25
27
47
25
38
25
45
23
25
25
23
28
25
87
8
25
8
25
25
25
25
25
36
8
25
25
25
25
25
8
8
87
8
7
25
25
25
8
25
Page 26
VSS
VSS_NCTF
VSS
(5 OF 6)
VCC1_5_B
V5REF_SUS
VCCDMIPLL
VCC_DMI
VCC3_3
VCC1_05
V5REF
VCCCL1_5
VCCGLANPLL
VCC3_3
VCC1_5_A
VCC3_3
VCCHDA
VCCSUS1_5
VCCSUS3_3
V_CPU_IO
VCC3_3
VCCSUSHDA
VCC1_5_A
VCC3_3
VCCSATAPLL
VCCGLAN3_3
VCCSUS3_3
VCCLAN3_3
VCCCL1_05
VCCSUS1_05
VCCSUS1_5
VCCSUS3_3
VCCA3GP
VCCGLAN1_5
VCCCL3_3
VCCLAN1_05
VCC1_5_A24
VCC1_5_A
VCCRTC
VCC1_5_A
VCCUSBPLL
VCC1_5_A
VCC1_5_A
VCC1_5_A
GLAN POWER
USB CORE
ATX
ARX
(6 OF 6)
VCCPSUS
IDE
CORE
VCCP
CORE
PCI
VCCPUSB
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
6 uA S0-G3
1 mA
1 mA S0-S5
657 mA
Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.
Current figures provided assume 1.5V.
depending on VIO of HD Audio interface.VccHDA and VccSusHDA can be 1.5V or 3.3VNOTE:
1130 mA
23 mA
50 mA
1 mA
(VCC3_3 total)
442 mA
117 mA S0,
11 mA S0,
44 mA S3-S5
1 mA S3-S5
(VCCSUS3_3 total)
32 mA1080 mA
47 mA
(VCC1_5_A total)
63 mA M1 & WOL19 mA S0,
10 mA
23 mA
80 mA
1 mA51 mA M1 & WOL19 mA S0,
1uF6.3VCERM
10%
402 402CERM10V20%0.1uF
ICH8MBGA
OMIT
BGAICH8M
OMIT
SYNC_MASTER=T9_NOME
051-7261
9226
A.0.0
SYNC_DATE=01/25/2007
SB Power & Ground
=PP3V3_S0_SB_VCC3_3_PCI
=PP1V5_S0_SB_VCCUSBPLL
PP3V3_G3_SB_RTC
TP_VCCLAN1_05_INTERNAL_REG1TP_VCCLAN1_05_INTERNAL_REG2
TP_VCCSUS1_05_INTERNAL_REG2
TP_VCCSUS1_5_INTERNAL_REG2
TP_VCCSUS1_05_INTERNAL_REG1
TP_VCCCL1_05_INTERNAL_REG
=PP3V3_S0_SB_VCCGLAN3_3
PP1V5_S0_SB_VCCSATAPLL
=PP3V3_S0_SB_VCC3_3_DMI
=PP3V3_S5_SB_3V3_VCCSUSHDA
=PP3V3_S0_SB_VCC3_3_SATA
TP_VCCSUS1_5_INTERNAL_REG1
=PP3V3R1V5_S0_SB_VCCHDA
PP1V5_S0_SB_VCCGLANPLL
PP1V5_S0_SB_VCCDMIPLL
PP5V_S5_SB_V5REF_SUS
=PP1V5_S0_SB_VCCGLAN1_5
=PP3V3_S0MWOL_SB_VCCCL3_3
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
=PP1V5_S0_SB_VCC1_5_A
=PP3V3_S0MWOL_SB_VCCLAN3_3
=PP3V3_S5_SB_VCCSUS3_3_USB
=PP3V3_S5_SB_VCCSUS3_3
=PP1V5_S0_SB_VCC1_5_A_ATX
=PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V25_S0_SB_DMI
=PPVCORE_S0_SB
VCCCL1_5V
PP5V_S0_SB_V5REF
PP1V5_S0_SB_VCC1_5_B
=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S0_SB_VCC3_3_VCCPCORE
=PP1V05_S0_SB_CPU_IO
U2300A23
A5
AC26
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15AC27
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
AD17
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
AD20
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
AD28
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
AD29
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
AD3
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
AD4
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AD6
AB6
AD5
U4
W24
AE1
AA2
AE12
AE2
AE22
AD1
AE25
AE5
AE6
AE9
AF14
AF16
AA7
AF18
AF3
AF4
AG5
AG6
AH10
AH13
AH16
AH19
AH2
A25
AF28
AH22
AH24
AH26
AH3
AH4
AH8
AJ5
B11
B14
AB1
B17
B2
B20
B22
B8
C24
C26
C27
C6
D12
AB24
D15
D18
D2
D4
E21
E24
E4
E9
F15
E23
AC11
F28
F29
F7
G1
E2
G10
G13
G19
G23
G25
AC14
G26
G27
H25
H28
H29
H3
H6
J1
J25
J26
AC25
J27
J4
J5
K23
K28
K29
K3
K6
K7
L1
A1
A2
B1
B29
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
U2300
A16
T7
G4
AC23
AC24
A13
B13
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
C13
U18
V17
V14
V11
U11
V18
V16
V12
C14
D14
E14
F14
G14
L11
L12
AE7
AF7
AC10
AC9
AA5
AA6
G12
G17
H7
AC7
AD7
F1
AG7
L6
L7
M6
M7
W23
AH7
AJ7
AC1
AC2
AC3
AC4
AC5
AA25
AA26
E27
F24
F25
G24
H23
H24
J23
J24
K24
K25
AA27
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
AB27
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
AB28
W25
V24
U25
Y25
V25
V23
AB29
D28
D29
E25
E26
AF29
AD2
W6
W7
Y7
A8
B15
B18
B4
B9
C15
D13
AC8
D5
E10
E7
F11
AD8
AE8
AF8
AA3
U7
V7
W1
AE28
AE29
G22
A22
F20
G21
R29
B27
A27
B28
B26
A26
B25
A24
AC12
F17
G18
F19
G20
AD25
AJ6
J6
AF20
AC16
J7
C3
AC18
P1
P2
P3
P4
P5
R1
R3
R5
R6
AC21
AC22
AG20
AH28
P6
P7
C1
N7
AD11
D1
C2600 1
2
C26011
2
28
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
24
27
23
8
8
23
8
27
8
8
8
8
27
27
27
27
8
8
8
8
8
8
8
8
8
8
27
23
8
8
8
Page 27
NC
NC
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
PLACEMENT NOTE:PLACE C2703 < 2.54MM OF PIN A16..T7 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARYDISTRIBUTED BETWEEN AA25..V23
837 mA
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
PLACE CAPS NEAR PINS AC18..AH2844 mA S3-S5
117 mA S0 /
ICH VCCGLANPLL Filter
PLACEMENT NOTE:PLACE C2732 NEAR PIN A24
PLACE C2736 NEAR PIN B27..A26
PLACE CAPS < 2.54MM OF SB ON SECONDARYOR 3.56MM ON PRIMARY NEAR PIN AJ6
38 mA S0 / 114 mA M1 & WOL
(ICH INTEL HDA SUSPEND 3.3V/1.5V PWR)ICH VCCSUSHDA BYPASS
1 mA S3-S511 mA S0 /
32 mA(@ 1.5V)
(@ 1.5V)
ICH USB/VCCSUS3_3 BYPASS
0.6 uA G3
Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.
(ICH IO,LOGIC 1.5V PWR)
ICH VCCSUS3_3 BYPASS
442 mA
(VCCSUS3_3 Total)
PLACEMENT NOTE:
P6..R6
PLACEMENT NOTE:PLACE CAPS NEAR PIN AD25 OF SB
(ICH SUSPEND 3.3V PWR)
PLACE CAP NEAR PINSPLACEMENT NOTE:
(ICH SUSPEND USB 3.3V PWR)
ICH VCCRTC BYPASS(ICH RTC 3.3V PWR)
1080 mA
(VCC1_5_A Total)
657 mA
80 mA
ICH VCC1_5_B BYPASS
47 mA
33 mA
(ICH SATA PLL PWR)
23 mA
(ICH DMI PLL PWR)ICH VCCDMIPLL Filter
47 mA
23 mA
PLACEMENT NOTE:PLACE CAPS < 2.54MM OF SB ONSECONDARY SIDE OR 3.56MM ON PRIMARY
PLACEMENT NOTE:
PLACEMENT NOTE:
1 mA
(VCC3_3 Total)
3.56MM ON PRIMARY NEAR PINS AA3...Y7 PLACE < 2.54MM OF SB ON SECONDARY OR
PLACEMENT NOTE:PLACE < 2.54MM OF SB ON SECONDARYOR 3.56MM ON PRIMARY NEAR PIN AD2
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARYOR 3.56MM ON PRIMARY NEAR PIN AD11
PLACE < 2.54MM OF SB ON SECONDARYOR 3.56MM ON PRIMARY NEAR PIN AC12
PLACEMENT NOTE:
NEAR PINS A8 ... F11DISTRIBUTE IN PCI SECTION OF SB
OR 3.56MM ON PRIMARY NEAR PIN AF29PLACE CAP < 2.54MM OF SB ON SECONDARY
PLACEMENT NOTE:
PLACEMENT NOTE:
ICH VCCHDA BYPASS(ICH INTEL HDA CORE 3.3V/1.5V PWR)
ICH PCI/VCC3_3 BYPASS(ICH PCI I/O 3.3V PWR)
(ICH IDE I/O 3.3V PWR)ICH IDE/VCC3_3 BYPASS
(ICH LAN I/F BUFFER 3.3V PWR)ICH VCC_PAUX/VCCLAN3_3 BYPASS
PLACE CAP UNDER SB NEAR PINS F19 AND G20
PLACEMENT NOTE:
PLACEMENT NOTE:PLACE CAPS AT EDGE OF SB
ICH V_CPU_IO BYPASS(ICH CPU I/O 1.05V PWR)
50 mA
1 mA
1130 mA
10 mA
3.56MM ON PRIMARY NEAR PIN AC1..AC5
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACE NEAR PINS AC23,AC24 OF SB
PLACEMENT NOTE:PLACE C2715 NEAR PIN D1 OF SB
3.56MM ON PRIMARY NEAR PINS F1..M7
ICH USB CORE/VCC1_5_A BYPASS
PLACE < 2.54MM OF SB ON SECONDARY OR
(ICH USB CORE 1.5V PWR)
PLACEMENT NOTE:PLACE < 2.54MM OF SB ON SECONDARY OR
PLACEMENT NOTE:
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PINS AE7..AJ7PLACE < 2.54MM OF SB ON SECONDARY OR
ICH VCC1_5_A/ATX BYPASS(ICH LOGIC&IO[ATX] 1.5V PWR)
(ICH LOGIC&IO[ARX] 1.5V PWR)ICH VCC1_5_A/ARX BYPASS
PLACEMENT NOTE:
ICH VCCSATAPLL Filter
PLACEMENT NOTE:
1 mA S0-S5
1 mA
(ICH Reference for 5V Tolerance on Core Well Inputs)ICH V5REF Filter & Follower
ON SECONDARY SIDE OR 3.56MM ON PRIMARYPLACE C2704 < 2.54MM OF PIN G4 OF SB
1 mA S0-S5
(ICH Reference for 5V Tolerance on Resume Well Inputs)ICH V5REF_SUS Filter & Follower
ICH VCCUSBPLL BYPASS(ICH USB PLL 1.5V PWR)
(ICH CORE 1.05V PWR)ICH CORE/VCC1_05 BYPASS
OR 3.56MM ON PRIMARY NEAR PIN AE29PLACE < 2.54MM OF SB ON SECONDARY
PLACE C2700 & C2705-07 < 2.54MM OF SB
(ICH GLAN PLL PWR)
CASE-B2
20%
POLY2.5V
220UF
CRITICAL
0.1UF10%16V
402X5R
603
5%
MF-LF1/10W
1
603CERM
20%6.3V
4.7UF
X5R402
16V10%0.1UF
BAT54DWSOT-363
SOT-363BAT54DW
1.0UH-0.5A
1210
603
10UF20%
6.3VX5R
402
1UF10V10%
X5R
6.3VCERM402
10%1UF
6.3V20%
CERM1603
2.2uF
4.7uF
603CERM
20%6.3V
6.3V20%
603CERM
4.7uF
0.1UF10%16V
402X5R
X5R402
16V10%0.1UF
0805
10UH-100MA
X5R402
16V10%0.1UF
6.3V
22UF20%
CERM-X5R805-3
0.1UF10%16V
402X5R
0
1/16WMF-LF
5%
402
5%1/16W
100
402MF-LF
402
5%1/16WMF-LF
10
X5R402
16V10%
0.1UF
0805-1
FERR-330-OHM-1.5A
20%22UF
CERM-X5R6.3V
805-3CERM-X5R6.3V20%22UF
805-3 603
20%6.3VCERM1
2.2UF
10%0.01UF16VCERM402
X5R6.3V20%
10UF
603
10%1UF
402CERM6.3V
1UF10%
402CERM6.3V
0.1UF10%16V
402X5R
0.1UF10%16V
402X5R
X5R402
16V10%0.1UF
0.1UF10%16V
402X5R
X5R402
16V10%0.1UF
0.1UF10%16V
402X5R
0.1UF10%16V
402X5R
16V
402X5R
10%0.1UF
10%16V
402X5R
0.1UF
X5R402
16V10%0.1UF
X5R402
16V10%0.1UF
X5R402
16V10%0.1UF0.1UF
10%16V
402X5R
051-7261 A.0.0
9227
SB DecouplingSYNC_MASTER=T9_NOME SYNC_DATE=01/25/2007
PP1V5_S0_SB_VCC1_5_B
VOLTAGE=1.5VMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm
=PP1V5_S0_SB
=PP1V5_S0_SB_VCCGLAN1_5
=PP5V_S5_SB
=PP1V5_S0_SB_VCC1_5_A_ATX
=PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
=PP1V5_S0_SB_VCCUSBPLL
=PPVCORE_S0_SB
=PP1V05_S0_SB_CPU_IO
=PP3V3_S0MWOL_SB_VCCLAN3_3=PP3V3_S0MWOL_SB_VCCCL3_3
=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S0_SB_VCC3_3_SATA
=PP3V3_S0_SB_VCC3_3_DMI
=PP3V3R1V5_S0_SB_VCCHDA
=PP3V3_S5_SB_3V3_VCCSUSHDA
=PP3V3_S0_SB_VCC3_3_PCI
=PP3V3_S5_SB
VOLTAGE=5VMIN_NECK_WIDTH=0.25MM
PP5V_S5_SB_V5REF_SUSMIN_LINE_WIDTH=0.3MM
=PP5V_S0_SB=PP3V3_S0_SB
PP1V5_S0_SB_VCCDMIPLL_F
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MMVOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MMPP1V5_S0_SB_VCCSATAPLL_F
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MMVOLTAGE=1.5V
PP1V5_S0_SB_VCCDMIPLL
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MMVOLTAGE=1.5V
PP1V5_S0_SB_VCCSATAPLL
=PP3V3_S5_SB_VCCSUS3_3_USB
PP3V3_G3_SB_RTC
=PP3V3_S5_SB_VCCSUS3_3
PP1V5_S0_SB_VCCGLANPLL
=PP1V25_S0_SB_DMI
VOLTAGE=5V
PP5V_S0_SB_V5REFMIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.25MM
C2700 1
2
R27001 2
C2703 1
2
C2704 1
2
L2700
1 2
C27051
2
C27061
2
C2707
C27011
2
C2708 1
2
C2717
C27141
2
C27151
2
C27181
2
C27191
2
C27211
2
C27231
2
C27251
2
C27261
2
C27271
2
C27281
2
C27291
2
C27301
2
C27341
2
C27311
2
C27121
2
C2724 1
2
C27221
2
D27021
6
5
D27024
3
2
L2703
1 2
C2735 1
2
C27111
2
C27321
2
C27361
2
C27331
2
C27411
2
C27381
2
L2702
1 2
C27371
2
C27391
2
C27021
2
R27351 2
R27022
1
R27012
1
26
26
28
24
26
26
26
26
26
23
26
26
26
26
26
26
26
26
25
26
26
26
26
23 8
26
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
26
8
8
26
26
8
23
8
26
8
26
Page 28
OUT
IN OUT
IN
NCNC
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTIN
OUT
OUT
OUT
OUTIN
IN
OUT
OUT
IN
A
B
Y132
A
B
Y132
IN
IN
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
threshold at approx .8 ms nominal
ON POWER UP:This delay ensures that GPU clocksrun before GPU is released from reset(RC should reach schmitt trigger
NOTE: R2800 and D2805 form the double- fault protection for RTC battery.
PWROK Circuit
PCI Reset Connections
ON POWER DOWN:This ensures that GPU is put into
and clocks are still running.reset while chip is still powered
System Reset "Button"
VRMPWRGD Inverter
Muxed GFX GPU Reset Support
NC
Platform Reset Connections
to solder a reset button.
NC
Unbuffered
NC
GPU_IOENABLE_RC is used to isolate
w/ 1K pullup on PM_ALL_GPU_PGOOD)
RTC Power Sources
on the board to short orit provides a set of padsThis part is never stuffed,
NC
SB RTC Crystal
CPU VCore ForcePSI
518S0487
Coin-Cell Connector
certain GPU signals from the restof the system. RC prevents glitchthat would otherwise be injected
reset edge and isolating FET Cgs.into isolated signals due to sharp
1/16W5%
MF-LF
20K
402
23
CERM
20%10V
0.1UF
402
6.3VCERM
1UF10%
402
10 13
MF-LF1/16W
1M
402
5%
7 25 45
10K
MF-LF
5%
402
1/16W
5%
402
1/16WMF-LF
1K
CERM
5%50V
402
12pF
5%50V
12pF
402CERM
32.768KSM-2
CRITICAL
0
MF-LF
5%1/16W
402
1/16WMF-LF
10M5%
402
7 9 24 79
1K
1/16W5%
MF-LF
ITP&XDP
402
SOT-363BAT54DW
402
1/16WMF-LF
100
5%
1/16W5%
0
MF-LF402
MF-LF402
5%1/16W
100
100
MF-LF
5%1/16W
402
10V20%
CERM
0.1UF
402
7 9 16 59
45 46 66
7 9 25
10V20%
CERM
0.1UF
402
MF-LF402
1/16W5%
0
7 16
7 47
7 45
34
7 68
SC70MC74VHC1G08
SC70MC74VHC1G08
SC70-5MC74VHC1G00
MF-LF
OMIT
5%01/10W
603
SILK_PART=SYS RST
38
402
0
5%1/16WMF-LF
38
402
1/16W5%
MF-LF
1007 24
79
78
59 10
59
7 25
402
1/16W5%
MF-LF
10K10K5%
402
1/16WMF-LF
CRITICAL
BM02B-ACHKS-GAN-TF-LF-SN-MM-RT-SM
1/16W
402
1K
MF-LF
5%
0.001UF
402CERM
10%50V
5%
402MF-LF
0
1/16W
35
30 79
0.1UF
402CERM10V20%
5%1/16W
10K
MF-LF402
16V
0.047UF10%
CERM402
1/16WMF-LF
402
1%24.3K
CRITICAL
74LVC2G132US8 CRITICAL
US874LVC2G132
25
23 66
EXTGPU_RST_HW
5%
MF-LF402
1/16W
0
EXTGPU_RST_SW
1/16WMF-LF
5%
402
0
7 23
10%1UF6.3V
402CERM
SYNC_DATE=03/19/2007
28
051-7261 A.0.0
92
SYNC_MASTER=M75_MLB
SB Misc
GPU_RESET_R_L
GPU_IOENABLE_RCMAKE_BASE=TRUE
MAKE_BASE=TRUECPU_PSI_L IMVP6_PSI_L
SB_RTC_X1_R
VR_PWRGD_CLKENALL_SYS_PWRGD
=PP3V3_S0_RSTBUF
RST_L_AND_GPU_PGOOD_LGPU_PGOOD_RC
VR_PWRGD_CLKEN_L
PM_ALL_GPU_PGOOD
SMC_LRESET_L
SB_SM_INTRUDER_L
SB_RTC_RST_L
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mm
VOLTAGE=3.3V
PP3V3_G3_SB_RTC
FW_PLT_RST_L
NB_RESET_L
LIO_PLT_RST_L
SB_RTC_X1
XDP_DBRESET_L PM_SYSRST_L
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.3 mmPPVBATT_G3_RTC_RMIN_NECK_WIDTH=0.2 mm
=PP3V42_G3H_SB_RTC
PPVBATT_G3_RTC
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mm
=PP3V3_S0_SB_PM
VR_PWRGOOD_DELAY
SB_RTC_X2
=PP3V3_S0_SB_PM
GPU_RESET_L
=GPU_DDC_ENABLE=GPU_HPD_ENABLE
PCI_FW_RST_L
=PP3V3_S5_SB_PM
DEBUG_RESET_L
PLT_RST_LMAKE_BASE=TRUE
LCDBKLT_PLT_RST_L
ENET_RESET_L
PM_SB_PWROK
EXTGPU_RST_L
EXTGPU_PWR_EN
RST_L_AND_GPU_PGOOD
PCI_RST_L
EXTGPU_RST_QUAL_L
=PP3V3_S0_RSTBUF
C2805 1
2
R28061 2
C28061
2
R28051
2
R28002 1
C28301
2
R28251
2
C28101 2
C28111 2
Y2810
24
13
R28101 2
R28111
2
R28261 2
D2805
1
4
6
3
5 2
R28621 2
R28631 2
R28641 2
R28601 2
C2840 1
2
C2880 1
2
R28811 2U2880
3
2
1
4
5
U2840
3
2
1
4
5
U2830
3
2
1
4
5
R28201
2
R28611 2
R28901 2
R28401
2
R28411
2
J2800
3
4
1
2
R28821 2
C28821
2
R28651 2
C288312
R28851 2
C28851
2
R28861
2
U28835
6
4
8
3
U28831
2
4
8
7
R28871 2
R28801 2
27
28
26
28 28 28
8
23
23
8
7
8
23
8
8
8
Page 29
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
OUT
IN
BI
OUT
OUT
IN
IN
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
VSS_PCI
CLKREQ_7*
CLKREQ_8*
GPU_STOP*
REF_0/FS_C/TEST_SEL
48M/FS_A
DOT_96/27M
DOT_96*/27M_SS
SRC_8*
SRC_8
PCI_5/FCT_SEL
PCIF_0/ITP_EN
VDD_PCI
VDD_48
THRM_PAD
SRC_4*
CLKREQ_3*
SRC_3
SRC_0/LCD_CLK
SRC_0*/LCD_CLK*
CPU_1_MCH*
CPU_1_MCH
CPU_ITP*/SRC_10*
CPU_ITP/SRC_10
VSS_SRC
VSS_REF
VSS_CPU
VSS_48
SDA
PCIF_1
PCI_4
PCI_3
PCI_2
PCI_1
VSS_A
XTAL_OUT
CLKREQ_6*
CLKREQ_5*
CLKREQ_4*
CLKREQ_1*
SCL
CPU_0
SRC_1
SRC_2*
SRC_2
SRC_4
SRC_5*
SRC_5
SRC_7*
SRC_7
SRC_6*
SRC_6
VDD_REF
CPU_0*
SRC_3*
CPU_STOP*
PCI_STOP*
XTAL_IN
VDD_A
FS_B/TEST_MODE
VDD_CPU
SRC_1*
CKPWRGD/PD*
VDD_SRC
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NOTE: Pin 53 was REF_1 on SLG8LP537.
(*) CLKREQ# internal pull-ups/downs only on SLG2AP101, not SLG8LP537.
Yukon PCIe 100MHz on SLG8LP537 or device is set to CK410M mode.
NEED TO CHECK CAP VALUE
(266.6)
FS_AFS_BFS_C
One 10uF cap per rail.
1
1
0
1
1
1
1
1
0
0
10
0 0
00
1
0
1
166.6
(333.3)
100.0
(400.0)
RSVD1
0
0 200.0
0
1 133.3
CPU MHz
CPU Host Clock (FSB/4)
One 0.1uF per power pin (place at pin).
GMCH Host Clock (FSB/4)
ITP/XDP Host Clock (FSB/4)
GPU PCIe 100MHz (Ext GFX)
ICH SATA 100MHz
ICH DMI/PCIe 100MHz
From ICH
GMCH Display PLL B 100MHz (Int GFX)SMC LPC 33MHz
ExpressCard / Spare 100MHz
Linda/LPC+ 33MHz
Spare 33MHz
Spare 33MHzSpare 33MHz
GMCH DMI/PCIe 100MHz
PCIe Mini Card (AirPort) 100MHz
(Or 27MHz Spread & Non-Spread for Ext GFX)
ICH USB/Audio 48MHzICH SIO/LPC/REF 14.318MHz
From ICH
Spare 100MHz
(INT PU*)
(INT PU*)
(INT PU*)
(INT PU*)
(INT PU*)
ICH PCI 33MHz
NOTE: Pin 40 was PGMODE on SLG8LP537. Do not pull low
GMCH Display PLL A 96MHz (Int GFX)
(INT PU*)
(INT PU*)
TP or GPU PGOOD
(For External Graphics)
(For Internal Graphics)LCD_CLK-
PIN 11
SRC_0-SRC_0+
LCD_CLK+
PIN 10PIN 7
DOT_96-
27M w/SS
PIN 6
DOT_96+
27M
FCT_SEL
1
0
(INT PU*)
(INT PD*)
(INT PD*)
FW PCI 33MHz
6.3V20%
603X5R
10UF
0402
FERR-120-OHM-1.5A
16V10%
402X5R
0.1UF16V10%
402X5R
0.1UF
16V10%
402X5R
0.1UF
16V10%
402X5R
0.1UF
7 25 30
7 25 30
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
25
30 88
30 88
402CERM50V5%18pF
50V5%
CERM
18pF
402
30 88
30 88
30 88
30 88
48
48
6.3V20%
603X5R
10UF16V10%
402X5R
0.1UF
30 88
30
30 88
16V10%
402X5R
0.1UF16V10%
402X5R
0.1UF16V10%
402X5R
0.1UF16V10%
402X5R
0.1UF
6.3V10%
402CERM
1UF
6.3V20%
603X5R
10UF16V10%
402X5R
0.1UF
0402
FERR-120-OHM-1.5A
6.3V10%
402CERM
1UF
1/16W5%
402MF-LF
2.2
1/16W5%
402MF-LF
1
6.3V20%
603X5R
10UF
402MF-LF
2.2
1/16W5%
30 88
30 88
30
30
30
30
1/16W5%
402MF-LF
10K
XDP
30 88
30 88
25
30 88
30 88
30 88
30 88
30 88
30 88
7 16
5X3.2-SM
14.31818
CRITICAL
6.3V20%
603X5R
10UF
0402
FERR-120-OHM-1.5A
30
OMIT
SLG2AP101QFN
30
051-7261
29 92
A.0.0
SYNC_DATE=01/25/2007SYNC_MASTER=T9_NOME
Clock (CK505)
CK505_CLKREQ6_LCK505_SRC6_P
CK505_SRC5_P
=SMBUS_CK505_SCL
MIN_NECK_WIDTH=0.2mmVOLTAGE=3.3V
PP3V3_S0M_CK505_VDDAMIN_LINE_WIDTH=0.5mm
CK505_XTAL_IN
CK505_FSB_TEST_MODE
PM_STPPCI_LPM_STPCPU_L
CK505_SRC3_N
CK505_CPU0_N
MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.5mm
VOLTAGE=3.3V
PP3V3_S0M_CK505_VDD_PCI
MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.5mm
VOLTAGE=3.3V
PP3V3_S0M_CK505_VDD_REF
MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.5mm
VOLTAGE=3.3V
PP3V3_S0M_CK505_VDD_CPU_SRC
CK505_SRC7_N
CK505_SRC4_P
CK505_SRC2_PCK505_SRC2_N
CK505_SRC1_NCK505_SRC1_P
CK505_CPU0_P
CK505_CLKREQ1_L
SB_SATA_CLKREQ_L
NB_CLKREQ_L
CK505_PCI1_CLKCK505_PCI2_CLKCK505_PCI3_CLKCK505_PCI4_CLK
CK505_PCIF1_CLK
=SMBUS_CK505_SDA
CK505_CPU2_ITP_SRC10_PCK505_CPU2_ITP_SRC10_N
CK505_CPU1_PCK505_CPU1_N
CK505_LVDS_NCK505_LVDS_P
CK505_SRC3_PCK505_CLKREQ3_L
CK505_SRC4_N
MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.5mm
VOLTAGE=3.3V
PP3V3_S0M_CK505_VDD48
CK505_SRC8_PCK505_SRC8_N
CK505_DOT96_27M_NCK505_DOT96_27M_P
CLK_PWRGD
CK505_48M_FSACK505_REF0_FSCTP_GPU_STOP_L
=PP3V3_S0_CK505
=PP3V3_S0M_CK505
MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.5mm
VOLTAGE=3.3V
PP3V3_S0M_CK505_VDDA_R
CK505_SRC5_N
CK505_XTAL_OUT
CK505_CLKREQ7_LCK505_SRC7_P
CK505_PCI5_CLK_FCTSEL
CK505_PCIF0_CLK_ITPEN
=PP3V3_S0M_CK505
CK505_SRC6_N
CK505_CLKREQ8_L
C29101
2
C2912 1
2
L2902
1 2
C2913 1
2
C2915 1
2
C2909 1
2
C29901
2
C2989 1
2
C2907 1
2
C29081
2
C29061
2
C29051
2
C29041
2
C29031
2
C29111
2
C2901 1
2
C29021
2
L2901
1 2
C2900 1
2
R29011 2
R29021 2
C29141
2
R29001 2
R29031
2
Y29011 2
C29161
2
L2903
1 2
U2900
4
2
9
59
20
60
25
40
34
45
44
42
41
3736
55
67
8
53
57
58
63
64
65
56
68
1
54
47
48
10
11
13
14
15
16
18
19
21
22
23
24
26
27
29
30
33
32
69
3
38
43
61
67
49
12
17
28
35
5
39
46
62
66
52
31
51
50
30
30
30
29
29
8
8
8
Page 30
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
IN OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUTIN
IN
OUTIN
OUT
OUT
BI
OUT
OUT
IN
IN
IN
IN
OUT
OUT
IN
OUT
IN
IN
IN
OUT
OUT
OUT
IN
IN
OUT
OUTBI
OUT
OUT
OUT
IN
OUT
OUT
OUTBI
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
G
D
SIN
VER 1
VCC
A
1
0
B1
GND
B0
SEL
VER 1
VCC
A
1
0
B1
GND
B0
SEL
IN
IN
OUT
OUT
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
are not shown here).NB and SATA CLKREQs are not remappable (and thus
GPU Clock Gating
Silego SLG2AP101 has internal pull-ups on allCLKREQ# pins. Support for SL8GLP537 or equiv. only.
Unused Clocks
(ITP HOST 167/200MHZ)
(FW 100MHz)
(LINDA/LPC+ LPC 33MHZ)
(Only 100-200MHz supported by
(WIRELESS PCIe MINI 100MHZ)
CLK Termination
(Spare 33MHZ)
(Reserved for TPM PCI 33MHZ)
(GMCH PEG/DMI 100MHZ)
CLKREQ Controls(Note: HOST/SRC/GFX clock termination removed. Silego SL8GLP536 or equiv. support only)
(Int Gfx LVDS 100MHz)
(SMC PCI 33MHZ)
(FIREWIRE PCI 33MHZ)
(ICH8M PCI 33MHZ)
(Ext GFX Spread 27MHz)
(Ext GFX 27MHz)
(ENET 100MHZ)
(GPU PCIe 100MHz)
(GMCH HOST 167/200MHZ)
(CPU HOST 167/200MHZ)
(TO ICH8M USB 48MHZ)
SLG8LP536 and CY28545-5)
for manual CPU clk frequency.NO STUFF R3082, R3086 & R3090
CPU MHz
200.0
166.6
100.0
133.3
(266.6)
(333.3)
(400.0)
FS_AFS_BFS_C
1 RSVD
1
0
0
1
1
0
0 1
0
00
0
0
10
1
0
1
1
1
11
(TO/FROM CK505)
(TO MCH FS_C)
(TO CK505)
(TO MCH FS_B)
(TO/FROM CK505)
(TO ICH8M 14.318MHZ)
(FROM CPU FS_C)
(FROM CPU FS_A)
(FROM CPU FS_B)
0
(ICH8M SATA 100MHZ)
(ExpressCard 100MHz)
(TO MCH FS_A)
FCT_SEL (GFX clock select)
CK505 Configuration Straps
(ICH8M DMI 100MHZ)
FS_A, FS_B, FS_C (Host clock freq select)
29 88
29 88
29 88
29 88
29 88
29 88
7 16 88
7 16 88
29 88
29 88
29 88
29 88 35 88
35 88
24 88
29 88
29 88
29 88
29 88
29 88
38 88
45 88
24 88
34 88
34 88 29 88
29 88
7 47 88 29 88
24 88
402
10K
MF-LF1/16W
5%
1/16W5%
402MF-LF
1K
1K
MF-LF402
5%1/16W
29
29 88
23 88
23 88
29 88
29 88
MF-LF
1K
402
5%1/16W
NO STUFF
1/16W5%
MF-LF
0
402
10 83
10 83
1/16W5%
402MF-LF
0
MF-LF
1K
402
NO STUFF
1/16W5%
34 88
34 88
29 88
7 14 88
29 88
29 88
29 88
9 68
9 68
7 14 88
29 88
29 88
7 10 88
25 88 33
1/16W5%
402MF-LF
29 88
7 10 88
MF-LF1/16W5%
402
1K13 16 83
1K
5%1/16W
402MF-LF
13 16 83
10 83
1/16W5%
402MF-LF
0
MF-LF402
5%1/16W
1K
NO STUFF
1/16W5%
402MF-LF
1K
13 83 88
1K
1/16W5%
402MF-LF
13 16 83
25 88
33
402
1/16W5%
MF-LF
29 88
13 83 88
33
MF-LF
5%1/16W
402
MF-LF402
5%1/16W
33
7 22 88
7 22 88
29 88
29 88
33
402
1/16W5%
MF-LF
402MF-LF1/16W5%
33
33
402
1/16W5%
MF-LF33
5%1/16WMF-LF402
10K
MF-LF1/16W
5%
402
MF-LF402
2.2K5%
1/16W
402
5%
MF-LF1/16W
10K
NO STUFF
NO STUFF
402
5%
MF-LF1/16W
10K
34
34
7 25 29
7 25 29
29 88
29 88
29
29
29
29
74 90
74 90
SLG8LP537
SOT-3632N7002DW-X-F
28 30 79
SLG8LP537
SC70
NC7SB3157P6X
NC7SB3157P6XSC70
GPU_SS_EXT
402
10V
0.1UF
20%
CERM
GPU_SS_EXT
0.1UF
402CERM10V20% SLG8LP537
28 30 79
35
1/16WMF-LF
402
5%0
SLG2AP101
05%
402MF-LF1/16W
SLG2AP101
29
29
5%1/16WMF-LF
402
0
SLG2AP101
29 88
29 88
SYNC_MASTER=M75_MLB
051-7261
30 92
A.0.0
SYNC_DATE=03/19/2007
Clock Termination
CK505_FSA
CK505_PCI5_CLK_FCTSEL
=PP3V3_S0_CK505
CK505_SRC1_N
CK505_SRC2_P
MAKE_BASE=TRUEPCIE_CLK100M_EXCARD_P
CK505_PCIF1_CLK
CK505_CLK27MMAKE_BASE=TRUE
=PP1V25R1V05_S0_FSB_NB
CK505_FSB_TEST_MODE
CK505_FSC
SB_CLK48M_USBCTLR
CPU_BSEL<0>
CPU_BSEL<1>
CPU_BSEL<2>
CK505_REF0_FSC SB_CLK14P3M_TIMER
NB_BSEL<0>
CK505_48M_FSA
NB_BSEL<1>
NB_BSEL<2>
CK505_PCI1_CLK
CK505_PCIF0_CLK_ITPEN
GPU_CLK27M
CK505_PCI3_CLK
PCI_CLK33M_FW
PCI_CLK33M_SB
PCI_CLK33M_SMC
GPU_CLK27M_SS
MAKE_BASE=TRUEFSB_CLK_CPU_NCK505_CPU0_N
CK505_CPU0_P
CK505_CPU1_N
CK505_CPU1_PMAKE_BASE=TRUEFSB_CLK_NB_P
MAKE_BASE=TRUEFSB_CLK_NB_N
MAKE_BASE=TRUEXDP_CLK_P
MAKE_BASE=TRUEXDP_CLK_N
CK505_CPU2_ITP_SRC10_P
MAKE_BASE=TRUEPEG_CLK100M_GPU_P
MAKE_BASE=TRUEPEG_CLK100M_GPU_N
CK505_SRC2_NMAKE_BASE=TRUESB_CLK100M_DMI_P
MAKE_BASE=TRUESB_CLK100M_DMI_N
CK505_SRC3_N
CK505_SRC4_P
CK505_SRC5_N
CK505_SRC5_P
MAKE_BASE=TRUESB_CLK100M_SATA_N
SB_CLK100M_SATA_PMAKE_BASE=TRUE
CK505_SRC6_N
CK505_SRC6_P
CK505_SRC7_P
CK505_SRC7_N TP_PCIE_CLK100M_SRC7NMAKE_BASE=TRUE
PCIE_CLK100M_ENET_NMAKE_BASE=TRUE
PCIE_CLK100M_ENET_PMAKE_BASE=TRUE
CK505_CPU2_ITP_SRC10_N
=PP1V25R1V05_S0_FSB_NB
CK505_SRC4_N
MAKE_BASE=TRUETP_PCIE_CLK100M_SRC7P
CK505_CLK27M_SSMAKE_BASE=TRUE
PM_STPPCI_L
PM_STPCPU_L
TP_CK505_PCI2_CLKMAKE_BASE=TRUE
MAKE_BASE=TRUETP_CK505_PCI4_CLK
CK505_PCI2_CLK
CK505_PCI4_CLK
MAKE_BASE=TRUEPCIE_CLK100M_EXCARD_N
=PP3V3_S0M_CK505
MAKE_BASE=TRUENB_CLK100M_PCIE_P
=PP1V25R1V05_S0_FSB_NB
MAKE_BASE=TRUEFSB_CLK_CPU_P
MAKE_BASE=TRUENB_CLK100M_PCIE_N
MAKE_BASE=TRUEPCIE_CLK100M_MINI_N
PCIE_CLK100M_MINI_PMAKE_BASE=TRUE
CK505_CLKREQ1_L
CK505_SRC3_P
CK505_SRC1_P
MAKE_BASE=TRUENB_CLK100M_DPLLSS_P
MAKE_BASE=TRUENB_CLK100M_DPLLSS_NCK505_LVDS_N
CK505_LVDS_P
PCI_CLK33M_LPCPLUS
CK505_DOT96_27M_N
CK505_DOT96_27M_P
CK505_SRC8_N
CK505_SRC8_P
MAKE_BASE=TRUEPEG_CLKREQ_L
PM_ALL_GPU_PGOOD
GPU_CLK27M_GATED
GPU_CLK27M_SS_GATED
GPU_CLK27M
=PP3V3_S0_GPUCLKGATE
GPU_CLK27M_SS
CK505_CLKREQ8_L
CK505_CLKREQ3_L
CK505_CLKREQ6_LMINI_CLKREQ_LMAKE_BASE=TRUE
EXCARD_CLKREQ_LMAKE_BASE=TRUE
CK505_CLKREQ7_LTP_CK505_CLKREQ7_LMAKE_BASE=TRUE
MAKE_BASE=TRUEENET_CLKREQ_L=ENET_CLKREQ_L
PM_ALL_GPU_PGOOD
GPU_STOP_LMAKE_BASE=TRUE
TP_GPU_STOP_L
R30671
2
R30831
2
R30841
2
R30801
2 R30821 2
R30861 2
R30871
2
R30321 2
R30811 2
R30851 2
R30901 2
R30881
2
R30911
2
R30891 2
R30341 2
R30241 2
R30251 2
R30261 2
R30271 2
R30281 2
R30301 2
R30352
1
R30332
1
R30461 2
R30471 2
Q30506
2
1
U3050
43
1
2
6
5
U3055
43
1
2
6
5
C30551 2
C30501 2
R30501
2
R30551
2
R30511
2
30
30
30
29
14
90
90
14
29
14
90
90
88
8
8
88
30
30
8
8
8
30
8
30
Page 31
VSS7
VSS12
VSS9
KEY
DQ57
DQ51
DQS6
DQ43
DQ42
DQ40
DQ34
DQ1
DQ0
VSS1
DQS0*
DQS0
VSS6
DQ2
DQ3
DQ8
DQ9
VSS10
DQS1*
DQS1
DQ10
DQ11
VSS14
VSS16
DQ16
DQ17
VSS18
DQS2*
DQS2
VSS21
DQ18
DQ19
VSS23
DQ24
DQ25
VSS25
DM3
NC1
VSS27
DQ26
DQ27
VSS29
CKE0
VDD0
NC2
BA2
VDD2
A12
A9
A8
VDD4
A5
A3
A1
VDD6
A10/AP
BA0
WE*
VDD8
CAS*
NC/S1*
VDD10
NC/ODT1
VSS31
DQ32
DQ33
VSS33
DQS4*
DQS4
VSS36
DQ35
VSS38
DQ41
VSS40
DM5
VSS41
VSS43
DQ48
DQ49
VSS45
NC_TEST
VSS47
DQS6*
VSS49
DQ50
VSS51
DQ56
VSS53
DM7
VSS55
DQ58
DQ59
VSS57
SDA
SCL
VDDSPD
DM6
DQ55
DQ61
DQ46
DQ47
DQ12
DM1
DM0
DQ7
DQ13
VSS11
CK0
CK0*
VSS13
DQ14
DQ15
VSS15
VSS17
DQ20
DQ21
VSS19
NC0
DM2
VSS22
DQ22
DQ23
VSS24
DQ28
DQ29
VSS26
DQS3*
DQS3
VSS28
DQ30
DQ31
VSS30
NC/CKE1
VDD1
NC/A15
NC/A14
VDD3
A11
A7
A6
VDD5
A4
A2
A0
VDD7
BA1
RAS*
S0*
VDD9
ODT0
NC/A13
VDD11
NC3
VSS32
DQ36
DQ37
VSS34
DM4
VSS35
DQ38
DQ39
VSS37
DQ44
DQ45
VSS39
DQS5*
DQS5
VSS42
VSS44
DQ52
DQ53
VSS46
CK1
CK1*
VSS48
VSS50
DQ54
VSS52
DQ60
VSS54
DQS7*
DQS7
VSS56
DQ62
DQ63
VSS58
SA0
SA1
DQ5
VSS2
VREF
VSS4
VSS8
VSS0
DQ4
VSS5
DQ6
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Signal aliases required by this page:
NC
"Factory" (thru-hole) slot
DDR2 Bypass Caps
NC
516-0140
NC
(For return current)
ADDR=0xA0(WR)/0xA1(RD)
NC
- =PPSPD_S0M_MEM_A (2.5V - 3.3V)
- =I2C_SODIMMA_SDA
BOM options provided by this page:(NONE)
- =I2C_SODIMMA_SCL
- =PP1V8_S3M_MEM_A- =PP0V9_S3M_MEM_DIMMVREFA
Power aliases required by this page:
Page Notes
402
6.3VCERM
1UF10%
402
6.3VCERM
1UF10%
10UF
X5R603
20%6.3V
402
6.3VCERM
1UF10%
10UF
X5R603
20%6.3V
402
6.3VCERM
1UF10%
402
10%6.3VCERM
1UF
402
10%6.3VCERM
1UF
402
6.3VCERM
1UF10%
402
6.3VCERM
1UF10%
402
10%6.3VCERM
1UF
402
10%6.3VCERM
1UF
402
6.3VCERM
1UF10%
402
6.3VCERM
1UF10%
0.1uF
CERM402
20%10V
2.2uF20%
603CERM16.3V
F-RT-TH1
DDR2-SODIMM-DUAL
CRITICAL
SYNC_DATE=03/19/2007SYNC_MASTER=M75_MLB
DDR2 SO-DIMM Connector A
051-7261 A.0.0
9231
MEM_A_DQ<58>MEM_A_DQ<60>
MEM_A_DQ<51>
=PP1V8_S3M_MEM_A
=PP0V9_S3M_MEM_DIMMVREFA
MEM_A_DQ<6>
MEM_A_DQ<15>MEM_A_DQ<9>
MEM_A_A<2>MEM_A_A<4>
MEM_A_A<7>MEM_A_A<11>
MEM_A_DQ<29>MEM_A_DQ<25>
MEM_A_DQS_P<3>MEM_A_DQS_N<3>
MEM_A_DQ<24>MEM_A_DQ<26>
MEM_A_DM<2>PM_EXTTS_L<0>
MEM_A_DQ<20>MEM_A_DQ<18>
MEM_A_DQ<5>MEM_A_DQ<1>
MEM_CLK_N<0>MEM_CLK_P<0>
MEM_A_DM<0>
MEM_A_DQ<3>
MEM_A_DQ<12>MEM_A_DQ<8>
MEM_A_DQ<35>
MEM_A_DQ<47>MEM_A_DQ<44>
MEM_A_DQS_P<5>MEM_A_DQS_N<5>
MEM_A_DQ<40>MEM_A_DQ<45>
MEM_A_DQ<52>MEM_A_DQ<49>
MEM_A_DM<6>
MEM_CLK_N<1>MEM_CLK_P<1>
MEM_A_DQ<50>MEM_A_DQ<55>
MEM_A_DQ<61>MEM_A_DQ<57>
MEM_A_DQS_P<7>MEM_A_DQS_N<7>
MEM_A_DQ<62>MEM_A_DQ<63>
MEM_A_DQ<32>MEM_A_DQ<33>
MEM_A_DM<4>
MEM_A_DQ<39>
MEM_A_A<13>MEM_ODT<0>
MEM_CS_L<0>MEM_A_RAS_L
=PPSPD_S0M_MEM_A=I2C_SODIMMA_SDA
MEM_A_DQ<41>MEM_A_DQ<46>
MEM_A_DM<5>
MEM_A_DQ<42>MEM_A_DQ<43>
MEM_A_DQ<53>MEM_A_DQ<48>
MEM_A_DQS_P<6>
MEM_A_DQ<54>
MEM_A_DQ<59>MEM_A_DQ<56>
MEM_A_DQ<34>MEM_A_DQ<37>
MEM_A_DQS_P<4>
MEM_A_DQ<38>MEM_A_DQ<36>
MEM_ODT<1>
MEM_CS_L<1>MEM_A_CAS_L
MEM_A_WE_LMEM_A_BS<0>MEM_A_A<10>
MEM_A_A<1>MEM_A_A<3>MEM_A_A<5>
MEM_A_A<8>MEM_A_A<9>MEM_A_A<12>
MEM_A_BS<2>
=PP1V8_S3M_MEM_A
MEM_CKE<0>
MEM_A_DQ<28>MEM_A_DQ<30>
MEM_A_DQ<27>MEM_A_DQ<31>
MEM_A_DQ<16>MEM_A_DQ<23>
MEM_A_DQS_P<2>MEM_A_DQS_N<2>
MEM_A_DQ<21>MEM_A_DQ<17>
MEM_A_DQ<4>
MEM_A_DQS_P<0>MEM_A_DQS_N<0>
MEM_A_DQ<0>MEM_A_DQ<7>
MEM_A_DQ<11>MEM_A_DQ<10>
MEM_A_DQS_P<1>MEM_A_DQS_N<1>
MEM_A_DQ<13>
MEM_A_DQ<2>
MEM_A_DM<1>
MEM_A_DQ<14>
MEM_A_BS<1>
MEM_A_A<0>
MEM_A_DQS_N<4>
=I2C_SODIMMA_SCL
MEM_A_A<6>
MEM_A_DM<3>
MEM_CKE<1>
MEM_A_A<15>MEM_A_A<14>
=PP1V8_S3M_MEM_A
MEM_A_DQ<19>MEM_A_DQ<22>
MEM_A_DQS_N<6>
MEM_A_DM<7>
C31131
2
C31121
2
C31091
2
C31111
2
C31081
2
C31101
2
C31191
2
C31181
2
C31171
2
C31161
2
C31211
2
C31201
2
C31151
2
C31141
2
C31001
2
C3101 1
2
J3100
102B
105B
90B89B
101B
100B99B
98B97B
94B
92B
93B
91B
107B
106B
85B
113B
30B
32B
164B
166B
79B
10B
26B
52B
67B
130B
147B
170B
185B
5B
35B
37B
20B
22B
36B
38B
43B
45B
55B
57B
7B
44B
46B
56B
58B
61B
63B
73B
75B
62B
64B
17B
74B
76B
123B
125B
135B
137B
124B
126B
134B
136B
19B
141B
143B
151B
153B
140B
142B
152B
154B
157B
159B
4B
173B
175B
158B
160B
174B
176B
179B
181B
189B
191B
6B
180B
182B
192B
194B
14B
16B
23B
25B
13B
11B
31B
29B
51B
49B
70B
68B
131B
129B
148B
146B
169B
167B
188B
186B
201
202
116B
86B
84B
80B
119B
115B
50B
69B
83B
120B
163B
114B
108B
110B
198B
200B
197B
195B
81B
117B 118B
82B
87B 88B
95B 96B
103B 104B
111B 112B
199B
1B 2B
27B 28B
33B 34B
39B 40B
41B 42B
47B 48B
3B
53B 54B
59B 60B
65B 66B
71B 72B
77B
8B
78B
121B 122B
127B 128B
132B
133B
138B
139B
144B
145B
149B 150B
155B 156B
161B 162B
165B
168B
171B
9B
172B
177B 178B
183B 184B
187B
190B
193B
196B
12B
15B
18B
21B
24B
109B
91
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
91
85
85
85
85
85
85
91
85
85
85
31
85
85
85
33
33
33
33
85
85
85
85
85
85
85
45
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
33
33
33
33
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
33
33
33
33
33
33
33
33
33
33
33
33
33
31
33
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
33
33
85
33
85
33
33
31
85
85
85
85
17
17
17
8
8
17
17
17
17
17
17
17
17
17
17
17
17
17
17
16
17
17
17
17
16
16
17
17
17
17
17
17
17
17
17
17
17
17
17
17
16
16
17
17
17
17
17
17
17
17
17
17
17
17
17
16
16
17
8
48
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
16
16
17
17
17
17
17
17
17
17
17
17
17
8
16
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
48
17
17
16
9
16
8
17
17
17
17
Page 32
VSS2
DQS0*
DQ5
VSS0
DQ4
VSS5
DQ6
VSS29
DM0
VSS7
DM1
DQ7
VDD1
DQ30
DQ23
VSS22
NC/ODT1
RAS*
SA1
SA0
VSS58
DQ63
DQ62
VSS56
DQS7
DQS7*
VSS54
DQ60
VSS52
DQ54
VSS50
VSS48
CK1*
CK1
VSS46
DQ53
DQ52
VSS44
VSS42
DQS5
DQS5*
VSS39
DQ45
DQ44
VSS37
DQ39
DQ38
VSS35
DM4
VSS34
DQ37
DQ36
VSS32
NC3
VDD11
NC/A13
ODT0
VDD9
S0*
BA1
VDD7
A0
A2
A4
VDD5
A6
A7
A11
VDD3
NC/A14
NC/A15
NC/CKE1
VSS30
DQ31
DQS3
DQ29
DQ28
VSS24
DQ22
DM2
NC0
VSS19
DQ21
DQ20
VSS17
VSS15
DQ15
DQ14
VSS13
CK0*
CK0
VSS11
DQ13
DQ12
DQ47
DQ46
DQ61
DQ55
DM6
VDDSPD
SCL
SDA
VSS57
DQ59
DQ58
VSS55
DM7
VSS53
DQ56
VSS51
DQ50
VSS49
DQS6*
VSS47
NC_TEST
VSS45
DQ49
DQ48
VSS43
VSS41
DM5
VSS40
DQ41
VSS38
DQ35
VSS36
DQS4
DQS4*
VSS33
DQ33
DQ32
VSS31
VDD10
NC/S1*
CAS*
VDD8
WE*
BA0
A10/AP
VDD6
A1
A3
A5
VDD4
A8
A9
A12
VDD2
BA2
NC2
VDD0
CKE0
DQ27
DQ26
VSS27
NC1
DM3
DQ25
DQ24
VSS23
DQ19
DQ18
VSS21
DQS2
DQS2*
VSS18
DQ17
DQ16
VSS16
VSS14
DQ11
DQ10
VSS12
DQS1
DQS1*
DQ9
DQ8
VSS8
DQ3
DQ2
VSS6
DQS0
VREF
DQ34
DQ40
DQ42
DQ43
DQS6
DQ51
DQ57
KEY
VSS9
DQ1
VSS4
DQ0
VSS1
DQS3*
VSS26
VSS28
VSS25
VSS10
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Resistor prevents pwr-gnd short
ADDR=0xA4(WR)/0xA5(RD)
Page NotesPower aliases required by this page:
Signal aliases required by this page:
"Expansion" (surface-mount) slot
516S0471
DDR2 Bypass Caps(For return current)
NC
NC
NC
NC
BOM options provided by this page:(NONE)
- =I2C_SODIMMB_SCL- =I2C_SODIMMB_SDA
- =PP0V9_S3M_MEM_DIMMVREFB- =PPSPD_S0M_MEM_B (2.5V - 3.3V)
- =PP1V8_S3M_MEM_B
402CERM
1UF10%6.3V
402CERM
1UF10%6.3V
6.3V20%
603X5R
10UF
10V0.1uF
CERM402
20%
603
20%6.3VX5R
10UF
402CERM
1UF10%6.3V
10V0.1uF
CERM402
20%10V0.1uF
CERM402
20%
0.1uF
CERM402
20%10V402CERM
1UF10%6.3V
10V0.1uF
CERM402
20%0.1uF10VCERM402
20%
402CERM
1UF10%6.3V
402CERM
1UF10%6.3V
1/16W
402MF-LF
5%10K
0.1uF
CERM402
20%10V
2.2uF20%
603CERM16.3V
DDR2-SODIMM-DUAL
CRITICAL
F-RT-SM-M9
9232
051-7261 A.0.0
SYNC_MASTER=M75_MLB SYNC_DATE=03/19/2007
DDR2 SO-DIMM Connector B
=PP1V8_S3M_MEM_B
=PP0V9_S3M_MEM_DIMMVREFB
MEM_B_DQ<23>
=PP1V8_S3M_MEM_B
MEM_B_DQ<8>
MEM_B_DQ<3>
MEM_B_DQ<14>MEM_B_DQ<11>
MEM_B_DQS_N<3>
MEM_B_DQ<22>
MEM_ODT<2>
MEM_B_RAS_L
MEM_B_A<0>
MEM_B_A<11>
MEM_B_DQ<30>
MEM_B_DQ<28>MEM_B_DQ<26>
MEM_B_DQ<16>
MEM_B_DM<2>
MEM_B_DQ<18>
MEM_B_DQ<0>
MEM_B_BS<1>
MEM_CKE<4>
MEM_B_DQ<15>
MEM_B_DQ<10>MEM_B_DQ<13>
MEM_B_DQ<7>MEM_B_DQ<2>
MEM_B_DQS_N<0>MEM_B_DQS_P<0>
MEM_B_DQ<1>
MEM_B_DQ<21>MEM_B_DQ<19>
MEM_B_DQS_N<2>MEM_B_DQS_P<2>
MEM_B_DQ<20>
MEM_B_DQ<24>
MEM_B_DM<3>
MEM_B_DQ<27>MEM_B_DQ<25>
MEM_CKE<3>
MEM_B_BS<2>
MEM_B_A<12>MEM_B_A<9>MEM_B_A<8>
MEM_B_A<5>MEM_B_A<3>MEM_B_A<1>
MEM_B_BS<0>MEM_B_WE_L
MEM_B_DQ<4>
MEM_B_DQS_P<4>
MEM_B_DQ<35>
MEM_B_DQ<57>MEM_B_DQ<60>
MEM_B_DM<7>
MEM_B_DQ<61>MEM_B_DQ<62>
MEM_B_DQ<48>MEM_B_DQ<51>
MEM_B_DQS_N<6>MEM_B_DQS_P<6>
MEM_B_DQ<50>MEM_B_DQ<55>
MEM_B_DQ<40>MEM_B_DQ<47>
MEM_B_DM<5>
MEM_B_DQ<42>MEM_B_DQ<45>
=I2C_SODIMMB_SDA=I2C_SODIMMB_SCL
MEM_B_DQ<9>
MEM_B_DM<1>
MEM_B_DM<0>
MEM_CLK_P<4>MEM_CLK_N<4>
MEM_B_DQ<5>
MEM_B_DQ<17>
MEM_B_A<15>MEM_B_A<14>
MEM_B_A<6>
MEM_B_A<2>
MEM_CS_L<2>
=PP1V8_S3M_MEM_B
MEM_B_A<13>
MEM_B_DQ<32>MEM_B_DQ<37>
MEM_B_DM<4>
MEM_B_DQ<38>MEM_B_DQ<39>
MEM_B_DQ<56>MEM_B_DQ<59>
MEM_B_DQS_N<7>MEM_B_DQS_P<7>
MEM_B_DQ<63>
MEM_B_DQ<54>MEM_B_DQ<53>
MEM_B_DQS_N<5>MEM_B_DQS_P<5>
MEM_B_DQ<41>
PM_EXTTS_L<1>
MEM_B_DQ<58>
MEM_B_DQS_P<3>
MEM_B_DQ<31>
MEM_B_DQ<29>
MEM_B_DQS_N<1>
MEM_B_DQ<6>
MEM_B_DQ<12>MEM_B_DQS_P<1>
MEM_B_A<4>
MEM_B_A<7>
=PPSPD_S0M_MEM_B
MEM_B_DQ<43>
=PPSPD_S0M_MEM_B
SODIMM_B_SA1
MEM_B_DQ<46>
MEM_B_DQ<52>
MEM_CLK_N<3>MEM_CLK_P<3>
MEM_B_DQ<36>
MEM_B_DQ<34>
MEM_ODT<3>
MEM_CS_L<3>
MEM_B_A<10>
MEM_B_DQ<44>
MEM_B_DQ<49>
MEM_B_DM<6>
MEM_B_DQS_N<4>
MEM_B_DQ<33>
MEM_B_CAS_LC32131
2
C32121
2
C32091
2
C32111
2
C32081
2
C32101
2
C32191
2
C32181
2
C32171
2
C32161
2
C32211
2
C32201
2
C32151
2
C32141
2
R32001
2
C32001
2
C3201 1
2
J3200
102A
105A
90A89A
101A
100A99A
98A97A
94A
92A
93A
91A
107A
106A
85A
113A
30A
32A
164A
166A
79A
10A
26A
52A
67A
130A
147A
170A
185A
5A
35A
37A
20A
22A
36A
38A
43A
45A
55A
57A
7A
44A
46A
56A
58A
61A
63A
73A
75A
62A
64A
17A
74A
76A
123A
125A
135A
137A
124A
126A
134A
136A
19A
141A
143A
151A
153A
140A
142A
152A
154A
157A
159A
4A
173A
175A
158A
160A
174A
176A
179A
181A
189A
191A
6A
180A
182A
192A
194A
14A
16A
23A
25A
13A
11A
31A
29A
51A
49A
70A
68A
131A
129A
148A
146A
169A
167A
188A
186A
201
202
203
204
116A
86A
84A
80A
119A
115A
50A
69A
83A
120A
163A
114A
108A
110A
198A
200A
197A
195A
81A
117A 118A
82A
87A 88A
95A 96A
103A 104A
111A 112A
199A
1A 2A
27A 28A
33A 34A
39A 40A
41A 42A
47A 48A
3A
53A 54A
59A 60A
65A 66A
71A 72A
77A
8A
78A
121A 122A
127A 128A
132A
133A
138A
139A
144A
145A
149A 150A
155A 156A
161A 162A
165A
168A
171A
9A
172A
177A 178A
183A 184A
187A
190A
193A
196A
12A
15A
18A
21A
24A
109A
91
91
85
85
85
85
85
85 85
85
85
85
85
85
85
85
85
85
85
85
85
85
91
85
85
85
85
85
85
85
32
85
32
85
85
85
85
85
85
33
33
33
33
85
85
85
85
85
85
85
33
33
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
33
33
33
33
33
33
33
33
33
33
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
33
33
33
33
32
33
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
45
85
85
85
85
85
85
85 85
33
33
32
85
32
85
85
85
85
85
85
33
33
33
85
85
85
85
85
33
8
8
17
8
17
17
17
17
17
17
16
17
17
17
17
17
17
17
17
17
17
17
16
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
16
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
48
48
17
17
17
16
16
17
17
9
16
17
17
16
8
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
16
17
17
17
17
17
17
17 17
17
17
8
17
8
17
17
16
16
17
17
16
16
17
17
17
17
17
17
17
Page 33
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Ensure CS_L and ODT resistors are close to SO-DIMM connector
One cap for each side of every RPAK, one cap for every two discrete resistors
CERM
20%10V
0.1uF
402
CERM
20%10V
0.1uF
402CERM
20%10V
0.1uF
402
CERM
20%10V
0.1uF
402
CERM
20%10V
0.1uF
402
CERM
20%10V
0.1uF
402
CERM
20%10V
0.1uF
402CERM
20%10V
0.1uF
402
20%10VCERM
0.1uF
402
CERM
20%10V
0.1uF
402
17 32 85
17 32 85
16 32 85
SM-LF1/16W5%56
SM-LF5% 1/16W56
17 31 85
17 32 85
17 31 85
16 32 85
16 31 85
16 31 85
16 32 85
16 31 85
16 31 85
17 32 85
17 31 85
17 31 85
17 31 85
17 31 85
17 31 85
17 31 85
17 31 85
17 31 85
17 31 85
17 31 85
17 31 85
17 31 85
17 31 85
17 31 85
16 31 85
17 31 85
17 32 85
17 32 85
17 32 85
17 32 85
17 32 85
17 32 85
17 32 85
17 32 85
17 32 85
17 32 85
17 32 85
17 31 85
17 32 85
17 32 85
17 32 85
17 32 85
16 32 85
16 32 85
17 32 85
565% MF-LF 4021/16W
16 31 85
SM-LF1/16W5%5656
5% 1/16W SM-LF
SM-LF1/16W5%56
SM-LF1/16W56
5%
1/16W56
SM-LF5%
SM-LF1/16W5%56
1/16W5%56
SM-LF565% 1/16W SM-LF
1/16W5%56
SM-LF
SM-LF1/16W5%56
SM-LF56
5% 1/16W
SM-LF1/16W5%56
SM-LF56
5% 1/16W
SM-LF1/16W5%56
SM-LF1/16W5%56
SM-LF1/16W5%56
1/16W5% SM-LF56
565% 1/16W SM-LF
SM-LF1/16W5%56
SM-LF1/16W5%56
565% 1/16W SM-LF
SM-LF1/16W5%5656
5% 1/16W SM-LF
SM-LF56
5% 1/16W
565% 1/16W SM-LF
565% 1/16W SM-LF
SM-LF1/16W5%56
SM-LF56
5% 1/16W
SM-LF1/16W5%56
1/16W5%56
SM-LF
5% 1/16W SM-LF56
SM-LF56
5% 1/16W
565% 1/16W SM-LF
SM-LF56
5% 1/16W
565% 1/16W SM-LF
1/16W5%56
SM-LF565% 1/16W SM-LF
SM-LF56
5% 1/16W
SM-LF1/16W5%56
1/16W5% SM-LF56
SM-LF1/16W5%56
1/16W56
SM-LF5%
5% 1/16W SM-LF56
1/16W5% SM-LF56
565% 1/16W SM-LF
1/16W5% SM-LF56
5% 1/16W SM-LF56
1/16W5%56
SM-LF
SM-LF1/16W5%56
SM-LF56
5% 1/16W
MF-LF1/16W5%56
40216 32 85
10V20%
CERM
0.1uF
402
17 31 85
16 31 85
17 31 85
16 32 85
CERM
20%10V
0.1uF
402CERM
20%10V
0.1uF
402
CERM
20%10V
0.1uF
402CERM
20%10V
0.1uF
402
20%0.1uF10V
402CERM
20%10V
402CERM
0.1uF
402
20%10V
0.1uF
CERM10V20%
CERM
0.1uF
402
CERM
20%10V
0.1uF
402CERM
20%10V
0.1uF
402
CERM
20%10V
0.1uF
402CERM
20%10V
0.1uF
402
CERM
20%10V
0.1uF
402CERM
20%10V
0.1uF
402
CERM
20%10V
0.1uF
402CERM
20%10V
0.1uF
402
051-7261
9233
A.0.0
Memory Active TerminationSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
MEM_A_A<11>
=PP0V9_S0M_MEM_TERM
MEM_A_BS<2>
MEM_B_A<11>
MEM_B_BS<2>
MEM_B_A<7>MEM_B_A<8>MEM_B_A<9>
MEM_B_A<13>MEM_B_A<14>
MEM_B_A<4>
MEM_A_WE_L
MEM_B_BS<1>
MEM_CS_L<2>
MEM_CKE<1>MEM_CKE<0>
MEM_CKE<3>MEM_CKE<4>
MEM_ODT<0>MEM_ODT<1>
MEM_A_A<6>
MEM_A_A<8>MEM_A_A<7>
MEM_A_A<13>
MEM_A_A<10>
MEM_A_BS<1>
MEM_A_CAS_LMEM_A_RAS_L
MEM_A_BS<0>
MEM_A_A<14>
MEM_A_A<5>
MEM_ODT<3>
MEM_A_A<0>MEM_A_A<1>MEM_A_A<2>
MEM_ODT<2>
MEM_A_A<12>
MEM_A_A<4>
MEM_B_A<1>
MEM_B_A<12>
MEM_B_A<2>
MEM_B_A<5>
MEM_CS_L<0>
MEM_CS_L<3>
MEM_B_RAS_L
MEM_CS_L<1>
MEM_B_BS<0>
MEM_B_A<0>
MEM_B_A<6>
MEM_A_A<9>
MEM_B_CAS_LMEM_B_WE_L
MEM_B_A<3>
MEM_A_A<3>
MEM_B_A<10>
C33481
2
C33461
2
C33361
2
C33341
2
C33321
2
C33301
2
C33121
2
C33101
2
C33071
2
C33051
2
C33021
2
C33001
2
C33441
2
C33421
2
C33401
2
C33381
2
C33521
2
C33561
2
C33541
2
C33501
2
C33601
2
C33641
2
C33681
2
C33661
2
C33621
2
C33581
2
RP3358 2 7
RP3300 3 6
R3370 1 2
RP3346 4 5
RP3330 1 8
RP3342 2 7
RP3330 3 6RP3330 4 5
RP3330 2 7
RP3342 4 5
RP3342 3 6
RP3342 1 8
RP3358 4 5
RP3346 3 6
RP3358 3 6
RP3346 1 8
RP3346 2 7
RP3358 1 8
RP3366 4 5
RP3366 1 8
RP3366 2 7
RP3350 1 8
RP3334 4 5
RP3338 2 7
RP3354 3 6RP3354 4 5
RP3310 1 8
RP3310 4 5
RP3310 2 7
RP3362 3 6
RP3350 4 5
RP3350 2 7
RP3354 2 7
RP3350 3 6
RP3354 1 8
RP3338 4 5
RP3338 3 6RP3338 1 8
RP3334 2 7
RP3334 1 8
RP3334 3 6
RP3300 4 5
RP3305 2 7
RP3366 3 6
RP3300 2 7
RP3310 3 6
RP3362 2 7
RP3305 4 5
RP3305 1 8
RP3305 3 6
RP3300 1 8
RP3362 1 8
RP3362 4 5
R3371 1 2
C33701
2
8
Page 34
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
BI
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NC
Place caps close to SB
516S0348
Left I/O Board Connector
Output to LIO
Place caps close to SB
Pull-up on LIO, FETs to GND on MLB
24 86
24
24
24 87
24 87
7 45 54
M-ST-SMQT500806-L121-9F
CRITICAL
66
45
66
45 46 57 67
24
13 24
7 54
30
30
24 46
45 46
25 35
23 86
23 86
23 86
23 86
23 86
28
45 46
24 86
24 86
24 86
24 86
24 86
24 86
30 88
30 88
30 88
30 88
24 87
24 87
24
24
48
48
48
48
X5R16V10%
402
0.1uF
16V10%
402X5R
0.1uF
16V10%
402X5R
0.1uF
16V10%
402X5R
0.1uF
24 86
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
Left I/O Board Connector
051-7261 A.0.0
9234
USB_EXCARD_N
USB_EXTB_N
USB_EXTC_PPM_WLAN_EN_LSYS_ONEWIREALS_GAIN
PCIE_MINI_R2D_P
HDA_SDIN0
USB_EXTC_N
PCIE_CLK100M_MINI_N
PCIE_CLK100M_EXCARD_N
PCIE_EXCARD_R2D_NPCIE_EXCARD_R2D_P
=SMBUS_LIO_SMC_SCL=SMBUS_LIO_SMC_SDA
HDA_RST_L
HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT
=SMBUS_LIO_SB_SDA=SMBUS_LIO_SB_SCL
PCIE_WAKE_LLIO_S3_ENSMC_EXCARD_PWR_ENLIO_S0_EN_LSMC_EXCARD_CPEXCARD_OC_LMINI_CLKREQ_LEXCARD_CLKREQ_L
LIO_PLT_RST_LLTALS_OUT
USB_EXTC_OC_L
MAKE_BASE=TRUEPCIE_EXCARD_R2D_C_P
PCIE_MINI_R2D_C_N
TP_PCIE_EXCARD_D2R_NTP_PCIE_EXCARD_D2R_P
TP_PCIE_EXCARD_R2D_C_N
TP_PCIE_EXCARD_R2D_C_P
=PP1V5_S0_LIO
USB_MINI_PUSB_MINI_N
PCIE_CLK100M_EXCARD_P
PCIE_MINI_D2R_PPCIE_MINI_D2R_N
PCIE_EXCARD_D2R_NMAKE_BASE=TRUE
PCIE_EXCARD_R2D_C_NMAKE_BASE=TRUE
PCIE_MINI_R2D_C_P
PCIE_EXCARD_D2R_PMAKE_BASE=TRUE
USB_EXCARD_P
PCIE_MINI_R2D_N
PCIE_CLK100M_MINI_P
USB_EXTB_P
SMC_BC_ACOK
USB_EXTB_OC_L
J3400
1
10
11 12
13 14
15 16
17 18
19
2
20
21 22
23 24
25 26
27 28
29
3
30
31 32
33 34
35 36
37 38
39
4
40
41 42
43 44
45 46
47 48
49
5
50
51 52
53 54
55 56
57 58
59
6
60
61 62
63 64
65 66
67 68
69
7
70
71 72
73 74
75 76
77 78
79
8
80
81
82 83
84
9
C342112
C342012
C341112
C341012
91
91
91
87
8
87
87
87
91
Page 35
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
IN
IN
IN
OUT
OUT
IN
IN
THRML_PAD
VDDO_TTL1
VMAIN_AVLBL
SWITCH_VAUX
VAUX_AVLBL
LED_DUPLEX*
RSVD_43
RSVD_29
RSVD_25
RSVD_24
NC_64
CTRL12
NC_57
NC_52
NC_51
NC_32
RSET
SWITCH_VCC
AVDDH
AVDD0
AVDD3
VDDO_TTL3
LOM_DISABLE*
VDD0
VDD1
VDD3
VDD4
TX_P
CTRL18
TESTMODE
VDD2
VDD5
VDD7
CLKREQ*
WAKE*
PERST*
MDIP0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
XTALI
MDIN3
XTALO
REFCLKP
REFCLKN
RX_N
RX_P
SPI_DO
SPI_CLK
SPI_CS
VPD_DATA
VPD_CLK
TX_N
MDIN0
AVDD1
LED_LINK1000*
VDD6
VDDO_TTL2
VDDO_TTL0
LED_ACT*
LED_LINK10/100*
AVDD2
SPI_DI
ANALOGPCI EXPRESS
SPI
LED
TWSIMEDIA
MAIN CLK
TEST/RSVD
IN
OUT
OUT
E2
WC*
NC0NC1
VCC
VSS
SCL
SDA
IN
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
EC:CTRL25
NC
No link: 130 mA10 Mbps: 130 mA
1000 Mbps: 290 mA
(IPU)
and magnetics. Can also use BCP69T1 connected to CTRL18 pin 4 for internal VR.
- =ENET_VMAIN_AVLBL (See note by pin)
NOTE: See bottom of page for
Yukon Ultra schematic support. instructions for dual Yukon EC /
YUKON_EC - Selects Yukon EC RSET value.
To support Yukon EC and Ultra on the same board:
- =PP1V8R2V5_ENET_PHY
Signal aliases required by this page:- =ENET_CLKREQ_L (NC/TP for Yukon EC)
BOM options provided by this page:
YUKON_ULTRA - Selects Yukon Ultra RSET.
(EC:2.5V)
Yukon Ultra: Alias to GNDYukon EC: Alias to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF & 1x 0.001uF caps
No link: 82 mA
1000 Mbps: 218 mA100 Mbps: 126 mA10 Mbps: 108 mA
Yukon EC (2.5V)
1000 Mbps: 150 mA100 Mbps: 40 mA
No link: 0 mA10 Mbps: 30 mA
Yukon Ultra (1.8V)
10 Mbps: 4 mA100 Mbps: 4 mA
1000 Mbps: 80 mA
Must be high in S0 state (can use PP3V3_S0 as input)
- =YUKON_EC_PP2V5_ENET
Yukon Ultra
1000 Mbps: 426 mA100 Mbps: 203 mA
No link: 171 mA
Yukon EC
100 Mbps: 150 mA
Yukon EC
VPD ROM
NC
1000 Mbps: 4 mA
No link: 4 mA
10 Mbps: 179 mA
Yukon Ultra
100 Mbps: 70 mA
EC:NO CONNECT
EC:AVDD 2.5V
NCNCNC
NCNC
NC
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPD)
NCNCNC
NCNCNC
NC
NC
(2.5V / GND)(2.5V / 1.8V)(EC / Ultra)
- =PP1V2_ENET_PHY
- =PP3V3_ENET_PHYPower aliases required by this page:
Page Notes
Yukon EC: Pin 42 should be NC (or TP) net.
- Use 0-ohm resistors or variable supply to provide 1.8V or 2.5V to =PP1V8R2V5_ENET_PHY
- Use YUKON_EC and YUKON_ULTRA BOMOPTIONs to select stuffed part- Connect =ENET_CLKREQ_L to clock generator via 0-ohm resistor (BOMOPTION: YUKON_ULTRA)
- Alias =YUKON_EC_PP2V5_ENET to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF and 1x 0.001uF caps
10 Mbps: 70 mANo link: 60 mA
SIGNAL_MODEL=EMPTY
402
1/16W1%
MF-LF
49.9
SIGNAL_MODEL=EMPTY
402
1%
MF-LF
49.91/16W
37 87
37 87
37 87
37 87
37 87
37 87
37 87
37 87
24 87
24 87
10%
CERM50V
0.001UF
402
10%
CERM50V
0.001UF
402
10%
CERM50V
0.001UF
402
10%
CERM50V
0.001UF
402
1/16W
SIGNAL_MODEL=EMPTY
402
1%
MF-LF
49.9
SIGNAL_MODEL=EMPTY
402
1%
MF-LF
49.91/16W
SIGNAL_MODEL=EMPTY
402
1%
MF-LF
49.91/16W
SIGNAL_MODEL=EMPTY
402
1%
MF-LF
49.91/16W
SIGNAL_MODEL=EMPTY
402
1%
MF-LF
49.91/16W
SIGNAL_MODEL=EMPTY
402
1/16W1%
MF-LF
49.9
0.1uF 10% X5R 40216V
0.1uF 10% 16V X5R 402PLACEMENT_NOTE=Place C3730 close to southbridge.
16V10%0.1uF X5R 402
PLACEMENT_NOTE=Place C3731 close to southbridge.
402X5R16V10%0.1uF
24 87
24 87
28
25 34
30
30 88
30 88
BOMOPTION=OMITCRITICAL
88E8058QFN
66
YUKON_ULTRA
4.99K
402MF-LF1/16W1%
CERM6.3V20%
4.7UF
603
50VCERM
0.001UF
402
10%0.1UF
402
16V10%
X5R402
0.1UF16V10%
X5RX5R
10%16V
402
0.1UF
402
10%0.001UF50VCERM
0.1UF
402
16V10%
X5R
0.1UF
402
16V10%
X5RX5R
10%16V
402
0.1UF6.3V20%
603
4.7UF
CERM CERM50V
0.001UF
402
10%
0.1UF
X5R
10%16V
402
0.1UF
X5R
10%16V
402X5R
10%16V
402
0.1UF
X5R
10%16V
402
0.1UF0.1UF
402
16V10%
X5R603
4.7UF20%
6.3VCERM
10%
402
0.001UF50VCERM
10%
402
0.001UF50VCERM
10%
402
0.001UF50VCERM
SO8M24C08
OMIT
CRITICAL
X5R
10%16V
402
0.1UF 4.7K5%
402MF-LF1/16W
4.7K5%
402MF-LF1/16W
5%4.7K
402MF-LF1/16W
FERR-120-OHM-1.5A
0402
36
36
114S0285 1 YUKON_ECRES,4.87K,1%,1/16W,0402,LF R3760
CRITICAL1 YUKON_EC341S1797 IC,EEPROM,SERIAL IIC,8KBIT,SO8 U3780
CRITICAL1 U3780 YUKON_ULTRA341S2060 IC,FLASH,88E8058 ETHERNET VPD,IIC,SO8
1338S0386 U3700 CRITICAL YUKON_ULTRAIC,88E8058,GIGABIT ENET XCVR,64P QFN
YUKON_EC1 U3700338S0270 IC,88E8053,GIGABIT ENET XCVR,64P QFN CRITICAL
051-7261 A.0.0
92
Ethernet (Yukon)
35
SYNC_MASTER=T9_NOME SYNC_DATE=01/25/2007
ENET_MDI_P<3>ENET_MDI_N<3>
ENET_CLK25M_XTALOENET_CLK25M_XTALI
ENET_RESET_L
ENET_MDI_P<0>
PCIE_WAKE_L
PCIE_CLK100M_ENET_N
=ENET_CLKREQ_L
ENET_MDI_N<0>
ENET_MDI_N<1>
PCIE_CLK100M_ENET_P
ENET_MDI_P<1>
ENET_MDI_N<2>ENET_MDI_P<2>
PCIE_ENET_D2R_C_P
YUKON_VPD_CLK
ENET_MDI3ENET_MDI2ENET_MDI1ENET_MDI0
ENET_LOM_DIS_L
YUKON_RSET
=ENET_VMAIN_AVLBL
TP_YUKON_CTRL12TP_YUKON_CTRL18
PCIE_ENET_D2R_C_N
PCIE_ENET_R2D_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
YUKON_VPD_DATA
PCIE_ENET_R2D_P
=PP1V2_ENET_PHY
PP1V8R2V5_ENET_PHY_AVDDMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.8V
=PP1V8R2V5_ENET_PHY
=YUKON_EC_PP2V5_ENET
=PP3V3_ENET_PHY
R37401
2
R37411
2
C37401
2
C37421
2
C37441
2
C37461
2
R37421
2
R37431
2
R37471
2
R37461
2
R37451
2
R37441
2
C3735 1 2
C3736 1 2
C3730 1 2
C3731 1 2
U3700
19
22
23
28
8
42
3
4
59
63
62
60
10
18
21
27
31
17
20
26
30
32
51
52
57
64
5
56
55
16
24
25
29
43
53
54
37
36
35
34
9
11
46
65
50
49
12
2 7 13
33
39
44
48
58
1 40
45
61
47
38
41
6
15
14
R37651
2
C3720 1
2
C37241
2
C37231
2
C37221
2
C37211
2
C37141
2
C37131
2
C37121
2
C37111
2
C3710 1
2
C37151
2
C37051
2
C37041
2
C37031
2
C37021
2
C37011
2
C3700 1
2
C37081
2
C37071
2
C37061
2
U3780
3
1
2
6
5
8
4
7
C37801
2
R37801
2
R37811
2
R37601
2
L3720
1 2
87
87
87
87
8
37
8
8
8
Page 36
OUT
THRM_PAD NC
IN1
EN
IN2
OUT1
OUT2
NR/FB
GND
IN
OUT
G
D
SIN
G
D
S G
D
S IN
OUT
G
DS
G
D
S
G
D
S
G
D
SIN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
"ENET" = "S0" || ("S3" && "AC" && "WOL_EN")
NOTE: S3 term is guaranteed by source of R3800 & Q3810, MUST BE S3 RAIL.
EC: Vout = 2.510V
Yukon Ultra requires 1.9V on its magnetics to pass compliance tests
Yukon AVDDL LDO
WLAN Enable Generation"WLAN" = "S0" || ("S3" && "AC" && "WOW_EN")
NOTE: S3 term is guaranteed by FET & pull-up source, MUST BE S3 RAIL.
Ultra: Vout = 1.912V
(PM_SLP_S3_L)
3.3V ENET FET
NC
500 mA max output(U3850 limit)
Vout = 1.2246V * (1 + Ra / Rb)
NC
1.9V for Yukon Ultra, 2.5V for Yukon EC
ENET Enable Generation
(AC_EN_L)
Yukon Crystal
NC
7 66
CRITICAL
SONLREG_TPS79501DRB
10%
402CERM6.3V
1UF1UF6.3VCERM402
10%
16.9K1%1/16WMF-LF402
YUKON_ULTRA
MF-LF
30.1K1%1/16W
402
5%50V
CERM402
33PF
SM-3.2X2.5MM25.0000M
CRITICAL
CERM402
50V5%18PF
CERM
5%50V
402
18PF
35
35
2N7002DW-X-FSOT-363
40 45 46 57
402
10%
CERM
0.22UF10V
SOT-3632N7002DW-X-F 2N7002DW-X-F
SOT-363
13 24
34
1/16W5%
MF-LF
100K
402
10K
MF-LF
5%1/16W
402
10%16V
402
0.01UF
CERM
SOT-23NTR4101P
10%16V
402X5R
0.033UF5%
1/16W
10K
402MF-LF
SOT-3632N7002DW-X-F
SOT-3632N7002DW-X-F
2N7002DW-X-FSOT-363
7 25 40 45 66
25
1 R3855 YUKON_ECRES,31.6K,1%,1/16W,402,LF114S0363
SYNC_DATE=03/19/2007SYNC_MASTER=T9_NOME
36 92
A.0.0051-7261
Yukon Power Control
PM_ENET_EN_L
WOL_EN
PM_SLP_S3_L
AC_EN_L
=PP3V3_ENET_AVDDLDO
ENET_CLK25M_XTALIENET_CLK25M_XTALO
PM_ENET_EN
SMC_ADAPTER_EN
WOW_EN
ENETAVDDL_FB
=PPVOUT_ENET_AVDDLDO
P3V3ENET_SS
=PP3V3_ENET_FET=PP3V3_S3_P3V3ENETFET
PM_WLAN_EN_L
R38101 2
R38111
2C3810
12
Q3810
3
1
2
C38111
2
R38001
2
Q38013
5
4
Q38003
5
4
Q38016
2
1
U3850
8
6
1
2
7
5
3
4
9
C3850 1
2
C38511
2
R38551
2
R38561
2
C3855 1
2
Y3860
24
13
C38611
2
C3860 1
2
Q38006
2
1
C3800 1
2
Q38053
5
4
Q38056
2
1
8 8
8 8
Page 37
SYM_VER2
NC2 NC3NC4
LINE
SIDE
CHIP
SIDENC1
SYM_VER2
NC2 NC3NC4
LINE
SIDE
CHIP
SIDENC1
BI
BI
BI
BI
BI
BI
BI
BI
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
Place one cap at each pin of transformer
- =GND_CHASSIS_ENET
New Series Rs required for European Telecom Compliance
Place close to connector
(NONE)
(NONE)
514-0277Short shielded RJ-45
BOM options provided by this page:
Signal aliases required by this page:
Power aliases required by this page:
Page Notes
mirrored on oppositeTransformers should be
sides of the board
402NONE
NONE
SHORT
NONE
OMIT
402CERM
1uF6.3V10%
6.3V
402CERM
10%1uF
755%1/16W
402MF-LF
1/16W5%
402MF-LF
7575
MF-LF402
5%1/16W
75
402
5%
MF-LF1/16W
CERM
10%1uF
402
6.3V
402
10%6.3VCERM
1uF
OMIT
XFR-SM
CRITICAL1000BT-824-00275
1000BT-824-00275
XFR-SM
CRITICALOMIT
35 87
35 87
35 87
35 87
35 87
35 87
35 87
35 87
9
CRITICAL
JM36113-P2054-7FF-RT-TH-RJ45
402NONE
NONE
SHORT
NONE
OMIT
402NONE
NONE
SHORT
NONE
OMIT
402NONE
NONE
SHORT
NONE
OMIT
1206
1000PF
CERM2KV10%
CRITICAL
CRITICALT3900,T3901XFMR,ISO,HALF-PORT,1000T,16P,SMD,2MM2157S0030
SYNC_DATE=12/21/2006SYNC_MASTER=M75_MLB
A.0.0
37
051-7261
92
Ethernet Connector
ENET_MDI_N<3>
ENET_MDI_P<3>
ENET_MDI_N<2>
ENET_MDI_P<2>
ENET_MDI_N<1>
ENET_MDI_P<1>
ENET_MDI_N<0>
ENET_MDI_P<0>
=GND_CHASSIS_ENET
ENET_CTAP0
ENET_CTAP3
ENET_CTAP1
ENET_CTAP2
ENETCONN_P<1>
ENETCONN_N<0>
ENETCONN_P<0>
ENETCONN_N<1>
ENETCONN_P<3>
ENETCONN_N<2>
ENETCONN_P<2>
ENETCONN_N<3>
ENET_CTAP_COMMONMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
PP1V8R2V5_ENET_PHY_AVDD
RX39101 2
C39031
2
C39021
2
R39031
2
R39021
2
R39011
2
R39001
2
C39011
2
C39001
2
T39001
10
11
14
15
16
2
3
6
7
8 9
4
5 12
13
T39011
10
11
14
15
16
2
3
6
7
8 9
4
5 12
13
J3900
9
10
11
12
1
2
3
4
5
6
7
8
RX39111 2
RX39911 2
RX39901 2
C39041 2
91
91
91
91
91
91
91
91
35
Page 38
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
IN
IN
IN
OUT
BI
BI
BI
BI
BI
BI
OUT
IN
IN
BI
OUT
SDA
SCL
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD31
PCI_AD30
PCI_AD28
PCI_AD29
PCI_AD27
PCI_AD25
PCI_AD26
PCI_AD24
PCI_AD23
PCI_AD21
PCI_AD20
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_PAR
PCI_CLK
PCI_IDSEL
GND
PCI_AD1
PCI_AD0
VCC
MFUNC
G_RST_L
REG18_1
REG18_0
REG_EN_L
PHY_PINT
PHY_PCLK
PHY_LREQ
PHY_LPS
PHY_LINKON
PHY_LCLK
PHY_D7
PHY_D6
PHY_D5
PHY_D4
PHY_D3
PHY_D1-D1
PHY_D2
PHY_D0-D0
PHY_CTL1-CTL1
PHY_CTL0-CTL0
PCI_ACK64_L
PCI_TRDY_L
PCI_STOP_L
PCI_SERR_L
PCI_RST_L
PCI_REQ64_L
PCI_REQ_L
PCI_PME_L
PCI_PERR_L
PCI_IRDY_L
PCI_INTA_L
PCI_GNT_L
PCI_FRAME_L
PCI_DEVSEL_L
VCCP
PCI_AD22
PCI_C_BE2_L
PCI_C_BE0_L
PCI_C_BE3_L
PCI_C_BE1_L
G
D
S
IN
G
D
S
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(FW_G_RST_L)Might use
a GPIOMFUNC as
G_RST* assertion min 2ms
(OK if VCCP and VCC are
It must not be taken high
aliased to the same rail)
G_RST* is clamped to VCCP
when there’s no power on VCCP
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
25
24 87
30 88
24 87
28
1uF10VX5R402
10%10V
402X5R
1uF10%
10V
402X5R
1uF10%
10V
402X5R
10%1uF
10V
1uF10%
X5R402
10%1uF10VX5R402
10%
X5R10V
402
1uF
402MF-LF1/16W5%4.7K
1/16WMF-LF
402
5%4.7K
24 87
39
39
39
39
39
39
220
402MF-LF1/16W
5%1K
402MF-LF1/16W
5%2205%1/16WMF-LF402
39 89
39 89
39 89
39 89
39 89 10K5%
1/16WMF-LF
402
TSB83AA22CZAJ
CRITICAL
(2 OF 2)BGA
SOT-3632N7002DW-X-F
39
2N7002DW-X-FSOT-363
100K
402MF-LF1/16W5%
10K5%1/16WMF-LF402 45
28
402MF-LF1/16W
5%22
16V10%
402X5R
0.1uF
402X5R16V10%0.1uF
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
24 87
SYNC_DATE=12/04/2006SYNC_MASTER=M75_MLB
38 92
A.0.0051-7261
FireWire Link (TSB83AA22)
CLKFW_LINK_PCLK
FW_LLC_PP1V8LDO_EN_L
PCI_REQ64_L
PCI_IRDY_LPCI_PERR_L
PCI_DEVSEL_L
PCI_FW_REQ_L
FW_SCLFW_SDA
FW_MFUNC
PCI_AD<19>
FW_PCI_IDSEL
PCI_AD<18>PCI_AD<17>PCI_AD<16>PCI_AD<15>PCI_AD<14>PCI_AD<13>PCI_AD<12>PCI_AD<11>PCI_AD<10>
PCI_AD<31>PCI_AD<30>
PCI_AD<28>PCI_AD<29>
PCI_AD<27>
PCI_AD<25>PCI_AD<26>
PCI_AD<24>PCI_AD<23>
PCI_AD<21>PCI_AD<20>
PCI_AD<9>PCI_AD<8>PCI_AD<7>PCI_AD<6>PCI_AD<5>PCI_AD<4>PCI_AD<3>PCI_AD<2>
PCI_CLK33M_FW
PCI_AD<1>PCI_AD<0>
FW_PINT
FW_LREQFW_LPSFW_LINKONCLKFW_PHY_LCLKFW_DATA<7>FW_DATA<6>FW_DATA<5>
FW_DATA<3>
TP_FW_DATA<1>
FW_DATA<2>
TP_FW_DATA<0>
TP_FW_CTL<1>TP_FW_CTL<0>
PCI_STOP_LPCI_SERR_LPCI_FW_RST_L
PCI_PME_FW_L
PCI_C_BE_L<0>
PCI_C_BE_L<3>
PCI_AD<22>
PCI_C_BE_L<2>PCI_C_BE_L<1>
PCI_PAR
FW_DATA<4>
=PP1V8_S3_FW
FW_PLT_RST_L
=PP3V3_S3_FW
FW_G_RST_LSMC_RSTGATE_L
PLT_GATED_RST
PCI_TRDY_LPCI_ACK64_L
PCI_FRAME_LPCI_FW_GNT_LINT_PIRQD_L
=PP3V3_S3_FW=PP3V3_S3_PCI
U4000
E4
C7C8
F7F8F9
F10G6G7G8G9
G10H6
D6
H7H8H9
H10J8J9
J10
K10
D7E6E7E8E9
E10F6
A1
N12
L12N11
N6M6M7K9K8M5K3N1L4M2
M11
M1L1J4H3H4J3H2G3H1F1
N10
F2G4
M10K12M9N9L8M8
N8M3K5K2
D3
N2L3E3
L2
B3K4
N3
L6F4
J13F3
D1L7L5J5
F13F12
E13E12
C13B9B10C11B12A11B7B4A2D4B6A3
G11G12
C2
C3C4
D5
D8
D9
E5
F5H11
J6
J7J11
E11
F11
R40001
2C40101
2
C40111
2
C40081
2
C40091
2C40041
2
C40031
2
C40021
2
C40011
2
C40001
2
R40021
2
R40011
2
R40901
2
R40801
2
R40911
2
R40101
2
Q40703
5
4
Q40706
2
1
R40701
2
R40711
2
38
38
8
8
8
8
Page 39
SE
SM
RESET
D7
D5
D6
D4
D3
D2
CPS
PD
BMODE
PC2
PC0
PC1
LREQ
LPS
DS1
LCLK
DS0
XI
R1
R0
TESTM
TESTW
TPBIAS0
TPBIAS1
TPB1N
TPB1P
TPB0N
TPB0P
TPA1N
TPA1P
TPA0P
TPA0N
PINT
PCLK
AVDD_3P3
DVDD_3P3
DVDD_CORE
PLLVDD_3P3
PLLVDD_CORE
PLLGND
LKON_DS2
CNA
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT TRI-ST/NC
VCC
GND
IN
IN
IN
OUT
BI
BI
BI
BI
BI
BI
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
R4160 provides isolation between R4161 and unpowered LLC.
No need for DS2 pull-down on TSB83AA22A,as 3rd FireWire port is not pinned out.
Power Class:Single-port / Desktop systems are Power Class 0 (’000’).
Strap via alias on port page.
Implement 1K pull-up or pull-down on port page.Multi-port Portable systems are Power Class 4 (’100’).
DSx Straps:Hi: Data-Strobe only (1394a).Lo: Beta Mode enable (1394b).
PHY power-up reset.
C4150 with internalpull-up provides
NC
(IPU)
NC
1MA (MAX) BUS HOLDERS
0.22uF
X5R402
20%6.3V
402MF-LF1/16W
5%390K
CRITICAL
(1 OF 2)BGA
TSB83AA22CZAJ
16V20%
402CERM
0.01uF
10V10%
402X5R
1uF
1uF
X5R402
10%10V
41 89
41 89
41 89
41 89
41 89
41 89
41 89
41 89
38 89
41
41
10V10%
402X5R
1uF 1uF10V10%
402X5R
10V10%
402X5R
1uF
10V10%
402X5R
1uF10%10V
402X5R
1uF 1uF10V10%
402X5R
1uF10V10%
402X5R
SM98P3040MHZ
CRITICAL
38 89
38 89
38 89
38 89
38
38
38
38
38
38
5%1/16W
402MF-LF
1K
402
5%
MF-LF1/16W
1K
10V10%
402X5R
1uF10V10%
402X5R
1uF
6.3V10%
603CERM1
2.2uF
41
402MF-LF1/16W
5%10K
402MF-LF1/16W5%4.7
1/16W5%
402MF-LF
1
1/16W5%
402MF-LF
1
1
MF-LF402
5%1/16W
1/16W5%
402MF-LF
470
1/16W1%
MF-LF
6.34K
402
5%1/16WMF-LF402
1K38
22
MF-LF402
5%1/16W
6.3V20%
402X5R
0.22uF
1/16W5%
402MF-LF
1K1K
MF-LF402
5%1/16W 1/16W
5%
402MF-LF
1K
FireWire PHY (TSB83AA22)SYNC_DATE=12/04/2006
051-7261 A.0.0
9239
SYNC_MASTER=M75_MLB
FWPHY_R0
FW_0_TPBIASVOLTAGE=1.86V
=PP3V3_FW_PHY
FW_1_TPBIASVOLTAGE=1.86V
CLKFW_LINK_PCLK
FWPHY_TESTM
FW_PINT
FW_0_TPA_P
FW_1_TPA_N
FW_1_TPB_NFW_1_TPB_P
FWPHY_R1
=PPVP_FW_CPS
FWPHY_DS0FWPHY_DS1
FWPHY_TESTW
FW_LINKON
FWPHY_CPS
FWPHY_BMODE
FW_0_TPA_N
CLKFW_PHY_LCLK
FW_DATA<2>
FW_DATA<7>FW_DATA<6>FW_DATA<5>FW_DATA<4>FW_DATA<3>
=FWPHY_DS0
FW_LINKON_R
=FWPHY_PC0
FW_0_TPB_N
FWPHY_CLK98P304
=PP1V8_FW_PHYOSC
PP1V8_FW_PHYOSC_RMIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.25 mm
VOLTAGE=1.8V
FWPHY_CLK98P304M_R
FW_LPS
FWPHY_RESET_L
=FWPHY_DS1
FW_LREQ
FW_0_TPB_P
FW_1_TPA_P
PP1V95_FW_PHY_PLLVDDMIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.22 mmVOLTAGE=1.95V
=PP1V95_FW_PHY
PP3V3_FW_PHY_AVDDMIN_NECK_WIDTH=0.22 mmMIN_LINE_WIDTH=0.38 mm
VOLTAGE=3.3V
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.25 mm
PP3V3_FW_PHY_PLLVDD
R41801 2
C41801
2
R41911
2
R41401
2
R41901
2
C41501
2
R41551
2
U4000
D10
D11
G5
H5
L9
M12
A5
D13
C9
C10
C12
B13
B11
A6
B8
D12
H12
J12
K7
K6
C5
C6
G13
L13
N13
K13
N4
M4
N5
H13
K11
M13
A10
A7
A8
A12
A13
L10
A4
B5
L11
N7
E2
E1
J1
J2
B1
C1
G1
G2
D2
K1
A9
C41101
2
C41021
2
C41211
2
C41011
2
C41031
2
C41041
2
C41111
2
C41121
2
C41131
2
C41141
2
G4180
2
3 1
4
R414512
R414212
C4131 1
2
C4130 1
2
C41351
2
R41561
2
R41861
2
R41001 2
R41351 2
R41201 2
R41611
2
R41621
2
R41601 2
41 8
8
41
8
41
8
Page 40
V-
V+
S
G
D
S
G
D
GND
SENSEB
OUTA
FAULTB_L
FAULTA_L
ONB
INB
ONA
ONQ1
INA
GATE1A
GATE2A
SENSEA
GATE1B
GATE2B
OUTB
G
D
S
G
D
SIN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
FireWire Port Power Switch- =PPVP_FW_SUMNODE (power passthru summation node)
- FW_PORT_FAULT_PUBOM options provided by this page:
(NONE)Signal aliases required by this page:
- =PP3V3_FW_LATEVG_ACTIVE- =PPBUS_S5_FWPWRSW (system supply for bus power)Power aliases required by this page:
spikes. Current limit has been set higher to compensate.
and -1/128 if under the limit. As a result, the device
reaches 16. A new sample (taken every 125 us) is weightedas +1 if over the limit (at any point during the period)
0.025 ohm => 2A
0.033 ohm => 1.5A
2.81V on late Vg event and port power is off2.95V when port power is onFWLATEVG_3V_REF Hysteresis:
Enables port power when machineis running or on AC.
Current Limits
0.020 ohm => 2.4A
NC
Late-VG Event Detection
NC
Page Notes
0.030 ohm => 1.66A (Ideal)
MAX5944 current limiter trips if integrator (counter)
tends to trip easily on devices that produce periodic current
SENSEB PINS RESPECTIVELY. SENSEA & SENSEB PINS SHOULD NOT BE PART OFR4220 & R4225 PADS SHOULD BE ROUTED DIRECTLY TO MAX5944 SENSEA &
THE MAIN CURRENT PATH
Current Limit/Active Late-VG Protection
2.0M
MF-LF402
5%1/16W
0.33UF
CERM-X5R603
10%10V
10V20%
402CERM
0.1UF
1/16W1%
402MF-LF
200K
SM-LFLMC7211
10K
MF-LF402
5%1/16W
50V5%
CERM
100pF
402
10K
402
1%1/16WMF-LF
1/16W1%
402MF-LF
80.6K
MBR0540XXG
SOD-123
CRITICAL
SI2318DSSOT23-3
CRITICAL
SOT23-3SI2318DS
CRITICAL
X7R805
10%1uF35V35V
10%
805X7R
1uF
CRITICAL
0.020
0.25W1%
MF805
CRITICAL
SOICMAX5944
CRITICAL
CRITICAL
0.25W
805
0.020
1%
MF
FW_PORT_FAULT_PU
MF-LF1/16W5%
402
100K
NDS9407
CRITICAL
SOI-LF
0.01uF
CERM402
20%16VMF-LF
5%1/16W
470K
402
SOT-3632N7002DW-X-F
5%330K
MF-LF1/16W
402
SOT-3632N7002DW-X-F
36 45 46 57
7 25 36 45 66
1.5A-24V
CRITICAL
MINISMDC
PWRDI5
CRITICAL
PDS540XF
SYNC_DATE=03/07/2007SYNC_MASTER=M75_MLB
FireWire Port Power
9240
051-7261 A.0.0
PPVP_FW_PORTA_ISENSEMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
VOLTAGE=33V
LATEVG_EVENT_L
=PPVP_FW_SUMNODE
VOLTAGE=33VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPPVP_FW_PORTB_UF
FW_PORTB_PWRCTRL
FWLATEGV_3V_REF
PPVP_FW_PORTA_UF
VOLTAGE=33VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
PPVP_FW_PORTB_ISENSE
VOLTAGE=33VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
FW_PORTA_PWRCTRL
FW_PORTPWR_DISABLE_LFW_PORT_FAULT_L
PM_SLP_S3_L
SMC_ADAPTER_EN
FWPWR_EN_L
P2V4_FWLATEVG_RC
PP2V4_FW_LATEVG
FWPWR_EN_L_DIV
PPBUS_FW_FWPWRSW_F
VOLTAGE=12.6VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
=PP3V3_FW_LATEVG_ACTIVE
=PPBUS_S5_FWPWRSW=PPBUS_S5_FW_FET
VOLTAGE=12.6V
PPBUS_FW_FWPWRSW_DMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
R42191
2
C42191
2
C42101
2
R42101 2
U42104
3
1
5
2
R42111
2
C4211 1
2
R42121
2
R42131
2
D421912
Q4220
3
1
2
Q4225
3
1
2
C42251
2
C4220 1
2
R42201 2
U4220
3
11
15
7
14
6
12
1
9
2
10
4 13
5
16
8
R42251 2
R42291
2
Q4260
5
6
7
8
4
1
2
3
C4260 1
2
R42601
2
Q42616
2
1
R42611
2
Q42613
5
4
F42601 2
D4260
1
2
3
8
8
8
41
8
8
8 8
Page 41
TPO#
TPI
TPO
TPI#
VGND
VP
SYM_VER-2
SYM_VER-2
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
FW spec calls out 0.33uFTI PHYs require 1uF even though
Place close to FireWire PHY
ESD and late-VG railfor snap-back diodes(Common to all ports)
and should be biased to 2.4V for marginto at least 2.1V for FW signal integrity
R4390 should be 390 Ohms max for a 3.3V rail
(NONE)
- =GND_CHASSIS_FW_EMI_R
- =PPVP_FW_PORT0
appropriate connectors and/or to
assumed that FireWire PHY page will
to apply to entire TPA/TPB XNets.
FireWire Design Guide (FWDG 0.6, 5/14/03)1394b implementation based on Apple Termination
- Port "0" Data-Strobe only (1394A)- 2-port Portable Power Class (4)
Configures PHY for:
- Port "1" Bilingual (1394B)
PP2V4_FWLATEVG needs to be biased
Late-VG Protection Power
Page Notes
- =PPVP_FW_PORT1- =PP3V3_FW_LATEVG
- =GND_CHASSIS_FW_PORT0U- =GND_CHASSIS_FW_PORT1
properly terminate unused signals.
BOM options provided by this page:
NOTE: FireWire TPA/TPB pairs are NOT constrained on this page. It is
provide the appropriate constraints
FireWire PHY Config StrapsSignal aliases required by this page:
NOTE: This page is expected to contain the necessary aliases to map the
(TPB-)
Cable Power
TPB-
TPB<R>
TPA-
TPA<R>
TPA+
TPB+
VP
VG
NCNC
BILINGUAL
between them (to avoid ground offset issue)
(FW_PORT1_BREF)
BREF should be hard-connected to logic
detection currents per 1394b V1.33
local grounds per 1394b spec
beta-only device, there is no DC path
"Snapback" & "Late VG" Protection
1394A
Note: Trace PPVP_FW_PORT0 must handle up to 5A
(TPB+)
(TPA+)
(TPA-)
PORT 0
514-0255
(GND_FW_PORT0_VG)
(PPFW_PORT0_VP)
INPUT
OUTPUT
PORT 1
(GND_FW_PORT1_VG)
Note: Trace PPVP_FW_PORT1 must handle up to 5A
(PPVP_FW_PORT1)
Cable Power
ground for speed signaling and connection
When a bilingual device is connected to a
AREF needs to be isolated from all
514S0133
Power aliases required by this page:
- =GND_CHASSIS_FW_PORT0L
(NONE)
FireWire TPA/TPB pairs to their
"Snapback" & "Late VG" Protection
1uF
CERM402
10%6.3V
1/16W1%
402MF-LF
56.21/16W1%
402MF-LF
56.2
1/16W1%
402MF-LF
56.2
SIGNAL_MODEL=EMPTY
1/16W1%
402MF-LF
56.2
SIGNAL_MODEL=EMPTY
4.99K
MF-LF402
1%1/16W
220pF
CERM402
5%25V
CRITICAL
FERR-250-OHM
SM
CERM402
20%50V
0.001uF
BAV99DW-X-FSOT-363
CRITICAL
1394AF-RT-TH-LF
50VCERM603
20%0.01uF
BAV99DW-X-FSOT-363
402
10%0.01uF
50VX7R
BAV99DW-X-FSOT-363
0.01uF50V10%
402X7R
50V10%
402X7R
0.01uF
BAV99DW-X-FSOT-363
0.01uF
X7R402
10%50V
1/16W1%
402MF-LF
56.2
4.99K
MF-LF402
1%1/16W
1/16W1%
402MF-LF
56.2
220pF
CERM402
5%25V
1/16W1%
402MF-LF
56.2
1uF
CERM402
10%6.3V
1/16W1%
MF-LF402
56.2
0.01uF
CERM402
20%16V
NO STUFF
PLACEMENT_NOTE=Place C4319 close to connector pin 5.
0.1uF
X7R603-1
10%50V
1M1/16W5%
402MF-LF
CERM402
20%50V
0.001uF
FERR-250-OHM
CRITICAL
SM
CERM603
20%50V
0.01uF
402NONE
NONESHORT
NONE
OMIT
X7R402
10%50V
0.01uF
SOT-363BAV99DW-X-F
X7R402
0.01uF50V10%
SOT-363BAV99DW-X-F
SOT-363BAV99DW-X-F
SOT-363BAV99DW-X-F
X7R402
10%50V
0.01uF
0.01uF
402X7R
10%50V
332
MF-LF402
1%1/16W
CRITICAL
MMBZ5227BSOT23
1394B-UG31903F-RT-SM1
CRITICAL
CRITICAL
1210-4SM190-OHM-100MA
90-OHM-100MA1210-4SM1
CRITICAL
0402
CRITICAL
18NH-250MA
0402
18NH-250MA
CRITICAL
0402
CRITICAL
18NH-250MA
SIGNAL_MODEL=EMPTY0402
SIGNAL_MODEL=EMPTY
18NH-250MA
CRITICAL
402NONE
NONESHORT
NONE
OMIT
402NONE
NONESHORT
NONE
OMIT
402NONE
NONESHORT
NONE
OMIT
402NONE
NONESHORT
NONE
OMIT
402NONE
NONESHORT
NONE
OMIT
402NONE
NONESHORT
NONE
OMIT
402NONE
NONESHORT
NONE
OMIT
FireWire PortsSYNC_MASTER=M75_MLB SYNC_DATE=12/04/2006
9241
A.0.0051-7261
=FWPHY_DS1
FW_B_TPB_L_P
FW_PORT1_TPB_N
FW_PORT1_TPB_P
=GND_CHASSIS_FW_PORT1
FW_PORT1_TPA_NFW_PORT1_AREF
FW_PORT1_TPA_P
PP2V4_FW_LATEVG
=GND_CHASSIS_FW_PORT1MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=33V
PPVP_FW_PORT1
=GND_CHASSIS_FW_PORT0U
FW_PORT0_TPB_P
PP2V4_FW_LATEVG
FW_PORT0_TPA_P
PPVP_FW_PORT0MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=33V
=GND_CHASSIS_FW_PORT0L
=GND_CHASSIS_FW_PORT0L
FW_PORT0_TPB_N
=PPVP_FW_PORT0
FW_PORT0_TPA_FL_PFW_PORT0_TPA_N
=PPVP_FW_PORT1
FW_PORT0_TPB_FL_P
FW_PORT0_TPA_FL_N
FW_PORT0_TPB_FL_N
PP2V4_FW_LATEVGMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mm
VOLTAGE=2.4V
FW_1_TPBIAS
FW_B_TPA_L_P
FW_0_TPA_P
FW_0_TPA_N
FW_1_TPA_N
FW_0_TPBIAS
FW_0_TPB_P
=FWPHY_PC0=FWPHY_DS0
=PP3V3_FW_PHY
FW_B_TPA_L_N
=PP3V3_FW_LATEVG
FW_PORT1_TPB_NMAKE_BASE=TRUE
MAKE_BASE=TRUEFW_PORT1_TPA_N
MAKE_BASE=TRUEFW_PORT1_TPB_P
MAKE_BASE=TRUEFW_PORT1_TPA_P
FW_PORT0_TPB_PMAKE_BASE=TRUEFW_PORT0_TPB_NMAKE_BASE=TRUE
FW_PORT0_TPA_NMAKE_BASE=TRUE
FW_PORT0_TPA_PMAKE_BASE=TRUE
FW_PORT0_TPB_C
FW_0_TPB_N
FW_PORT1_TPB_C
FW_1_TPB_N
FW_1_TPB_P
FW_1_TPA_P
FW_B_TPB_L_N
C43501
2
R43511
2
R43501
2
R43531
2
R43521
2
R43541
2
C43541
2
L4300
1 2
C43041
2DP4300
4
5
3
J4300
7 8 9 10
4
3
6
5
2
1
C43051
2
DP4301
4
5
3
C4301 1
2
DP4300
1
2
6
C4300 1
2
C4303 1
2
DP4301
1
2
6C4302 1
2
R43631
2
R43641
2
R43621
2
C43641
2
R43611
2
C43601
2
R43601
2
C4317 1
2
C4319 1
2
R43191
2
C43141
2
L4310
1 2
C43151
2
CX4304 1
2
C4310 1
2
DP4310
1
2
6
C4311 1
2
DP4310
4
5
3
DP4311
1
2
6DP4311
4
5
3C4313 1
2
C4312 1
2
R43901 2
D4390
1
3
J4310
1
10
11
2
3
4
5
6
7
8
9
FL4300
1
2 3
4
FL4301
1
2 3
4
L4360
1 2
L4361
1 2
L4362
1 2
L4363
1 2
CX4305 1
2
CX4306 1
2
CX4307 1
2
CX4302 1
2
CX4303 1
2
CX4300 1
2
CX4301 1
2
41
41
41
41
41
41
89
89
89
89
39
89
89
89
89
39
41
41
41
41
40
9
9
41
40
41
9
9
41
8
91 41
8
91
91
91
40
39
39
39
39
39
39
39
39
8
8
41
41
41
41
41
41
41
41
39
39
39
39
Page 42
BI
BI
IN
IN
IN
IN
OUT
OUT
OUT
OUT
G
D
S
G
D
S
IN
IN
IN
Y
B
A
S
G
D
IN
BI
BI
BI
BI
BI
IN
BI
BI
BI
IN IN
IN
OUT
BI
BI
BI
BI
BI
BI
BI
BI
IN
OUT
OUT
INOUT
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
10K pull-up to 5V)
(UATA_DSTROBE)
(UATA_CS0*)
Placement notePlace within 12.7mmfrom ball of SB
Unused SATA Ports
IDE (ODD) Connector
(UATA_CS1*)
(UATA_STOP)
516S0335
NC
(UATA_HSTROBE)
(SB has internal 5.7k-23.5k pull-down)
Indicates disk presence
(ODD has internal
23
23
23 86
23 86
23 86
23 86
23 86
23 86
23 86
23 86
SOT-3632N7002DW-X-F
2N7002DW-X-FSOT-363
1/16W5%
402MF-LF
100K
24
CRITICAL
M-ST-SM1-LF
23 86
CERM
10%0.068UF
10V
402
24 86
MC74VHC1G09SC70
100K
MF-LF402
5%1/16W
CRITICAL
SOT-6
FDC606P
23 86
23 86
23 86
23 86
23 86
23 86
42
402MF-LF1/16W
24.91%
23 86
23 86
23 86
23 86 23 86
23 86
402
4.7K
MF-LF
5%1/16W
6.2K
MF-LF402
5%1/16W
45
402MF-LF1/16W5%33K
10K1/16WMF-LF
402
5%
23 86
23 86
23 86
23 86
23 86
23 86
23 86
23 86
23 86
23 86
23 86
23 86 23 86
23 86
16V
0.01UF
10%
CERM402
47K
1/16WMF-LF
5%
402
PATA Connector
051-7261 A.0.0
42 92
SYNC_MASTER=M75_MLB SYNC_DATE=12/07/2006
=PP5V_S0_ODD
MIN_NECK_WIDTH=0.4 mmMIN_LINE_WIDTH=0.6 mmPP5V_ODD
VOLTAGE=5V
P5VODD_SS
=PP3V3_S0_IDE
ODD_PWR_EN_L
IDE_PDDREQ
IDE_PDIORDYIDE_IRQ14
SMC_ODD_DETECT
IDE_PDA<0>
IDE_PDD<6>IDE_PDD<5>
IDE_PDD<1>
IDE_PDIOR_L
IDE_PDA<2>
IDE_PDD<8>IDE_PDD<9>IDE_PDD<10>IDE_PDD<11>
IDE_PDD<12>IDE_PDD<13>IDE_PDD<14>IDE_PDD<15>
IDE_PDIOW_LIDE_PDDACK_L
IDE_PDA<1>
IDE_PDCS3_L
IDE_PDD<4>
IDE_PDD<3>
IDE_PDD<0>
SATA_C_D2R_N
SATA_C_D2R_P
SATA_B_D2R_N
SATA_B_D2R_P
SATA_C_R2D_C_N
SATA_C_R2D_C_P
SATA_B_R2D_C_N
SATA_B_R2D_C_P
SATA_RBIAS_NSATA_RBIAS_P
MAKE_BASE=TRUETP_SATA_B_R2DP
MAKE_BASE=TRUETP_SATA_C_R2DP
TP_SATA_C_R2DNMAKE_BASE=TRUE
MAKE_BASE=TRUETP_SATA_C_D2RP
MAKE_BASE=TRUETP_SATA_B_R2DN
MAKE_BASE=TRUETP_SATA_B_D2RNMAKE_BASE=TRUETP_SATA_B_D2RP
MAKE_BASE=TRUETP_SATA_C_D2RN
MAKE_BASE=TRUESATA_RBIAS
ODD_RST_BUF_L
IDE_PDD<7>
IDE_PDD<2>
P5VODD_EN_L
ODD_RST_5VTOL_L
=PP5V_S0_PCIREQFIX
ODD_RST_BUF_L
IDE_PDCS1_L
=PP5V_S0_ODDPWREN
ODD_PWR_EN
R44601
2
R44021
2
R44031
2
R44101
2
R44201
2C4421
1 2
R44211 2
Q44213
5
4
Q44216
2
1
R44221
2
J4400
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25 26
27
28
29
3
30
31
32
33
34
35
36
37
38
39
4
40
41
42
43
44
45
46
47
48
49
5
50
6
7
8
9
C4422 1
2
U4430
3
2
1
4
5
R44301
2
Q4420
12
56
3
4
8
8
86
8
42
8
Page 43
OUT
VBUS
D-
D+
GND
IN
IN
OUT
OUT
OUT
EN OC*
GNDTHRMLPAD
VDD
THRM_PAD GND
0I0 Y0
SEL
1I1
1I0
0I1
Y1
BI
BI
SYM_VER-1
IN
OUT
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
USB/SMC Debug Mux
SEL=1 Choose USBSEL=0 Choose SMC
If power source is S3, can tie EN to IN.
514S0115
Place L4600 and L4605 across moat
Right USB PortPort Power Switch
FERR-220-OHM-2A
0603
CRITICAL
CRITICAL
100UF6.3V20%
B2POLYCERM
10uF20%
805-1
6.3V6.3V20%
805-1CERM
10uF10V20%
402CERM
0.1UF
0.01uF
CERM402
20%16V
402NONE
NONESHORT
NONE
OMIT
13 24
CRITICAL
F-RT-SM-USB-RGT1UAR2X
RTUSB_ESD
RCLAMP0502BSC-75
CRITICAL
CRITICAL
MSOPTPS2051
SIGNAL_MODEL=USB_MUX
SMC_DEBUG_YES
CRITICALTDFN
PI3USB10
24 86
24 86
0.1UF10V20%
402CERM
SMC_DEBUG_YES
1/16W5%
402MF-LF
10K
CRITICAL
90-OHM-100MA1210-4SM1
7 45 46 47
7 45 46 47
45
66
402
5%
0
MF-LF1/16W
SMC_DEBUG_NO
SMC_DEBUG_NO
0
402
5%
MF-LF1/16W
402NONE
NONESHORT
NONE
OMIT
402NONE
NONESHORT
NONE
OMIT
402NONE
NONESHORT
NONE
OMIT
051-7261
External USB ConnectorSYNC_DATE=12/04/2006SYNC_MASTER=M75_MLB
A.0.0
9243
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.5 mm
PP5V_S3_RTUSB_ILIM
=GND_CHASSIS_RTUSB
USB2_RT_N
USB2_EXTA_MUXED_P USB2_RT_P
=USB_EXTA_EN
VOLTAGE=5VMIN_NECK_WIDTH=0.5 mm
PP5V_S3_RTUSB_FMIN_LINE_WIDTH=0.5 mm
USB_DEBUGPRT_EN_L
SMC_RX_LSMC_TX_L
USB2_EXTA_MUXED_N
USB_EXTA_NUSB_EXTA_P
=PP3V42_G3H_SMCUSBMUX
=PP5V_S3_RTUSB
USB_EXTA_OC_L
L4605
1 2
C46961
2
C4695 1
2
C4690 1
2
C46911
2
C4605 1
2
CX4601 1
2
J4600
1
2
3
4
5
6
7
8
D4600
3
12
U4690
4
1
2
3
5
8
7
6
9
U465012
10
11
9
157
6
13
28
3
4
C4650 1
2
R46501
2
L4600
1
2 3
4
R46511 2
R46521 2
CX4600 1
2
CX4603 1
2
CX4602 1
2
9
91
91 91
91
8
8
Page 44
SYM_VER-1
BI
BI
BI
BI
SYM_VER-1
TABLE_5_ITEM
TABLE_5_ITEM
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
SIM Interconnect
WWAN Ground
Camera USB D+
Left Clutch Barrel Interconnect
WWAN USB D+
WWAN Power
Connector shield
Camera Power
Camera GroundCamera GroundCamera USB D-
Camera TwinAx Shield
Keep close to FL4735 to keepreturn current loop small
NC
WWAN GroundWWAN Ground
NC
WWAN PowerWWAN TwinAx Shield 2
WWAN Ground
NCWWAN_SIM_VCC
WWAN_SIM_RESETWWAN_SIM_DATA
WWAN Power
WWAN USB D-
514S0172
Keep close to FL4745 to keepreturn current loop small
514S0171
WWAN_SIM_CLOCK
WWAN Power
Camera Power
50V
402X7R
10%0.01UF
0603
OMIT
FERR-220-OHM-2A
CRITICAL
20%
CERM
0.001uF
NO STUFF
402
50V
FERR-220-OHM-2A
OMITCRITICAL
0603
CRITICAL
FERR-220-OHM-2A
0603
F-RT-SM20347-125E-12
CRITICAL
1210-4SM190-OHM-100MA
CRITICAL
24 86
24 86
50V10%0.01UF
402X7R
0603
CRITICAL
FERR-220-OHM-2A
50V20%
402CERM
0.001uF
NOSTUFF
24 86
SIM_CONNCRITICAL
20347-110E-12F-RT-SM
OMIT
FERR-120-OHM-1.5A
CRITICAL
0402
24 86
5%1/10W
603
0
MF-LF
603
1/10W
0
5%
MF-LF
603
1/10W
0
5%
MF-LF
1210-4SM1
CRITICAL
90-OHM-100MA
SYNC_DATE=12/21/2006SYNC_MASTER=M75_MLB
051-7261 A.0.0
9244
Left Clutch Barrel Interconnect
RES,MF,1/16W,0OHM,5,0402,SM,LF1 L4764116S0004 CRITICAL
L4731,L4741RES,MF,1/10W,0OHM,5,0603,SM,LF2113S0022 CRITICAL
WWAN_SIM_RESET
WWAN_SIM_CLOCK
MIN_LINE_WIDTH=0.25 mmPPVCC_WWAN_SIM
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUEUSB_WWAN_P
PP5V_S3_WWAN_FMIN_NECK_WIDTH=0.2 mmVOLTAGE=5V
MIN_LINE_WIDTH=0.25 mm
WWAN_SIM_DATA
USB_CAMERA_F_P
=PP5V_S3_CAMERA
USB_EXTD_P
MAKE_BASE=TRUEUSB_WWAN_N USB_EXTD_N
WWAN_SIM_DATA
WWAN_SIM_RESET
USB_CAMERA_F_N
WWAN_SIM_CLOCK
PP5V_S3_CAMERA_FMIN_LINE_WIDTH=0.25 mm
VOLTAGE=5VMIN_NECK_WIDTH=0.2 mm
USB_CAMERA_P
USB_CAMERA_N
PPVCC_WWAN_SIM
USB_WWAN_F_PUSB_WWAN_F_N
=GND_CHASSIS_LEFTCLUTCH
=PP5V_S3_WWAN
=GND_CHASSIS_LEFTCLUTCH
C47301
2
FL4735
1
2 3
4
L4731
1 2
C4731 1
2
L4741
1 2
L4730
1 2
J4731
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
31
32
4
5
6
7
8
9
FL4745
1
2 3
4
C47401
2
L4740
1 2
C4741 1
2
J4732
1
10
11
12
13
14
2
3
4
5
6
7
8
9
L4764
1 2
R47421 2
R47401 2
R47411 2
80
80
91
91
91
91
91
91
91
91
44
44
44
44
44
7
44
7
8
44
44
7
44
7
44
7
7
9
8
9
Page 45
IN
IN
IN
OUT
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
OUT
P16
P51
P50
P42/SDA1
P97/IRQ15*/SDA0
P95/IRQ14*
P94/IRQ13*
P93/IRQ12*
P92/IRQ0*
P91/IRQ1*
P86/IRQ5*/SCK1/SCL1
P83/LPCPD*
P82/CLKRUN*
P80/PME*
P35/LRESET*
P34/LFRAME*
P10
P12
P13
P14
P15
P17
P31/LAD1
P30/LAD0
P32/LAD2
P33/LAD3
P36/LCLK
P37/SERIRQ
P44/TMO1
P77/AN7
P76/AN6
P81/GA20
P96/EXCL
P11
P47/PWX1/PWM1
P45
P46/PWX0/PWM0
P40/TMIO
P43/TMI1/EXSCK1
P27
P26
P25
P24
P23
P22
P21
P20
P41/TMO0
P52/SCL0
P60/KIN0*
P61/KIN1*
P62/KIN2*
P63/KIN3*
P64/KIN4*
P65/KIN5*
P66/IRQ6*/KIN6*
P67/IRQ7*/KIN7*
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P84/IRQ3*/TXD1
P85/IRQ4*/RXD1
P90/IRQ2*
(1 OF 4)
PA2/KIN10*/PS2AC
PA3/KIN11*/PS2AD
PA5/KIN13*/PS2BD
PA4/KIN12*/PS2BC
PB2
PB3
PB4
PE0
PG6/EXIRQ14*/EXSDAB
PG5/EXIRQ13*/EXSCLA
PH1/EXIRQ7*
PH0/EXIRQ6*
PG7/EXIRQ15*/EXSCLB
PG4/EXIRQ12*/EXSDAA
PH3/EXEXCL
PH2/FWE
PB5
PF4/PWM4
PF2/IRQ10*/TMOY
PG2/EXIRQ10*/SDA2
PG0/EXIRQ8*/TMIX
PF7/PWM7
PC3/TIOCD0/TCLKB/WUE11*
PH5
PB7
PB6
PH4
PF5/PWM5
PF6/PWM6
PG1/EXIRQ9*/TMIY
PA6/KIN14*/PS2CC
PA7/KIN15*/PS2CD
PD0/AN8
PD1/AN9
PD2/AN10
PD3/AN11
PD4/AN12
PD5/AN13
PD6/AN14
PD7/AN15
PF0/IRQ8*/PWM2
PF1/IRQ9*/PWM3
PB0/LSMI*
PB1/LSCI
PC0/TIOCA0/WUE8*
PC1/TIOCB0/WUE9*
PC2/TIOCC0/TCLKA/WUE10*
PC4/TIOCA1/WUE12*
PC5/TIOCB1/TCLKC/WUE13*
PC6/TIOCA2/WUE14*
PC7/TIOCB2/TCLKD/WUE15*
PG3/EXIRQ11*/SCL2
PF3/IRQ11*/TMOX
PA1/KIN9*/PA2DD
PA0/KIN8*/PA2DC
PE1*/ETCK
PE2*/ETDI
PE3*/ETDO
PE4*/ETMS
(2 OF 4)
VCL
AVREF
VCC
VCC
VCC
AVCC
XTAL
EXTAL
AVCC
VCC
MD1
MD2
NMI
RES*
ETRST*
AVREF
AVSSVSS
(3 OF 4)
NC22
NC21
NC20
NC19
NC18
NC17
NC16
NC15
NC14
NC13
NC12
NC9
NC6
NC11
NC10
NC8
NC7
NC5
NC4
NC3
NC2
NC1
NC0
(4 OF 4)
OUT
OUT
BI
IN
IN
OUT
BI
BI
OUT
OUT
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
ININ
OUT
OUT
BI
BI
OUT
IN
OUT
OUT
OUT
IN
BI
BI
BI
BI
IN
IN
IN
OUT
BI
IN
IN
IN
IN
BI
BI
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(OC)
(DEBUG_SW_1)
If SMS interrupt is not used, pull up to SMC rail.NOTE: SMS Interrupt can be active high or low, rename net accordingly.
NCNCNCNCNC
NCNC
NCNCNC
NCNC NC
NC
NCNCNC
NCNC
NCNCNCNC
(DEBUG_SW_3)
those designated as inputs require pull-ups.
NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating,
(OC)
(OC)
(OC)
(OC)
(OC)(OC)
(OC)
(OC)
(DEBUG_SW_2)
(OC)
(OC)(OC)(OC)(OC)(OC)(OC)
22UF20%
6.3VCERM-X5R
805-3
7 25 46 47
7 46 47
7 46 80
6.3V
402
10%
PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
0.47UF
CERM-X5R
20%
402
0.1UF10VCERM
20%
402
0.1UF10V
CERM
PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15
402
4.7
1/16W5%
MF-LF
PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15
20%
402
0.1UF10VCERM
SM
25
7 59
20%
402
0.1UF10VCERM
7 25
46
28 46 66
38
20%
402
0.1UF10VCERM
49
49
49
49
49
49
49
49
7 46 57
34 46 57 67
7 43 45 46 47
7 43 45 46 47
36 40 46 57
66
BGASMC_H8S2116
OMIT
OMIT
BGASMC_H8S2116
BGASMC_H8S2116
OMIT
BGASMC_H8S2116
OMIT
46 67
46 67
48
402
10K
MF-LF
5%1/16W
7 47
7 47
MF-LF402
10K5%1/16W
402
1/16W5%
MF-LF
10K
402
NO STUFF
0
MF-LF
5%1/16W
402
10K
MF-LF
5%1/16W
43
34 46
16 32
25
7 49
42
34 46
34
25
46
52
52
46
46
46
46
52
52
55
55
49
55
54
54
49
7 46 47
46
7 46 47
7 46 47
7 46 47
46 80
67
46
67
46
48
48
48
48
48
48
46
46
7 34 54
55
49
7 43 45 46 47
7 43 45 46 47
46
9 46
46
46
7 25 47
16 31
7 25 28
7 47
13 25
7 25 47
7 25
46
7 23 47
7 23 47
7 23 47
7 23 47
7 23 47
7 28
30 88
54
48
7 25 36 40 66
7 25 66
7 25 46
46
48
48
46
SYNC_DATE=12/21/2006SYNC_MASTER=T9_NOME
SMC
45 92
A.0.0051-7261
PM_LAN_ENABLE
SMC_P22
SMC_PF3
PM_SYSRST_L
SMC_BATT_ISET
SMC_SYS_VSET
SMC_FAN_1_TACHSMC_FAN_0_TACHSMC_FAN_3_CTLSMC_FAN_2_CTL
SMC_GFX_OVERTEMP_LSMC_EXCARD_OC_L
ISENSE_CAL_ENSMC_ODD_DETECTSMC_RUNTIME_SCI_L
SMC_EXCARD_CPSMC_EXCARD_PWR_EN
SMC_PB0
SYS_ONEWIREPM_BATLOW_L
SMS_ONOFF_L
SMC_FWEALS_GAIN
SMC_THRMTRIP
SMB_B_S0_CLK
SMC_PROCHOT
SMB_B_S0_DATA
SMB_A_S3_DATA
SMB_BSA_DATA
SMC_TDI
SMC_CASE_OPEN
SMB_0_S0_DATASMC_SUS_CLK
PM_S4_STATE_L
SMC_BS_ALRT_LSMC_BC_ACOK
SMC_CPU_VSENSESMC_CPU_ISENSE
SMC_PM_G2_EN
SMC_EXTALSMC_XTAL
SMC_RESET_L
GND_SMC_AVSS
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM
VOLTAGE=3.3V
PP3V3_S5_SMC_AVCC
SMC_MD1
=PP3V3_S5_SMC
SMC_PA1SMC_PA0
PM_EXTTS_L<0>
SMC_VCL
SMC_NMI
SMC_TRST_L
SMC_KBC_MDE
SMC_P23
SMC_P26SMC_P27
RSMRST_PWRGD
SMC_RSTGATE_LALL_SYS_PWRGD
SMC_BATT_TRICKLE_EN_LSMC_BATT_CHG_EN
LPC_AD<0>LPC_AD<1>LPC_AD<2>LPC_AD<3>LPC_FRAME_L
PCI_CLK33M_SMC
SMB_MGMT_DATA
SMC_SYS_KBDLED
SMC_TX_LSMC_RX_LSMB_0_S0_CLK
INT_SERIRQ
SMC_P44
SMC_P46
USB_DEBUGPRT_EN_L
PM_EXTTS_L<1>
SMC_FAN_0_CTL
SMC_FAN_3_TACH
SMS_X_AXIS
SMC_NB_CORE_ISENSE
ALS_LEFTALS_RIGHT
PM_RSMRST_L
SMC_P21SMC_P20
IMVP_VR_ON
SMC_FAN_1_CTL
SMC_ANALOG_IDSMS_Z_AXISSMS_Y_AXIS
SMC_FAN_2_TACH
SMB_A_S3_CLK
=SMC_SMS_INT
SMC_PROCHOT_3_3_LPM_PWRBTN_L
PM_SLP_S3_L
SMC_SYS_ISETSMC_BATT_VSET
SMC_TDOSMC_TMS
SMB_BSA_CLK
SMC_LIDSMC_PF1SMC_PF0
SMC_TCK
PP3V3_S5_AVREF_SMC
SMC_GPU_VSENSE
PM_CLKRUN_L
SMC_ONOFF_L
PM_SLP_S5_L
SMC_NB_1V25_ISENSESMC_BATT_ISENSESMC_PBUS_VSENSESMC_DCIN_ISENSE
SMC_P81SMC_WAKE_SCI_L
SMC_SYS_LED
SMC_P43
SMC_P45
SMC_GFX_THROTTLE_L
PM_LAN_PWRGD
SMC_P67
SMC_P14
SMC_GPU_ISENSE
SMC_ADAPTER_ENSMC_P62SMC_P63SMC_P64
SMC_PH4
SMC_PG0
SMC_NB_1V8_ISENSE
SMB_MGMT_CLKSMC_RX_L
PM_SUS_STAT_LSMC_TX_L
SMC_LRESET_L
C4902 1
2
C49031
2
C49041
2
C49051
2
C49061
2
C4907 1
2C4920 1
2
R49991 2
XW4900
1
2
U4900B12
C13
A15
B14
B15
C14
D12
C15
D13
D14
D15
E12
E14
E15
E13
F14
D9
C9
A9
B9
D8
C8
A8
D7
A5
B5
D5
C3
B1
C2
D3
C1
G1
G4
F2
L13
L14
L15
K12
K13
K14
J12
J13
N12
R13
P13
R14
P14
R15
N13
P15
C7
A7
B7
D6
C6
A6
B6
K4
J2
J1
J3
J4
H2
H1
G2
U4900R3
P3
R2
N3
R1
N2
M4
N1
B10
A10
D10
A11
B11
C11
A12
D11
G14
G15
G13
G12
H14
H15
H13
H12
M11
P11
R11
N11
P10
R10
N10
M10
M3
M2
M1
L4
L2
M7
P6
R6
N6
M6
R5
P5
N5
P9
R9
N9
P8
R8
M8
P7
R7
E1
F3
K2
C4
D4
B3
U4900
N14
N15
M14
M15
P12
R12
L1
B2
E2
K1
F4
E3
P2
P1
J15
A1
F1
D1
P4
R4
F12
F13
B13
A13
A4
B4
D2
A2
U4900
G3
H3
K15
J14
F15
A14
C12
C10
C5
A3
B8
E4
K3
H4
M9
N8
L3
N4
M5
N7
M12
M13
L12
R49091
2
R49011
2
R49021
2
R49031
2
R49981
2
54 49
46
46
46 46
46
46
46
8
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
Page 46
G
D
S
IN OUT
GND
NCCD
GND
OUT
VDD
OUT
IN
OUT
OUT
IN OUT
IN
BI
OUT
ING
D
S
G
D
S
OUT IN
OUT
OUT
IN
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
SMC AVREF Supply
LAN PWRGD Circuit
SMC FSB to 3.3V Level Shifting
TO CPU
TO SMC
NC
TPS51120 PGOOD threshold 87-93% (4.35 - 4.65V)
TPS51120 PGOOD threshold 87-93% (2.87 - 3.07V)
System (Sleep) LED Circuit
Debug Power "Button"
Reports when 5V S5 and 3.3V S5 are in regulation
S5 Rail PWRGD Circuit
SMC Crystal Circuit
SMC Reset "Button" / Brownout Detect
10V
0.1uF
402
20%
CERM
SOT-3632N7002DW-X-F
10%6.3VCERM-X5R402
0.47UF
0.01UF10%16V
402CERM
6.3V20%
X5R603
10uF
CRITICAL
REF3133SOT23-3
MF-LF402
5%1/16W
0
10K1/16W5% MF-LF 402100K
MF-LF5% 1/16W 40210K5% MF-LF1/16W 402
40210K
1/16W5% MF-LF
4021/16W MF-LF5%100K
ONEWIRE_PU
4021/16W5% MF-LF2.0K
402100K
1/16W5% MF-LF
40210K
1/16W5% MF-LF
402MF-LF5% 1/16W10K
402MF-LF1/16W5%10K
402MF-LF5% 1/16W10K
402MF-LF5% 1/16W10K
402MF-LF5% 1/16W10K10K
4025% MF-LF1/16W10K402MF-LF5% 1/16W
1/16W MF-LF 402470K
5%
MF-LF 4025% 1/16W10K
CRITICAL
5X3.2-SM20.00MHZ
RN5VD30A-FSOT23-5
CRITICAL
1/16W5% MF-LF 402100K
1/16W MF-LF 402100K
5%
7 45 47
40210K
1/16W5% MF-LF
10K1/16W5% MF-LF 402
45
10 16 23 83
7 80
5%
OMIT
1/10W
0
MF-LF603
OMIT
1/10W
0
MF-LF
5%
603
100K1/16W5%
402MF-LF
61 45
CERM50V10%0.0022UF
402
61
SOT-363-LFMMDT3904XF
3.3K
402
5%1/16WMF-LF
SOT-363-LFMMDT3904XF
402MF-LF
5%1/16W
3.3K
5%1/16WMF-LF402
470
10 59 83
45
45
2N7002DW-X-FSOT-363
402MF-LF5% 1/16W100K
4021/16W MF-LF5%100K 4021/16W5% MF-LF100K
2N7002SOT23-LF
10K1/16W5% MF-LF 402
10K1/16W5% MF-LF 402
MF-LF1/16W
100K
NO STUFF
402
5%
0
402
5%
MF-LF1/16W
45 28 45 66
9
402
1K
MF-LF
5%1/16W
7 45 46 80
SOT23-LF2N3906
1/16W
100
MF-LF
5%
402
2.37K1/16WMF-LF
402
1%
45
MF-LF402
1/16W1%
9.09K
402
50V
15pF
CERM
5%
50VCERM402
15pF
5%
402CERM16V
0.01UF10%
SMC SupportSYNC_MASTER=M75_MLB
46 92
A.0.0051-7261
SYNC_DATE=04/25/2007
353S1278353S1381 Intersil ISL60002-33ALL
GND_SMC_AVSSMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0V
=PP3V3_S5_S5PWRGD
SMC_BATT_CHG_EN
MAKE_BASE=TRUESMC_ENRGYSTR_LDO_EN
TP_SMC_PF1MAKE_BASE=TRUE
TP_SMC_PF0MAKE_BASE=TRUE
MAKE_BASE=TRUETP_SMC_P81
SMC_P63MAKE_BASE=TRUETP_SMC_P63
SMC_P64 TP_SMC_P64MAKE_BASE=TRUE
SMC_P46 TP_SMC_P46MAKE_BASE=TRUE
SMC_P62 TP_SMC_P62MAKE_BASE=TRUE
PM_LAN_PWRGD
SMC_SUS_CLK
SMC_ONOFF_L
ALL_SYS_PWRGD
=PPVIN_S5_SMCVREF
=PP3V3_S5_SMC
SMC_PROCHOT_3_3_L
=PP3V3_S0_SMC
SMC_P14 TP_SMC_P14MAKE_BASE=TRUE
MAKE_BASE=TRUETP_SMC_P20SMC_P20
SMC_SYS_VSET TP_SMC_SYS_VSETMAKE_BASE=TRUE
SMC_BATT_VSETMAKE_BASE=TRUETP_SMC_BATT_VSET
SMC_PF3
SMC_TCKSMC_TDI
SMC_TMSSMC_TDO
SMC_BS_ALRT_LSYS_ONEWIRE
SMC_RX_L
SMC_LIDSMC_FWESMC_TX_L
SMC_ONOFF_L
SMC_PB0SMC_PA1SMC_PA0
SMC_CASE_OPEN
SYS_LED_L
SMC_SYS_LED
EXCARD_OC_L
MAKE_BASE=TRUERSMRST_PWRGD
=P5VS5_PGOOD
=P3V3S5_PGOOD
PM_SLP_S5_L
SMC_BC_ACOKSMC_EXCARD_CPPM_SUS_STAT_L
VOLTAGE=3.3V
PP3V3_S5_AVREF_SMCMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm
SMC_RESET_L
SYS_LED_L_VDIV
SYS_LED_ANODE
=PP5V_S3_SYSLED
SYS_LED_ILIM
SMC_XTAL
TP_SMC_FAN_2_CTLMAKE_BASE=TRUE
SMC_FAN_2_CTL
TP_SMC_FAN_2_TACHMAKE_BASE=TRUE
SMC_FAN_2_TACH
TP_SMC_FAN_3_TACHMAKE_BASE=TRUE
SMC_FAN_3_TACH
TP_SMC_FAN_3_CTLMAKE_BASE=TRUE
SMC_FAN_3_CTL
TP_SMC_GFX_OVERTEMP_LMAKE_BASE=TRUE
SMC_GFX_OVERTEMP_L
TP_SMC_GFX_THROTTLE_LMAKE_BASE=TRUE
SMC_GFX_THROTTLE_L
TP_SMC_P21MAKE_BASE=TRUE
SMC_P21
MAKE_BASE=TRUETP_SMC_P22SMC_P22
TP_SMC_P23MAKE_BASE=TRUE
SMC_P23
TP_SMC_P26MAKE_BASE=TRUE
SMC_P26
TP_SMC_P27MAKE_BASE=TRUE
SMC_P27
MAKE_BASE=TRUETP_SMC_P43SMC_P43
MAKE_BASE=TRUETP_SMC_P44SMC_P44
=PP1V05_S0_SMC_LS
CPU_PROCHOT_BUF
CPU_PROCHOT_L CPU_PROCHOT_L_R
SMC_PROCHOT
PM_THRMTRIP_L
SMC_THRMTRIP
SMC_PG0
SMC_P67=PP3V3_S0_SMC
SMC_EXTAL
SMC_MANUAL_RST_L
SMC_ADAPTER_EN
SMC_BATT_TRICKLE_EN_L
SMC_PH4
=PP3V3_S5_SMC
SMC_EXCARD_OC_L
SMC_PF1
SMC_PF0
SMC_P81
MAKE_BASE=TRUESUS_CLK_SB
SMC_P45
C5000 1
2
R50001
2
C5001 1
2
Q50301
3
2
R50301
2
R50311
2
R50321
2
C50101 2
C50111 2
Q50596
2
1
C50201
2
C50261
2
C5025 1
2
VR5020
3
1 2
R50951 2
R5070 1 2
R5071 1 2
R5072 1 2
R5073 1 2
R5074 1 2
R5075 1 2
R5076 1 2
R5077 1 2
R5078 1 2
R5079 1 2
R5080 1 2
R5083 1 2
R5084 1 2
R5085 1 2
R5086 1 2
R5087 1 2
R5088 1 2
Y5010 1
2
U5000
5
3
4
1
2
R5089 1 2
R5090 1 2
R5082 1 2
R5081 1 2
R50011
2
R50151
2
R50451
2
C50451
2
Q50605
3
4
R50611
2Q5060
2
6
1R50621 2
R50601
2
Q50593
5
4
R5091 1 2
R5093 1 2
R5092 1 2
Q50323
1
2
R5096 1 2
R5094 1 2
R50971
2 R50981 2
47
47
80
67
47
57
54
46
47
47
47
47
57
45
45
46
45
57
45
45
46
49
67
45 46
45
45
45
45
45
45
43
80
43
45
34
25
45
45
25
46
40
67
45
45
8
45
45
45
45
45
45
8
8 8
45
45
45
45
45
7
7
7
7
7
34
7
45
45
7
7
45
45
45
45
24
7
34
34
7
45
8
45
45
45
45
45
45
45
45
45
45
45
45
45
8
45
45 8
45
36
45
45
8
45
45
45
45
25
45
Page 47
BI
BI
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
BI
BI
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
OUT
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
FWH_INIT_L GenerationLPC+ Connector
516S0394
7 23 45
7 25 45
7 30 88
7 25 45 46
7 25 45
7 24
7 45 46
7 45
7 45
7 28
7 23 45
7 23 45
7 23 45
7 45 46
7 45 46
7 45
7 25
MMDT3904XFSOT-363-LF
LPCPLUS
LPCPLUS
PLACEMENT_NOTE=Place Q5190 close to R5190
SOT-363-LFMMDT3904XF
330
LPCPLUS
MF-LF1/16W5%
402
LPCPLUS
5%1/16WMF-LF402
1.3K
LPCPLUS
330
402MF-LF
5%1/16W
PLACEMENT_NOTE=Place R5190 to minimize CPU_INIT_L stub
10 23 83
7 43 45 46
7 43 45 46
7 45 46
7 45 46
CRITICAL
LPCPLUS
M-ST-SMQT500306-L021-9F
7 23 45
SYNC_DATE=12/04/2006
LPC+ Debug Connector
051-7261
47 92
A.0.0
SYNC_MASTER=M75_MLB
=PP3V3_S5_LPCPLUS=PP5V_S0_LPCPLUS
LPC_AD<0>LPC_AD<1>
LPC_FRAME_LPM_CLKRUN_LBOOT_LPC_SPI_LSMC_TMS
CPU_INIT_LS3V3
FWH_INIT_LPCI_CLK33M_LPCPLUS
LPC_AD<2>LPC_AD<3>
INT_SERIRQPM_SUS_STAT_LSMC_TDISMC_TCKSMC_RESET_LSMC_NMISMC_RX_L
LINDACARD_GPIO
DEBUG_RESET_LSMC_TRST_LSMC_TDOSMC_MD1SMC_TX_L
CPU_INIT_L
=PP3V3_S0_LPCPLUS
CPU_INIT_R_L
Q5190 5
3
4
Q5190 2
6
1
R51921
2
R51911
2
R51901 2
J5100
1
10
11 12
13 14
15 16
17 18
19
2
20
21 22
23 24
25 26
27 28
29
3
30
31 32
33 34
4
5 6
7 8
9
8
8
7
7
7
8
Page 48
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
SMC "0" SMBus Connections
SMC "Battery A" SMBus Connections
(Write: 0x16 Read: 0x17)
The bus formerly known as "Battery B"
(Write: 0x30 Read: 0x31)
SMCU4900
(MASTER)
SMC "B" SMBus Connections
(Write: 0x98 Read: 0x99)
CPU TempEMC1043-5: U5570
(Write: 0x92 Read: 0x93)
Battery ChargerTMP106:U5750
U4900(MASTER)
GPU Temp (Int)G84M: U8000
(Write: 0x9E Read: 0x9F)
(Write: 0x92 Read: 0x93)Left ALS - TMP106
(Write: 0x90 Read: 0x91)
(See Table)
M35B - TMP106
Left I/O SMBus Connections:
(Write: 0x9E Read: 0x9F)TMP275
SMC "A" SMBus ConnectionsNOTE: SMC RMT bus remains powered and may be active in S3 state
Top-CaseJ9600
Left I/O Board
(Write: 0x98 Read: 0x99)EMC1045-5: U5500
Remote Temps
U4900(Write: 0x98 Read: 0x99)
SMCGPU Temp (Ext)
SMC "Management" SMBus Connections
J3400
J6950
ICH8-M SMBus Connections
SO-DIMM "B"
SMSU5900
Clock Chip
ICH8-M ME SMBus Connections
(Write: 0xA4 Read: 0xA5)
CY28545-5: U2900
J3200
J3100
(MASTER)
SMC
SMC
U4900
SO-DIMM "A"
U4900(MASTER)
TMP401: U5550
Battery
(MASTER)U2300
ICH8-M
J3400Left I/O(See Table)
ICH8-M(MASTER?)U2300
ExpressCard Slot
(Write: 0xD2 Read: 0xD3)
(Write: 0xA0 Read: 0xA1)
SMC
Left I/O SMBus Connections:
(Address determined by ARP)
(MASTER)
1/16W5%
MF-LF402
4.7K5%1/16WMF-LF402
4.7K
4.7K
MF-LF
5%
402
1/16W
4.7K
402MF-LF1/16W5%
4.7K5%1/16W
402MF-LFMF-LF
5%
402
4.7K1/16W
3.3K1/16W
402MF-LF
5%3.3K
402
1/16WMF-LF
5%
5%
402
4.7K1/16WMF-LF
402
5%1/16W
4.7K
MF-LF402
1/16W
4.7K5%
MF-LF
4.7K
MF-LF
5%
402
1/16W
10K5%1/16WMF-LF402
10K5%
402
1/16WMF-LF
051-7261
9248
A.0.0
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
SMBus Connections
SMBUS_SB_SDAMAKE_BASE=TRUE
SMBUS_SB_SCLMAKE_BASE=TRUE
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
=I2C_SODIMMB_SDA
=SMBUS_LIO_SB_SCL
=SMBUS_CK505_SCL
MAKE_BASE=TRUESMBUS_SMC_MGMT_SDA
=PP3V3_S3_SMBUS_SMC_A_S3
=I2C_TOPCASE_SDA
MAKE_BASE=TRUESMBUS_SMC_BSA_SDA
MAKE_BASE=TRUESMBUS_SMC_BSA_SCL
=SMBUS_LIO_SB_SDA
SMB_ME_CLK
SMB_ME_DATAMAKE_BASE=TRUESMBUS_SB_ME_SDA
MAKE_BASE=TRUESMBUS_SB_ME_SCL
=PP3V3_S5_SMBUS_SB_ME
=PP3V3_S3_SMBUS_SMC_MGMT
=I2C_SMS_SCL
=I2C_SMS_SDA
=SMBUS_BATT_SDA
SMB_MGMT_DATA
SMB_MGMT_CLK
SMB_BSA_DATA
SMB_BSA_CLK
SMB_CLK
SMB_DATA =SMBUS_CK505_SDA
=I2C_SODIMMB_SCL
=PP3V3_S0_SMBUS_SB
SMB_0_S0_CLK =I2C_TOPCASE_SCL
SMB_0_S0_DATA
=PP3V42_G3H_SMBUS_SMC_BSA
MAKE_BASE=TRUESMBUS_SMC_0_S0_SCL
=SMBUS_BATT_SCL
=SMBUS_LIO_SMC_SDA
=SMBUS_LIO_SMC_SCL
=SMBUS_GPUTHMSNS_SDA
=SMBUS_GPUTHMSNS_SCL
SMB_A_S3_DATA
SMB_A_S3_CLK
=PP3V3_GPU_SMBUS_SMC_0_S0
=SMBUS_REMTHMSNS_SCL
=SMBUS_REMTHMSNS_SDA
MAKE_BASE=TRUESMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUESMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUESMBUS_SMC_MGMT_SCL
MAKE_BASE=TRUESMBUS_SMC_0_S0_SDA
=GPU_I2CS_SDA
=GPU_I2CS_SCL
=PP3V3_S0_SMBUS_SMC_B_S0
SMBUS_SMC_B_S0_SCLMAKE_BASE=TRUE
MAKE_BASE=TRUESMBUS_SMC_B_S0_SDA
=SMBUS_TMPSNSR_SCL
=SMBUS_TMPSNSR_SDA
=I2C_CPUTHMSNS_SCL
=I2C_CPUTHMSNS_SDA
SMB_B_S0_CLK
SMB_B_S0_DATA
R52001
2
R52011
2
R52801
2
R52811
2
R52911
2
R52901
2
R52611
2
R52601
2
R52711
2
R52701
2
R52511
2
R52501
2
R52311
2
R52301
2
86
86
57
86
86
57
31
31
32
34
29
88
8
80
88
88
34
25
25
8
8
55
55
7
45
45
45
45
25
25 29
32
8
45 80
45
8
88
7
34
34
51
51
45
45
8
51
51
88
88
88
88
75
75
8
88
88
53
53
51
51
45
45
Page 49
IN
OUT
N-CHN
S
D
G
P-CHN
G
DS
D
S
G
IN
D
S
G
ININ
IN
OUT
OUT
OUTIN OUTIN
OUTIN IN OUT
OUTOUT
OUTIN
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NB GFX Current Sense Filter
Place short near U1000 center
Place short near U8000 center
Place RC close to SMC
CPU Voltage Sense / Filter
GPU Voltage Sense / Filter
NB Core Current Sense Filter
Place RC close to SMC
GPU Current Sense Filter
Place RC close to SMC
Current Sense Calibration CircuitSwitches in fixed load on power supplies to calibrate current sense circuits
Place RC close to SMC
CPU Current Sense Filter
Place RC close to SMC
DCIN Current Sense Filter
Place RC close to SMC
Place RC close to SMC
Battery (PBUS) Current Sense Filter
Place RC close to SMC
Rthevanin = 4573 ohms
Place RC close to SMC
PBUS Voltage Sense & Filter
NB 1.8V Current Sense Filter
Place RC close to SMC Place RC close to SMC
S0/GPU 1.25V Current Sense Filter
Enables PBUS VSense divider when high.
7 45
100K5%
1/16WMF-LF
402
100K
402MF-LF1/16W
5%
45
402MF-LF1/16W
1%27.4K
20%
X5R402
0.22UF6.3V
1%1/16WMF-LF
402
5.49K
SC70-6FDG6332C_NL
SC70-6FDG6332C_NL
FDM6296
CRITICAL
MICROFET3X3
ISL9504B
1/16W1%
MF-LF402
4.53K59 66
1206MF-LF1/4W
1%1.00
MICROFET3X3FDM6296
CRITICAL
50 50
100K
402MF-LF1/16W
5%
SN74AHCT1G125DCKRE4
SC70-51/16WMF-LF
5%
402
1K
0.1UF
20%10VCERM402
1%
MF-LF402
4.53K
1/16W
50
6.3V
0.22UF
402X5R
20%
45
45
0.22UF20%6.3VX5R402
1/16W1%
MF-LF402
4.53K
45
1/16W
4.53K
402MF-LF
1%
20%
X5R402
0.22UF6.3V
50 45
402
20%
X5R6.3V
0.22UF402
1%1/16WMF-LF
4.53K76
45
402
6.3V
0.22UF
X5R
20%
1/16W
4.53K
402MF-LF
1%
53 53 4.53K
402MF-LF1/16W1%
6.3V
0.22UF
402X5R
20%
45
45
6.3V
0.22UF
402X5R
20%
4.53K
402MF-LF
1%1/16W
45
0.22UF20%6.3V
402X5R
402MF-LF
1%1/16W
4.53K
45
0.22UF
402
20%
X5R6.3V
1/16W1%
MF-LF
4.53K
402
ISL9504A
50
SM
45
402
1%
4.53K
MF-LF1/16W
402X5R6.3V20%0.22UF
SM
1206MF-LF1/4W
1%1.00
49 92
A.0.0051-7261
Current & Voltage SensingSYNC_MASTER=M75_MLB SYNC_DATE=03/19/2007
ISENSE_CAL_EN ISENSE_CAL_EN_LS5V_R
=PP5V_S0_ISENSECAL
IMVP6_IMON
SMC_CPU_ISENSECPUVCORE_IOUT
PBUSVSENS_EN_L
=PBUSVSENS_EN
PBUSVSENS_EN_DIV SMC_PBUS_VSENSE
SMC_NB_1V25_ISENSEP1V25_S0GPU_IOUT
GND_SMC_AVSS
MIN_LINE_WIDTH=0.20 mmMIN_NECK_WIDTH=0.20 mmVOLTAGE=18.5V
PPBUS_G3H_VSENSE
GND_SMC_AVSS
PPBUS_G3H
GPUVSENSE_IN SMC_GPU_VSENSE
CPUVSENSE_IN SMC_CPU_VSENSE
=PPVCORE_GPU_REG
GND_SMC_AVSS
LIO_BATT_ISENSE
GND_SMC_AVSS
GND_SMC_AVSS
SMC_BATT_ISENSE
CPUVCORE_ISENSE_CALMIN_LINE_WIDTH=0.50 mmMIN_NECK_WIDTH=0.20 mm
GND_SMC_AVSSGND_SMC_AVSS
GND_SMC_AVSS
SMC_DCIN_ISENSE
SMC_NB_1V8_ISENSE
LIO_DCIN_ISENSE
SMC_GPU_ISENSE
GND_SMC_AVSS
=PPVCORE_S0_CPU_REG
GPUVCORE_IOUT
=PPVCORE_S0_CPU
P1V8_S3_IOUT
GND_SMC_AVSS
SMC_NB_CORE_ISENSE
GND_SMC_AVSS
SMC_NBGFXCORE_ISENSE
NBCORE_IOUT
NBGFXCORE_IOUT
SMC_ANALOG_IDSMC_NBGFXCORE_ISENSEMAKE_BASE=TRUE
=PPVCORE_GPU_REG
MIN_LINE_WIDTH=0.50 mmMIN_NECK_WIDTH=0.20 mm
GPUCORE_ISENSE_CAL
ISENSE_CAL_EN_LS5V
C53591
2
R53591 2
R53701 2
C53701
2
C53751
2
R53751 2
C53801
2
R53801 2
R53901 2
C53901
2
C53401
2
R53401 2
C53351
2
R53351 2
C53301
2
R53301 2
XW53591 2
R53091 2
C53091
2
XW53091 2
R53201
2
R53271
2
R53151
2
R53851
2
C53851
2
R53861
2
Q5315
6
2
1
Q5315
3
5
4
Q5320
5
4
1 2 3
R53311 2
R53221
2
Q5322
5
4
1 2 3
R53161
2
U53272
3 1
54
R532812
C53271 2
R53651 2
C53651
2
54
54
76
54
54
54 54 54
54
54
54
54
76
49
49
49
49
49
49 49 49
49
49
59
12
49
49
49
8
46
46
8
46
46
46 46 46
46
46
8
11
46
46
8
7
66
45
45
8
7
45
45
45 45 45
45
45
7
8
45
45
49
49
7
Page 50
OUT
R1-
R1+ R2
V-
V+
+
IN
IN
OUT
R1-
R1+ R2
V-
V+
+
OUT
IN
IN
OUT
R1-
R1+ R2
V-
V+
+
OUT
R1-
R1+ R2
V-
V+
+
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Gain = 165:1
Gain = 100:1
Gain = 100:1
Gain = 100:1
2.0K1%1/16WMF-LF402
SM
SM
SM
SM
SM
SM
402
1%
MF-LF1/16W
10
0.1UF
402X5R16V10%
49
50V10%
402CERM
0.001UF100K
MF-LF1/16W1%
402
MSOPINA326EA-250
CRITICAL2.0K1%1/16W
402MF-LF
60
60
MF-LF
1%1/4W
1206
0.002
CRITICAL
CERM402
10%50V
470PF
1M
MF-LF402
1%1/16W
0.1UF
CERM402
20%10V
MF-LF
1%
402
1/16W
40.2K
NO STUFF
0.1UF
402CERM
20%10V
LMV2011MFSOT23-5
CRITICAL
1M
MF-LF402
1%1/16W
CERM402
10%50V
470PF
MF-LF
1%
40.2K
402
1/16W
0.1UF20%10V
NO STUFF
CERM402
49
10
1/16WMF-LF
1%
402
10%16VX5R402
0.1UF
0.001UF
CERM402
10%50V
CRITICAL
INA326EA-250MSOP
402
100K1%1/16WMF-LF
805-3CERM-X5R6.3V20%22UF
805-3CERM-X5R6.3V20%22UF
2.0K
MF-LF402
1%1/16W
CRITICAL
0.002
1206
1/4W1%
MF-LF
49
59
59
10
1/16WMF-LF
1%
402
49
0.001UF
CERM402
10%50V
CRITICAL
1206
1%
MF-LF1/4W
0.002
10%16VX5R402
0.1UF
165K
MF-LF1/16W1%
402
805-3CERM-X5R6.3V20%22UF
INA326EA-250MSOP
CRITICAL
805-3CERM-X5R6.3V20%22UF
2.0K
MF-LF402
1/16W1%
1/16W
402
1%
10
MF-LF
49
0.001UF50V
CERM402
10%
10%16VX5R402
0.1UF805-3
6.3V20%22UF
CERM-X5R805-3
6.3V20%22UF
CERM-X5R
CRITICAL
INA326EA-250MSOP
100K
402
1%1/16WMF-LF
SYNC_DATE=03/19/2007SYNC_MASTER=M75_MLB
Current Sensing
50 92
A.0.0051-7261
=PP1V8_S3_ISNS=PP1V8_S3_ISNS_R
IMVP6_VO
CPUCOREISNS_N
P1V8ISNS_P
NBCORE_IOUT
=PP3V3_S3_P1V8ISNS
=PPVCORE_S0_NB_R
MIN_LINE_WIDTH=0.25mm
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2mm
PP3V3_S0_NBCOREISNS_VCC
P1V25ISNS_PP1V25ISNS_R1_P
GFXIMVP6_VO
GFXIMVP6_PHASE_VSUM
NBGFXCORE_IOUTNBGFXISNS_R1_N
NBGFXISNS_R2
MIN_NECK_WIDTH=0.2mmVOLTAGE=3.3V
MIN_LINE_WIDTH=0.25mmPP3V3_S0_NBGFXISNS_VCC
NBGFXISNS_R1_P
P1V8_S3_IOUT
=PP3V3_S0_NBCOREISNS
NBCOREISNS_R2
=PPVCORE_S0_NBCOREISNS
NBCOREISNS_N
NBCOREISNS_PNBCOREISNS_R1_P
NBCOREISNS_R1_N
P1V8ISNS_R2
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25mmMIN_NECK_WIDTH=0.2mm
PP3V3_S3_P1V8ISNS_VCC
P1V8ISNS_R1_P
=PP1V25_ENET_ISNS_R =PP1V25_ENET_ISNS
P1V25ISNS_N
=PP3V3_S3_P1V25ISNS
P1V25_S0GPU_IOUT
P1V25ISNS_R2
MIN_LINE_WIDTH=0.25mm
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2mm
PP3V3_S3_P1V25ISNS_VCC
P1V25ISNS_R1_N
IMVP6_DROOP
CPUCOREISNS_P
CPUVCORE_IOUT
=PP3V3_S0_CPUCOREISNS
P1V8ISNS_NP1V8ISNS_R1_N
=PP3V3_S0_NBGFXCOREISNS
C54001 2
R54001 2
C54011
2
R54021 2
C5403 1
2
U5400
3
4
1
5
2
R54041 2
C540512
R54031 2
C5404 1
2
R54201 2
C54201
2
C5422 1
2
U54203
2
6
1
8
5
4
7
R54221
2
C54261
2
C54251
2
R54211
2
R54251 2 R5430
1 2
C5432 1
2
R54351 2
C54301
2
R54321
2
C54361
2
U54303
2
6
1
8
5
4
7
C54351
2
R54311
2
R54401 2
C5442 1
2
C54401
2
C54461
2
C54451
2
U54403
2
6
1
8
5
4
7
R54421
2
R54411
2
XW5425
1
2XW5426
1
2
XW5445
1
2XW5446
1
2
XW5435
1
2XW5436
1
2
R54101 2
C54101
2
C5412 1
2
R54121
2
U54103
2
6
1
8
5
4
7
R54111
2
R54451 2
8 8
91
8
8
91
8 8
91
8 8 8
8
8
Page 51
BI
BI
BI
BI
GND
VDD
SDATA
SCLK
THM*
ALERT*/
D+
D-
THM2*
BI
BI
BI
BI
OUT
IN
VDD
SMDATA
SMCLK
GND
DP1
DN1
DP2
DN2
VDD
SMDATA
SMCLK
GND
DP1
DN1
DP2
DN2
BI
BI
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Placement note:
518S0487
(TC0P)
(Th0H)
Placement note:Place U5550 near GPU
(Th1H)
(TG0P)
CPU T-Diode Thermal Sensor
(Reserved for CPU heatpipe sensor)
NB Thermal Diodes Not Used
(TG0T)
(Th2H)
518S0487
Place on left side of fan cutout
connectors as possibleKeep 2 caps as close toPlacement note:
GPU Die Thermal Sensor
(TC0D)
518S0487
Placement note:
GPU/Heat Pipe & Bottom Case Skin Thermal Sensor
Place near GPU(TG0H)
Keep 2 caps as closeto IC pins as possible
Placement note:
20
20
20
20
10V20%
402CERM
0.1uF
402
1/16W5%
MF-LF
47
5%18PF50VCERM402
NO STUFF
50V
402CERM
18PF5%
NO STUFF
M-RT-SM
CRITICAL
BM02B-ACHKS-GAN-TF-LF-SN-M
BM02B-ACHKS-GAN-TF-LF-SN-M
CRITICAL
M-RT-SM
402
1/16WMF-LF
5%10K
GPU_TMP401GPU_TMP401
1/16W
10K5%
402MF-LF
0.1UF
X5R402
10%16V
GPU_TMP401
50VCERM402
10%0.001UF
GPU_TMP401
402MF-LF1/16W1%
499
GPU_TMP401
499
1%1/16WMF-LF402
GPU_TMP401
CRITICAL
TMP401MSOP
GPU_TMP401
M-RT-SMBM02B-ACHKS-GAN-TF-LF-SN-M
CRITICAL
48
48
48
48
74 91
74
402
0.0022uF
CERM50V10%
MSOPEMC1043-5
CRITICAL
10%50V
CERM
0.0022uF
402
MSOPEMC1043-5
CRITICAL
48
48
10V
0.1uF20%
CERM402
MF-LF
5%1/16W
47
402
0.0022uF10%50V
CERM402
470PF10%50V
CERM402
10 91
10
SYNC_DATE=03/19/2007
Thermal Sensors
51 92
A.0.0051-7261
SYNC_MASTER=M75_MLB
=SMBUS_REMTHMSNS_SDA=SMBUS_REMTHMSNS_SCL
VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmPP3V3_S3_REMTHMSNS_R
HSTHMSNS_D_P
HSTHMSNS_D_N
RSFSTHMSNS_D_N
RSFSTHMSNS_D_P
=GND_CHASSIS_J5590
CPUTHMSNS_D2_N
=PP3V3_S0_GPUTHMSNS
GPU_TDIODE_P
GPUTHMSNS_D_NGPU_TDIODE_N
GPUTHMSNS_D_P
=PP3V3_S0_CPUTHMSNS
GPUTHMSNS_THM_L
GPUTHMSNS_ALERT_L
CPUTHMSNS_D2_P
VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmPP3V3_S0_CPUTHMSNS_R
CPU_THERMD_P
CPU_THERMD_N
=I2C_CPUTHMSNS_SDA=I2C_CPUTHMSNS_SCL
=PP3V3_S3_REMTHMSNS
=SMBUS_GPUTHMSNS_SDA=SMBUS_GPUTHMSNS_SCL
=NB_TDE_SENSE=NB_TDE_FORCE
=NB_TDB_SENSE=NB_TDB_FORCEU5570
2
4
1
3
5
8
7
6 C55701
2
R55701 2
C5590 1
2
C5580 1
2
C55001
2
R55001 2
C55101
2
C55201
2
J5510
3
4
12
J5520
3
4
12
R55521
2
R55511
2
C5550 1
2
C55601
2
R55601 2
R55611 2
U55506
32
5
87
4
1
J5590
3
4
12
C5511 1
2
U5500
2
4
1
3
5
8
7
6
C5521 1
2
91
91
91
7
7
7
7
9
7
8
91
8
7
8
Page 52
G
S D
G
S DIN
OUT OUT
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
518S0369
Left Fan Right Fan
518S0369
1/16W
47K
402
5%
MF-LF
1/16W5%
MF-LF402
47K402
MF-LF
47K5%
1/16W
402
47K
MF-LF1/16W5%
402MF-LF
5%1/16W
100K
2N7002DW-X-FSOT-363
100K5%
MF-LF402
1/16W
SOT-3632N7002DW-X-F
CRITICAL
SM04B-ACHM-RT-SM
CRITICAL
SM04B-ACHM-RT-SM
45
45 45
45
Fan Connectors
A.0.0051-7261
9252
SYNC_MASTER=M75_MLB SYNC_DATE=12/04/2006
=PP5V_S0_FAN_LT
FAN_LT_TACH
FAN_LT_PWM
=PP3V3_S0_FAN_RT
FAN_RT_TACH
=PP5V_S0_FAN_RT
FAN_RT_PWM
=PP3V3_S0_FAN_LT
SMC_FAN_0_TACH
SMC_FAN_0_CTL
SMC_FAN_1_TACH
SMC_FAN_1_CTL
R56501
2R56551 2
R56601
2R56651 2
R56511
2
Q5660
3
5
4
R56611
2
Q5660
6
2
1
J5650
5
6
1234
J5660
5
6
1234
8 7
7
7
8
7
8
7
8
Page 53
GND
OUT
VIN+ VIN-
V+
ALERT
A0
SCL
SDA
GNDS
V+
GND
OUT
VIN+ VIN-
V+
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Battery Current Sense
(Tm0P) R:0x93,W:0x92
Battery Charger Thermal Sensor
Placement Note:Place near R8307
near L8300 and
bottom side
Q8301 and Q8302
DCIn Current Sense
Place sensor on
Place near R8308
Placement Note:
Temp Sensor has address x92,x93
1/16WMF-LF
05%
402
0
402MF-LF1/16W5%
NO STUFF
INA193SOT23-5
CRITICAL
402
1uF
CERM6.3V10%
1uF
402CERM
10%6.3V
402
20%0.1uF
CERM10V
TMP106
CRITICAL
WCSP-6
INA193SOT23-5
CRITICAL
A.0.0051-7261
Current & Thermal SensorsSYNC_MASTER=(MASTER)
9253
SYNC_DATE=(MASTER)
CHGR_CSO_R_N
LIO_BATT_ISENSE
TMPSNSR_A0
=SMBUS_TMPSNSR_SCL
=SMBUS_TMPSNSR_SDA
LIO_DCIN_ISENSE
CHGR_CSI_P
=PP3V3_S0_PDCISENS
CHGR_CSI_R_N
=PP3V3_S0_PBATTISENS
=PP3V3_S0_TMPSNSR
CHGR_CSO_R_P
R57511
2
R57501
2
U5705
2
15
3 4
C57151
2
C57051
2
C57501
2
U5750
C2
B2
A2
B1
A1
C1
U5715
2
15
3 4
67
49
48
48
49
67
8
67
8
8
67
Page 54
V+
V-
G
D
SIN
OUT
OUTIN
IN OUT
IN
THRML
CAP
SW
LED
VIN
CTRL
PADGND
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Right ALS Circuit
RTALS_OP_IN and RTALS_OP_COMP need to be matched
Keyboard LED Driver
Left ALS circuit has 1K series-R
Left ALS Filter
WF: This circuit does not use return, can tie cathode to GND on topcase flex
CRITICAL
SOT23-6-LFMAX4236EUTT
0.1UF10V20%
402CERM
1/16W5%
402MF-LF
120K
6.3V20%
402X5R
0.22UF
1/16W1%
402MF-LF
15.0K1/16W
1%
402MF-LF
1K
1K
1/16W1%
402MF-LFCRITICAL
TH
BS520EOF
1/16W5%
402MF-LF
5.1M
402
16V20%
CERM
0.01UF
SOT23-LF2N7002
7 34 45
45
1/16W1%
402MF-LF
4.53K
402
6.3V20%
X5R
0.22UF45
0.22UF
X5R402
20%6.3V
3.48K
MF-LF402
1%1/16W
7 34
DE2812C-SM
10UH-0.58A
CRITICAL
CERM603
20%1UF10V
402
10K1/16W
5%
MF-LF
45
MF-LF
1%101/16W
402
80
603
10%25V
1UF
X5R
80
DFNLT3491
CRITICAL
SYNC_DATE=12/04/2006SYNC_MASTER=M75_MLB
A.0.0051-7261
9254
ALS Support
KBDLED_CAP
=PP5V_S0_KBDLEDKBDLED_SWMIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.25 MMSWITCH_NODE=TRUE
LTALS_OUT
ALS_GAIN
RTALS_OP_COMP
=PP3V3_S3_RTALS
ALS_RT_OUT ALS_RIGHT
GND_SMC_AVSS
RTALS_OP_INRTALS_PHOTODIODE
RTALS_GAIN_L
GND_SMC_AVSS
ALS_LEFT
KBDLED_ANODESMC_SYS_KBDLED
KBDLED_RETURN
U5805
3
4
1
5
6
2
C5805 1
2
R58061
2
C5806 1
2
R58071
2
R58081
2
R58011 2
PD58001
2
R58001
2
C58001
2
Q58083
1
2
R58101 2
C58101
2
C58301
2
R58301 2
L5850
1 2
C5850 1
2
R58521
2
R58551
2
C5855 1
2
U5850
4
62
5
3
7
1
54
54
49
49
46
46
8
8
45
45
Page 55
CS*
SCL/SCLK
ADDR/SDI
MOT_ENABLE
ENABLE
VDD
X
Y
Z
FF/MOT
SDA/SDO
GND
IN
OUT
OUT
OUT
OUT
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
APN:338S0354
Desired orientation when
+Z (up)
ADDR low => 0x30, 0x31
ADDR high => 0x32, 0x33
I2C addresses:
Alias SCL/SDA to GND if using analog outputs only
+X
1
+Z (dn)
Package Top
1
+X
+Y +Y
Desired orientation whenplaced on board top-side:
Top-through View
placed on board bottom-side:
10V20%
402CERM
0.1uF
0.033UF10%16VX5R402
0.033UF10%16VX5R402
KXPS5-2050LGA
CRITICAL
1/16W5%
402MF-LF
10K
45
45
45
45
SMS_MOT_EN
0
MF-LF402
5%1/16W
SMS_MOT_DIS
402MF-LF1/16W5%0 100K
402MF-LF1/16W5%
9
48
48
X5R
10%16V
0.033UF
402
SYNC_DATE=12/04/2006SYNC_MASTER=M75_MLB
Sudden Motion Sensor (SMS)
051-7261 A.0.0
9255
SMS_ONOFF_L
SMS_Z_AXIS
SMS_MOT_EN
SMC_SMS_INT
=PP3V3_S3_SMS
=I2C_SMS_SCL
SMS_Y_AXIS
=I2C_SMS_SDA
SMS_X_AXIS
C59011
2
C59001
2
C59021
2
C59031
2
U5900
32
611
10
12
54
1 1314
789
R59001
2
R59011
2
R59021
2
R59031
2
8
Page 56
SO
VDD
CE*
SCK
VSSHOLD*
SI
WP* OUTIN
IN IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
402
0.1UF10V20%
CERMMF-LF
3.3K5%1/16W
402
3.3K
MF-LF
5%1/16W
402
402
1/16W5%
MF-LF
15
PLACEMENT_NOTE=Place R6114 within 12.7mm of U6100
CRITICAL
16MBITSOI
SST25VF016B
OMIT24 86
PLACEMENT_NOTE=Place R6190 within 12.7mm of U2300
402
15
1/16W5%
MF-LF
PLACEMENT_NOTE=Place R6191 within 12.7mm of U2300
15
1/16W5%
MF-LF402
24 86
24 86
402
15
1/16W5%
MF-LF
PLACEMENT_NOTE=Place R6193 within 12.7mm of U2300
24 86
SPI BootROM
56 92
A.0.0051-7261
SYNC_DATE=01/25/2007SYNC_MASTER=T9_NOME
SPI_CE_R_L<0>
SPI_SCLK_R
SPI_CE_L<0>
SPI_SCLK
SPI_A_SO_RSPI_WP_L
SPI_A_SI_R
SPI_HOLD_L
SPI_SO
SPI_SI_R
=PP3V3_S5_ROM
C61001
2
R61011
2
R61001
2
R61141 2
U6100
1
7
6 5
2
8
4
3
R61901 2
R61911 2
R61931 2
86
86
86
86
8
Page 57
BI
OUT
V-
V+
S3
S2
D1D2
D3D4
GATE
S1
G
D
S
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
<R2b>
Assuming 1% variance for R6910-R6915 and 3.42V:
REQ of R6910 (on LIO), R6912, & R6913 is 36.9K.
NOTE: R6910 is on LIO.System must provide 10K-70K impedance
to A52 adapter for system load detection.
DC-In Connector Battery Connector
Inrush Limiter
ACIN Detection
518S0456
(HOST_DETECT_L)
Worst case Vth: min:12.47V, max: 13.54V
Vref = 3.42V * (R2a / (R1a + R2a))Vth = (Vref / (R2b / (R1b + R2b))
<R1a><R1b>
Vth = 13.0VVref = 1.23V
<R2a>
518S0457
7 48
CRITICAL
M-RT-SM87438-0832-BLK
SOD-323
1SS355
7 45 46
5%
47
1/8WMF-LF805
NO STUFF
8V-100PF402
NO STUFF
4028V-100PF 8V-100PF
NO STUFF
402
4028V-100PF
NO STUFF
SM-LFLMC7211
CRITICAL
CRITICAL
SO-8SI4413ADY-E3
X5R603
20%25V
0.22uF
MF-LF
1M
402
5%1/16W
102K
MF-LF402
1%1/16W
57.6K
MF-LF402
1%1/16W
1%1/16W
402MF-LF
102K
402MF-LF1/16W
1%10.7K
CERM402
0.1uF20%10V
470K1/16WMF-LF
402
1%
330K
MF-LF
5%1/16W
402
2N7002SOT23-LF
MC74VHC1G08SC70
CRITICAL
M-RT-SM87438-1043-BLK
7 48
SYNC_DATE=(MASTER)
A.0.0
9257
DC-In & Battery ConnectorsSYNC_MASTER=(MASTER)
051-7261
=BATT_NEG
MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mm
MAKE_BASE=TRUEBATT_NEG=PPBATTNEG_G3H_BATT_CONN
=SMBUS_BATT_SDA=SMBUS_BATT_SCL
=BATT_POSVOLTAGE=18.5V
MIN_NECK_WIDTH=0.20mm
PP18V5_DCINMIN_LINE_WIDTH=0.60mm
SMC_BS_ALRT_L
ACIN_1V20_REF
=PP18V5_G3H_CHGR
PP18V5_G3H_CHGR
VOLTAGE=18.5V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.6mm
ACIN_DIV
SMC_BC_ACOK
=PPDCIN_G3HPPDCIN_G3H_RVOLTAGE=18.5V
MIN_NECK_WIDTH=0.20mmMIN_LINE_WIDTH=0.50mm
SMC_ADAPTER_EN
ACOK_AND_PS_ON
=PP3V42_G3H_ACIN
ACIN_ENABLE_DIV2_L
PP18V5_DCIN
ACIN_ENABLE_DIV_LMIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.2mm
=PP18V5_G3H_INRUSH
MIN_NECK_WIDTH=0.25mmMIN_LINE_WIDTH=0.6mm
BATT_POSMAKE_BASE=TRUE
=PPBATTPOS_G3H_BATT_CONN
=PPBUS_G3H_LIO_CONN
U69004
3
1
5
2
Q6950
5
6
7
8
4
1
2
3
C69501
2
R691612
R69141
2
R69151
2
R69121
2
R69131
2
C69101
2
R69211
2
R69501
2
Q69103
1
2
U6950
3
2
1
4
5
J6950
1
10
2
3
4
5
6
7
8
9
J6990
1
2
3
4
5
6
7
8
D69011 2
R69071 2 DZ6962
1
2
DZ6963
1
2DZ6961
1
2
DZ6960
1
2
67
46
46
45
67
67
57
45
40
67
57
8
7
7
7
67
34
8
36
8
7
7
Page 58
D
SG
D
SG
D
SG
D
SG
D
SG
D
SG
D
SG
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
D
S
G
D
S
G
D
S
G
IN
IN
IN
IN
IN
IN
IN
IN
IN
D
SG
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
3.3V S3 FET
5V S0 FET
1.25V GPU FET
PBUS used for lower Rds(on)
1.8V GPU FET
3.3V GPU FET
1.8V S0 FET
5V S3 FET
3.3V S0 FET1.25V S0 FET
SSM6N15FESOT563
SOT563SSM6N15FE
SSM6N15FESOT563
SSM6N15FESOT563
SSM6N15FESOT563
SSM6N15FESOT563
SSM6N15FESOT563
2N7002DW-X-FSOT-363
2N7002DW-X-FSOT-363
SOT-3632N7002DW-X-F
SOT-3632N7002DW-X-F
2N7002SOT23-LF
CRITICAL
IRF7707PBFTSSOP
FDC638P
CRITICAL
SM-LF
CRITICAL
SOT23FDC637AN
CRITICAL
FDC638PSM-LF
CRITICAL
FDC638PSM-LF
CRITICAL
FDC638PSM-LF
CRITICAL
SOT23FDC637AN
CRITICAL
LFPAKRJK0301DPB
FDM6296MICROFET3X3
CRITICAL
CERM-X5R402
10%0.15UF6.3V
66
1/16WMF-LF
1%
402
499
402
10%
CERM-X5R6.3V
0.15UF
5%1/16W
402MF-LF
100K
1%1/16WMF-LF402
15.0K
0.1UF
402X5R
10%16V
1%
MF-LF1/16W
402
69.8K
402
1%
499
MF-LF1/16W
66
16V
0.01UF
CERM402
10%
1UF10%10VX5R402
402MF-LF1/16W5%
100K
10K5%
1/16WMF-LF
402
66
0.15UF6.3VCERM-X5R
10%
402
MF-LF1/16W
499
1%
402
1/16WMF-LF
1%
402
499
6.3V10%
402
0.15UF
CERM-X5R
5%1/16W
100K
402MF-LF
5%
100K
402MF-LF1/16W
10V
0.1UF
20%
402CERM
1%1/16WMF-LF402
15.0K
MF-LF1/16W
1%69.8K
402
402
1/16WMF-LF
5%
220K
15.0K
1/16W
402MF-LF
1%
402
0.1UF
X5R
10%16V
402CERM
20%
0.1UF
10V
402MF-LF1/16W
1%69.8K
66
66
10%10V
0.068UF
CERM402
16V
0.01UF
CERM402
10%
402
69.8K1%
1/16WMF-LF
10K5%
MF-LF402
1/16W
47K
5%
402MF-LF1/16W
66
16V
0.01UF
CERM402
10%
16VX5R
0.033UF10%
402
402MF-LF1/16W5%
100K
10K5%
1/16WMF-LF
402
66
10%
0.01UF
16V
402CERM
CERM
0.068UF10%10V
402
47K
5%1/16WMF-LF402
402MF-LF1/16W
5%10K
15.0K
402MF-LF1/16W1%
66
10%
402CERM
0.01UF
16V
16V
0.033UF10%
X5R402
100K
5%1/16WMF-LF402
402MF-LF1/16W
5%10K
66
SSM6N15FESOT563
SYNC_MASTER=M75_MLB SYNC_DATE=04/24/2007
Power FETs
A.0.0
58
051-7261
92
=PP5V_S5_P1V25S0FETP1V25S0_SS
=PP1V25_S0_P1V25S0FET
=PPBUS_S5_P1V25S0FET
P5VS3_SS
P1V25S0_SS_RC
=PP1V25_S0_FET
=PP3V3_S3_P3V3S3FET
=PP5V_S0_FET
=PPBUS_S5_P1V8GPUFET
P1V8GPU_SS_RC
=PP1V8_GPU_FET
=PP5V_S3_FET=PP5V_S3_P5VS3FET
P1V8S0_SS_RC
P1V8S0_EN_L
=PP5V_S5_P1V8S0FET
P1V8S0_EN_L_RC
P1V8S0_SS
=PP1V8_S0_FET
=PP1V8_S0_P1V8S0FET
=P1V8S0_EN =PP5V_S5_P1V25GPUFET
=PP1V25_GPU_P1V25GPUFET
=P1V8GPU_EN
P1V25GPU_EN_L_RC
P1V25GPU_SS
=PP1V25_GPU_FET
P3V3S0_SS
P1V25GPU_SS_RC
=PP5V_S5_P1V8GPUFET
P1V25S0_EN_L_RC
P1V25S0_EN_L
=P1V25S0_EN
P1V25GPU_EN_L
=P1V25GPU_EN
P1V8GPU_EN_L
P1V8GPU_EN_L_RC
=P5VS3_EN
P3V3S3_EN_L
=P3V3S3_EN
P5VS0_EN_L
P3V3S0_EN_L
=P3V3S0_EN
P3V3GPU_EN_L
=P3V3GPU_EN
P5VS0_SS
=PP5V_S0_P5VS0FET
=P5VS0_EN
=PP3V3_S0_FET=PP3V3_S0_P3V3S0FET
=PP3V3_GPU_FET=PP3V3_GPU_P3V3GPUFET
P3V3GPU_SS
=PP3V3_S3_FET
P3V3S3_SS
=PP1V8_GPU_P1V8GPUFET
P1V8GPU_SS
P5VS3_EN_L
C70901
2
R70931 2
R70921 2
C70931 2
R70911
2 R70901 2
R70831 2
C70801
2
R70821 2
R70801 2
C70831 2
R70811
2
C70701 2
C7071 1
2
R70701 2
R70721
2
C70501
2
R70531 2
R70981 2
C70961
2
R70521 2
C70531 2
R70501 2
R70511
2
R70971 2
R70961 2
C70951 2
R70951
2
C7001 1
2
C70001 2
R70021
2 R70001 2
C70101 2
C7011 1
2
R70101 2
R70121
2
C70201 2
C7021 1
2
R70201 2
R70221
2
C70301 2
C7031 1
2
R70301 2
R70321
2
Q7091 6
21
Q7091 3
5 4
Q7081 3
54
Q7081 6
2 1
Q7051 3
54
Q7051 6
21
Q7096 3
54
Q7096 6
21
Q70026
2
1
Q70126
2
1
Q70023
5
4
Q70123
5
4
Q70723
1
2
Q7020
15
8
4
23
67
Q7000
1
2
5
6
3
4
Q70901
2
5
63
4
Q7070
1
2
5
6
3
4
Q7030
1
2
5
6
3
4
Q7010
1
2
5
6
3
4
Q70501
2
5
63
4
Q7080
5
4
1 2 3
Q7095
5
4
1 2 3
9
8
8
8
8
8
8
8
8
8 8
8
8
8
8
8
8
8
8
8 8
8 8
8 8
Page 59
IN
IN
IN
OUT
IN
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
OUT
VID0
DPRSTP*
NC
VW
COMP
FB
FB2
RBIAS
VR_TT*
NTC
VR_ON
PGOOD
PSI*
RTN
VSEN
DFB
DROOP
VO
OCSET
VSUM
ISEN2
VID1
VID3
VID2
VID4
VID5
VID6
PGND2
VIN VDD PVCC
LGATE2
PHASE2
UGATE2
ISEN1
PGND1
LGATE1
UGATE1
PHASE1
BOOT1
BOOT2
3V3
VDIFF
SOFT
DPRSLPVR
TPADGND
CLK_EN*
IMONOUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM
PLACE IT AWAY FROM THE EDGE OF THE BOARD/FAN
(IMVP6_PHASE2)
FOR GOOD THERMAL COUPLING
PLACE R7131 CLOSE TO & IN BTW L7100, L7101 & CPU
(IMVP6_VO)
(IMVP6_VO)
(IMVP6_ISEN2)
(IMVP6_FB)
(GND_IMVP6_SGND)
(IMVP6_NTC)LAYOUT NOTE:
Place R7126 in hot
spot of reg circuit.
These caps are for Q7102
(IMVP6_VW)
(IMVP6_COMP)
(GND)
(GND)
(IMVP6_ISEN1)
1
1
0
1
0 1
00
10
01
PSI*
1-Phase
Operation2-Phase
1-Phase1-Phase CCM
DCMDCM
ModeCCM
These caps are for Q7100
(IMVP6_PHASE1)
44A MAX CURRENT
(PGD_IN)(ISL9504A)
(IMVP6_VSUM)
DPRSTP*DPRSLPVR
(GND_IMVP6_SGND)
CERM
NO STUFF
0.0022UF10%50V
402
10K
1/16WMF-LF
1%
402402
10%10VCERM
0.22UF
SM
20%0.22UF25V
603X5R
7 10 16 23 83
7 16 25 83
28
28
7 45
7 9 16 28
SM
1/16WMF-LF
1%
10K
402402
10%
0.22UF
10VCERM
CERM50V10%0.0022UF
NO STUFF
402
20%
603X5R25V
0.22UF
MF-LF1/16W1%
402
10
402
1/16WMF-LF
10
1%
X5R
10%1UF10V
402
402
10
MF-LF1/16W1%
0.1uF16V
402
10%
X5R
1/16W
499
402
1%
MF-LF
402
ISL9504B
CERM50V10%
0.001UF
402MF-LF1/16W1%6.81K
ISL9504B
CERM6.3V20%
603
4.7uF
CERM402
16V
0.01uF10%
ISL9504B
402
1%1/16WMF-LF
1K
ISL9504B
402MF-LF1/16W1%1K
ISL9504B
402
50V
220PF
X7R-CERM
10%
ISL9504B
402
1/16WMF-LF
1%97.6K
402MF-LF1/16W5%1
MF-LF1/16W5%1
402
CERM402
50V10%
NO STUFF
0.001uF
1%1/16W
3.09K
402MF-LF
50V
402
5%
CERM
180pF
402
1K1/16WMF-LF
1%
402
2.61K1%
1/16WMF-LF
MF-LF402
11K1/16W1%
0.22UF6.3V10%
402CERM-X5R
402
10%
CERM
0.047UF16V
0
402MF-LF
5%1/16W
16VCERM
10%0.01UF
SIGNAL_MODEL=EMPTY
402
CERM402
16V
0.01uF10%
NO STUFF 5%
0
402MF-LF1/16W
CERM402
16V
0.01uF10%
0.22UF20%
402X5R
6.3V
SM
3.65K
MF-LF603
1%1/10W
3.65K1/10W
603MF-LF
1%
SM-IHLP
CRITICAL
0.36UH-30A-1.2M-OHM
OMIT
0.36UH-30A-1.2M-OHM
SM-IHLP
OMITCRITICAL
0.1UF25VX5R402
10%
7 12 83
7 12 83
7 12 83
7 12 83
7 12 83
7 12 83
7 12 83
ISL9504B
402CERM50V10%0.001UF
ISL9504B
CERM402
50V10%470PF
ISL9504B
402MF-LF
1%1/16W
255
402
16V10%
0.015UF
X7R
13.3K1/16W1%
MF-LF402
25V10%
X5R603
1UF
CRITICALCPU_NTC_A
10KOHM-5%0603-LF
1/16W
402MF-LF
1%147K
1/16W
402
1%
MF-LF
4.02K
MF-LF402
1/16W5%2.0K
SM
SM
50 59
50 59
11 83
11 83
CRITICAL
402
470K
402
5%
MF-LF
0
1/16W
10 46 83
402
5%
MF-LF
681/16W
NO STUFF
OMIT
QFN
ISL9504BCRZ
LFPAKRJK0305DPB
CRITICAL
LFPAKRJK0301DPB
CRITICAL
LFPAKRJK0305DPB
CRITICAL
RJK0301DPB
CRITICAL
LFPAK
LFPAKRJK0301DPB
CRITICAL
RJK0301DPBLFPAK
CRITICAL
POLY
20%
CRITICAL
25V
22UF
CASE-D2-LF CASE-D2-LF
20%
POLY
CRITICAL
25V
22UF22UF20%
CRITICAL
POLY25V
CASE-D2-LF
1UF
603X5R
10%25V
49 66
I848I849
CPU_NTC_BCRITICAL
0603-LF
10KOHM-5%
152S0624 2 IND,0.36uH,20%,30A,1.2mOhm L7100,L7101 CRITICAL SYNC_MASTER=(MASTER)
051-7261 A.0.0
59 92
SYNC_DATE=(MASTER)
IMVP6 CPU VCore Regulator
IMVP6_DFB
IMVP6_FB
IMVP6_VW
IMVP6_FB2
IMVP6_SOFT
IMVP6_VDIFF
IMVP6_VO_R
IMVP6_VID<0>
IMVP6_DROOP
IMVP6_UGATE2
=PPVIN_S5_CPU_IMVP
IMVP6_OCSET
IMVP6_VID<3>
IMVP6_NTC
PP5V_S0_IMVP6_VDDMIN_NECK_WIDTH=0.2 MMVOLTAGE=5V
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.25 MMIMVP6_VSEN_P MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.25 MMIMVP6_VSEN_N
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.25 MMIMVP6_ISEN2IMVP6_ISEN1 MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MMIMVP6_UGATE1 MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MMIMVP6_VSUM1IMVP6_COMP MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MMIMVP6_VW MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM
IMVP6_LGATE1
IMVP6_BOOT1IMVP6_BOOT2
IMVP6_PHASE1
IMVP6_ISEN1
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MMIMVP6_OCSET
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MMIMVP6_DROOP
IMVP6_FB MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MMIMVP6_VO
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MMIMVP6_DFBMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MMIMVP6_SOFTMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MMIMVP6_RBIASMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MMIMVP6_VDIFF
IMVP6_FB2 MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM
MIN_LINE_WIDTH=1.5 MMIMVP6_PHASE1 MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.25 MMIMVP6_BOOT1 MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MMIMVP6_LGATE1
MIN_NECK_WIDTH=0.25 MMIMVP6_VO1 MIN_LINE_WIDTH=0.25 MM
IMVP6_VID<6>
IMVP6_VO2 MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
IMVP6_VO1
IMVP6_VO2IMVP6_VDIFF_RC
IMVP6_COMP_RC
VR_PWRGD_CLKEN_L
IMVP6_UGATE2 MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM
IMVP6_PHASE2 MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM
IMVP6_PSI_L
IMVP6_NTC_R
PM_DPRSLPVR
IMVP_VR_ON
CPU_PROCHOT_L
MIN_NECK_WIDTH=0.2 MM
PPVIN_S5_IMVP6_VINMIN_LINE_WIDTH=0.25 MM
VOLTAGE=18.5V
IMVP6_COMP
CPU_DPRSTP_L
=PP3V3_S0_IMVP
=PPVIN_S5_CPU_IMVP_VIN
IMVP6_RBIAS
VR_PWRGOOD_DELAY
IMVP6_UGATE1
MIN_LINE_WIDTH=0.25 MM
VOLTAGE=3.3V
PP3V3_S0_IMVP6_3V3MIN_NECK_WIDTH=0.2 MM
IMVP6_VR_TT_L
IMVP6_VSUM2
IMVP6_VID<1>
IMVP6_VID<4>IMVP6_VID<5>
IMVP6_IMON
MIN_NECK_WIDTH=0.25 MMIMVP6_LGATE2 MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MMIMVP6_VSUM2 MIN_LINE_WIDTH=0.25 MM
IMVP6_BOOT2 MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.25 MM
IMVP_DPRSLPVR
IMVP6_VID<2>
IMVP6_PHASE2
IMVP6_LGATE2
CPU_VCCSENSE_N
VOLTAGE=0V
GND_IMVP6_SGNDMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.50 MM
IMVP6_VSEN_P CPU_VCCSENSE_P
IMVP6_ISEN2
=PP5V_S0_CPU_IMVP
IMVP6_VSUM
IMVP6_VO
IMVP6_VSUM1
=PPVCORE_S0_CPU_REG
IMVP6_VSEN_N
C71001
2
R71001 2
C71031 2
XW710412
C71151
2
XW710212
R71051 2
C71041 2
C71021
2
C7127 1
2
R71201 2
R71121 2
C7126 1
2R71211 2
C7130 1
2
R71191 2
C7107 1
2
R71101
2
C71351
2
C7110 1
2
R71131
2
R71091
2
C7113 1
2
R71141
2
R71041
2
R71071
2
C7116 1
2
R71171 2
C71291
2
R71181
2
R71301
2
R71151
2
C7128 1
2
C71341
2
R71221 2
C7131 1
2
C71321
2
R71231 2
C7133 1
2
C7121 1
2XW71001 2
R71011
2
R71061
2
L7100
1 2
L7101
1 2
C7196 1
2
C71061
2
C71141
2
R71111
2
C7105 1
2
R71161
2
C71091
2
R7131
1
2
R71081
2
R71271
2
R71971
2
XW71031 2
XW71011 2
R7126
1
2
R71981 2
R71991
2
U7100
48
36
26
47
10
17
45
46
16
11
12
21
3
24
23
32
30
25
6
8
33
291
34
28
2
31
4
15
7
49
35
27
22
13
37
38
39
40
41
42
43
20
18
44
5
14
19
9
Q7100
5
4
1 2 3
Q7103
5
4
1 2 3
Q7102
5
4
1 2 3
Q7105
5
4
1 2 3
Q7104
5
4
1 2 3
Q7101
5
4
1 2 3
C7117 1
2
C7153 1
2
C7155 1
2
C71541
2
R7132
1
2
49
83 83
59
59
83
83
8
83
59
59
59
59
59
59
59
8
59
59 59
59 59
59
59 59
59
59
59
59
59
59
59
50
59
50
59
59
59
59
59
59
59
59
59 59
59
59
59
59
59
8
8
59
59
59
59
59
59
7
59
59
59
59
8
59
7
59
Page 60
OUT
IN
IN
IN
IN
IN
IN
S
D
G
OUT
OUT
OCSET
VO
DFB
COMP
VSUM
DROOP
RTN
VDIFF
PGND VSS THRM_PAD
VSEN
FDE
AF_EN
VID4
SOFT
FB
VW
VR_ON
VID3
VID2
PGOOD
VID0
LGATE
UGATE
PHASE
BOOT
RBIAS VIN
PVCC
VID1
VDD
IMON
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(GFXIMVP6_AGND)
(GFXIMVP6_AGND)
(VO/PHASE_VSUM offpage flags for current sensing)
VO=Sense-, PHASE_VSUM=Sense+
(GFXIMVP6_PHASE_VSUM)(GFXIMVP6_VO)
(GND)(NB VID0)(NB VID1)
ENTER DIODE-EMULATION-MODE IN ALL STATES
NOTE: Intel recommendation to stuff 30K pull-up and100K pull-down on VR_EN per Crestline Issue #306022.
(NB VID2)(NB VID3)
(GFXIMVP6_VO)
ENABLED WHEN GFXIMVP6_AF_EN = 1
WHEN GFXIMVP6_FDE = 1
(GFXIMVP6_AF_EN)(GFXIMVP6_FDE)
Vout according to VID10A max output(Q7250 limit)
IN RENDER SUSPEND STATE, AUDIO FILTER150K
MF-LF
1%1/16W
402
10%
0.01uF
16V
402CERM
402
1/16W5%
MF-LF
0
10%
402CERM10V
0.22uF
6.98K
MF-LF
1%1/16W
402
0.001UF10%50V
402CERM
NO STUFF
470pF50V10%
402CERM
0.001UF10%50V
402CERM10%
50V
0.0033UF
402CERM
CERM402
10%50V
330pF
X5R402
16V10%
0.1uF
402MF-LF
1%1/16W
750
SM
MF-LF402
1/16W5%1K
0
MF-LF
5%1/16W
402
0
MF-LF
5%1/16W
402
PLACEMENT_NOTE=Place R7220 at NB
0
MF-LF
5%1/16W
PLACEMENT_NOTE=Place R7221 at NB
402
10%50V
402CERM
0.001UF
1K
MF-LF
5%1/16W
402
10
MF-LF
1%
402
1/16W
1uF10V10%
402X5R
X5R402
10%10V
1uF
CERM402
16V
0.01uF10%
CERM402
10%50V
680pF
10K1/16W
5%
NO STUFF
MF-LF402
NO STUFF
20K
5%1/16W
402MF-LF
10K
MF-LF
5%1/16W
402
MF-LF
10K5%1/16W
402
NO STUFF
10K
MF-LF
5%1/16W
402
SM SM
1
MF-LF402
1/16W5%
20%6.3V
10UF
603X5R
10UF
603
6.3V20%
X5R
402
1/16W1%
MF-LF
15.0K
3.01K
402
1%
MF-LF1/16W
CRITICAL
IHLP2525CZ-SM
0.47UH-26A
25V
22UF20%
CASE-D2-LFPOLY
CRITICAL
10%25VX5R
1UF
603
25VX5R
10%1UF
603
158K
MF-LF
1%1/16W
402
120PF5%50V
402CERM
2.21K
MF-LF
1%1/16W
402
3.65K
MF-LF
1%1/16W
402
NO STUFF
MF-LF
5%1/16W
402
0CERM
820PF
50V10%
402
680PF
50V10%
402CERM
9
9 60
9 60
9 60
9 60
9 60
5%1/16W
402MF-LF
22K
5%22K
MF-LF1/16W
402
5%1/16W
402MF-LF
22K
MF-LF
100K5%1/16W
402
MF-LF
30K5%1/16W
402MF-LF
22K5%
1/16W
4029 60
CRITICAL
PWRPK-1212-8SI7114DN
PWRPK-1212-8
CRITICAL
SI7108DNS
2.0V
330UF10%
D2TTANT
CRITICAL
1206
0.002
1/4WMF-LF
1%
50V
68PF5%
CERM402-1
50
50
CRITICAL
ISL6263B
QFN
IMVP6 NB Gfx Core Regulator
60 92
SYNC_MASTER=M75_MLB
051-7261 A.0.0
SYNC_DATE=03/05/2007
GFXIMVP6_VID<0>
GFXIMVP6_VID<0>=PPVCORE_S0_NBGFX_REG
MIN_NECK_WIDTH=0.3MMVOLTAGE=1.0V
MIN_LINE_WIDTH=0.6MMPPVCORE_S0_NBGFXSENSE_R
=PP5V_S0_GFXIMVP6
GFXIMVP6_VDIFF_RCMIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MMGFXIMVP6_COMP_RCMIN_NECK_WIDTH=0.3MM
GFXIMVP6_VDIFFMIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.3MM
=PPVCORE_S0_NBGFX_VSEN
MIN_NECK_WIDTH=0.3MMMIN_LINE_WIDTH=0.3MMGFXIMVP6_BOOT_RC
=PP3V3_S0_GFXIMVP6
=PPVIN_S0_GFXIMVP6
GFXIMVP6_VID<1>GFXIMVP6_VID<2>
GFXIMVP6_VID<4>GFX_VR_EN
GFXIMVP6_VID<3>
GFXIMVP6_PHASE_VSUMMIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.3MM
=PP3V3_S0_GFXIMVP6
GFXIMVP6_IMON
MIN_NECK_WIDTH=0.2MMVOLTAGE=5V
MIN_LINE_WIDTH=0.3MMPP5V_S0_GFXIMVP6_VDD
GFXIMVP6_VID<1>
VOLTAGE=5V
MIN_LINE_WIDTH=0.3MMPP5V_S0_GFXIMVP6_PVCCMIN_NECK_WIDTH=0.2MM
GFXIMVP6_VINMIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MMMIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MMGFXIMVP6_RBIAS
MIN_NECK_WIDTH=0.2MM
GFXIMVP6_BOOTMIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
GFXIMVP6_PHASEMIN_LINE_WIDTH=0.6MM
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.3MMMIN_LINE_WIDTH=0.6MMGFXIMVP6_UGATE
GFXIMVP6_LGATEMIN_NECK_WIDTH=0.3MMMIN_LINE_WIDTH=0.6MM
GFXIMVP6_PGOOD
GFXIMVP6_VID<2>GFXIMVP6_VID<3>
GFX_VR_EN
MIN_NECK_WIDTH=0.2MM
GFXIMVP6_VWMIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
GFXIMVP6_FBMIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MMGFXIMVP6_SOFT
GFXIMVP6_VID<4>
GFXIMVP6_AF_ENGFXIMVP6_FDE
GFXIMVP6_VSEN_P
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
GND_GFXIMVP6_AGNDMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MMGFXIMVP6_VDIFF_R
MIN_NECK_WIDTH=0.2MM
GFXIMVP6_VSEN_NMIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
GFXIMVP6_DROOPMIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MMGFXIMVP6_VSUM
MIN_NECK_WIDTH=0.2MM
GFXIMVP6_COMPMIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MMGFXIMVP6_DFB
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MMGFXIMVP6_VO
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MMGFXIMVP6_OCSET
R72022 1
C720312 R7251
1 2
C7256 1
2
R72221
2
C72221
2
C72331
2
C7221 1
2
C72201
2
C72711 2
C7272 1
2
R72771 2
XW72001 2
R72711
2R72321 2
R72201 2
R72211 2
C72231
2
R72501
2
R72001 2
C72001
2
C7201 1
2
C72021
2
C72511
2
R72041
2
R72032 1
R72051
2
R72061
2
R72071
2
XW7201
1
2
XW7202
1
2
R72081 2
C7266 1
2
C72651
2
R72701 2
R72722
1
L7200
1 2
C7252 C72531
2
C72541
2
R72301
2
C72321
2
R72331
2
R72311
2
R72012
1
C723012
C72311 2
R72911
2
R72921
2
R72941
2
R72961
2
R72951
2
R72931
2
Q7250
5
4
1 2 3
Q7251
5
4
1 2 3
C72601
23
R72601 2
C72731
2
U7200
30
17
5
11
10
6
32
28
21
3
20
31
19
22
1
9
2
33
18
16
7
23
24
25
26
27
14
12
29
8
15
13
4
60
8
60
60
60
60
60
60
60
9
7
8
8
8
8
8
9
9
9
9
9
91
Page 61
GND THRML_PAD
SKIPSEL
TONSEL
V5FILT
VIN
VREG5
VREG3
VREF2
EN5
EN3
VBST2
DRVH2
LL2
CS2
DRVL2
VO2
PGND2
COMP2
VFB2
PGOOD2
EN2
DRVH1
LL1
DRVL1
CS1
VO1
PGND1
VFB1
COMP1
PGOOD1
EN1
VBST1SYM (3 OF 3)
IN
IN
IN
OUT
OUT
IN
S
D
G
S
D
G
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
5.5A max output
5V Fixed 3.3V Fixed
Vout = 5.0V8A max output(L7320 limit)
When both are low TPS51120 VIN current drops from 100-150uA to 10-20uA.
NOTE: EN5 can float or tie to VIN for automatic 5V LDO enable EN3 can float or tie to VREG5 for automatic 3.3V LDO enable
(L7360 limit)
Vout = 3.3V
(Available for system use)TPS51120 LDO/Buffer outputs
50uA max load when EN5 & EN3 high
100mA max load when EN5 high
1UF25V
603X5R
10%
4.7UH
IHLP
CRITICAL
603X5R
10%25V
1UF
X7R603-1
0.1UF10%50V
20%6.3V
10UF
603X5R
X7R603-1
10%0.1UF50V
6.3VPOLY
CRITICAL
20%330UF
D3L
20%
CERM10V
10UF
805-2
CERM
20%10V
10UF
805-2
SM
20%
POLY
CRITICAL
CASE-B2
150UF6.3V
CASE-D2-LF
22UF25V
CRITICAL
20%
POLY25V
1UF
603X5R
10%
CASE-D2-LF
25V
22UF
POLY
20%
CRITICAL
CRITICAL
IHLP2525CZ-SM
2.2UH-14A
TPS51120LLP
CRITICAL
1%
MF-LF402
1/16W
4.22K1%
1/16W
402MF-LF
3.57K
603X5R
10UF20%
6.3V
603X5R6.3V20%10UF
5%4.7
402
1/16WMF-LF
1UF
X5R10V10%
402
66
66
66
46
46
66
0.001UF20%50V
CERM402
PWRPK-1212-8
CRITICAL
SI7114DN
SI7108DNSPWRPK-1212-8
CRITICAL
CRITICAL
PWRPK-1212-8SI7114DN
PWRPK-1212-8
CRITICAL
SI7108DNS
SM
PLACEMENT_NOTE=Place XW7360 next to C7390.
SM
PLACEMENT_NOTE=Place XW7320 next to C7350.
SM SM
61 92
A.0.0051-7261
SYNC_MASTER=M75_MLB SYNC_DATE=12/04/2006
5V / 3.3V Power Supply
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mmGND_P5VP3V3_SGND
MIN_NECK_WIDTH=0.2 mm
=P5VS5_EN=P5VS5_PGOOD=P3V3S5_PGOOD
=P5VP3V3_EN3=P5VP3V3_EN5
=P3V3S5_EN
VOLTAGE=0VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
GND_P3V3S5_PGND
=PPVIN_S5_P5VS5 =PPVIN_S5_P3V3S5
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmSWITCH_NODE=TRUE
P3V3S5_LL
MIN_NECK_WIDTH=0.2 mmGATE_NODE=TRUEP3V3S5_DRVL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mmGATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mmP3V3S5_DRVH
P3V3S5_CS
P3V3S5_VOVOLTAGE=0V
MIN_LINE_WIDTH=0.6 mmGND_P5VS5_PGND
MIN_NECK_WIDTH=0.2 mm P5VS5_VO
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
P5VS5_LLSWITCH_NODE=TRUE
VOLTAGE=5V
PP5V_S5_P5VP3V3_V5FILTMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
MIN_LINE_WIDTH=0.20 mmMIN_NECK_WIDTH=0.20 mmVOLTAGE=2V
PP2V0_S5_P5VP3V3_BUF
=PP5V_S5_REG
P5VS5_CSGATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
P5VS5_DRVL
GATE_NODE=TRUEP5VS5_DRVH
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
P5VP3V3_VREG3
=PP3V3_S5_REG
P3V3S5_VBSTMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.25 mm
VOLTAGE=5V
PP5V_S5_P5VP3V3_LDOMIN_NECK_WIDTH=0.20 mm
=PPVIN_S5_P5VP3V3
P5VS5_VBSTMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
C7300 1
2
L7360
1 2
C73411
2
C7364 1
2
C73901
2
C73241
2
C7352 1
2
C7350 1
2
C73511
2
XW73001 2
C73921
2
C7340 1
2
C73811
2
C7380 1
2
L7320
1 2
U7300
2 7
23 18
27 14
25 16
29 12
10
9
5
26 15
24 17
30 11
32
33
31
20
28 13
3 6
22
1 8
419
21
R73251
2
R73651
2
C7303 1
2
C73051
2R73061
2
C7306 1
2
C7302 1
2
Q7360
5
4
1 2 3
Q7365
5
4
1 2 3
Q7320
5
4
123
Q7325
5
4
123
XW7360
1
2XW7320
1
2 XW73251 2
XW73651 2
8 8
8 8
8
Page 62
OUT
IN
THRM_PAD
VFB
TRIP
VOUT
EN_PSV
GND PGND
V5DRVV5FILT
DRVL
DRVH
LL
TON
VBSTPGOOD
SYM (2 OF 2)
S
D
G
OUT
IN
THRM_PAD
VFB
TRIP
VOUT
EN_PSV
GND PGND
V5DRVV5FILT
DRVL
DRVH
LL
TON
VBSTPGOOD
SYM (2 OF 2)
S
D
G
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(GND)
(P1V05S0_TON)
<Ra>
(P1V05S0_VFB)
Vout = 1.2496V
(P1V25ENET_TON)
(GND)
(L7410? limit)
<Rb>
Vout = 0.75V * (1 + Ra / Rb)
<Rb>
8A max output
(L7460? limit)10A max outputVout = 1.051V
(P1V25ENET_VFB)Vout = 0.75V * (1 + Ra / Rb)
<Ra>1%
MF-LF402
1/16W
6.81K
66
66
402
1/16W1%
MF-LF
200
SM
TPS51117RGY_QFN14
CRITICAL
QFN
2.2UF10%16VX5R603
1UF10V10%
X5R402
SI7108DNS
CRITICAL
PWRPK-1212-8
0.1UF
X7R603-1
10%50V
SI7114DNPWRPK-1212-8
CRITICAL
IHLP2525CZ-SM
CRITICAL
2.2UH-14A
200K1%
402MF-LF1/16W
CRITICAL
POLY
20%25V
22UF
CASE-D2-LF 603
10%1UF25VX5R
12.1K1%
1/16WMF-LF
402
1/16W
8.06K1%
MF-LF402
50V
100PF
NO STUFF
CERM402
5%
PLACEMENT_NOTE=Place XW7430 close to C7415.
SM
X5R603
10UF20%
6.3V
5.62K
MF-LF
1%
402
1/16W
66
66
1/16WMF-LF402
1%
200
SM
CRITICAL
QFNTPS51117RGY_QFN14
X5R603
10%2.2UF
16V10%10VX5R402
1UF
CRITICAL
SI7108DNSPWRPK-1212-8
0.1UF
X7R603-1
10%50V
CRITICAL
SI7114DNPWRPK-1212-8
1.0UH-22A
CRITICAL
IHLP2525CZ-SM
402
200K1%
MF-LF1/16W
POLY
20%25V
CASE-D2-LF
22UF
CRITICAL
10%
603
1UF25VX5R
14.0K1%
1/16WMF-LF
402
1/16W
5.62K1%
402MF-LF 50V
CERM402
5%
NO STUFF
100PF
PLACEMENT_NOTE=Place XW7480 close to C7465.
SM
10UF6.3V
603
20%
X5R
CRITICAL
2.0V
330UF20%
CASE-B2POLY
2.0V
330UF
D2TTANT
CRITICAL
10%
SM
SM
92
SYNC_DATE=03/05/2007
62
A.0.0051-7261
SYNC_MASTER=M75_MLB
1.25V / 1.05V Power SupplyMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0V
GND_P1V05S0_SGND
P1V05S0_TRIP
P1V05S0_TON
MIN_NECK_WIDTH=0.2 mm
P1V05S0_VBSTMIN_LINE_WIDTH=0.25 mm
P1V05S0_DRVHMIN_LINE_WIDTH=0.6 mmGATE_NODE=TRUEMIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mmP1V05S0_LL
SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.2 mmP1V05S0_DRVLMIN_LINE_WIDTH=0.6 mmGATE_NODE=TRUEMIN_NECK_WIDTH=0.2 mm
=PP1V05_S0_REG
=PP5V_S5_P1V25ENET
P1V25ENET_TON
P1V25ENET_DRVHMIN_LINE_WIDTH=0.6 mmGATE_NODE=TRUEMIN_NECK_WIDTH=0.2 mm
=PP1V25_ENET_REG=PP1V25_ENET_REG
PP1V25_ENET_VDDQSNS
=P1V05S0_EN
=PP1V05_S0_REG
PP1V05_S0_VDDQSNS
VOLTAGE=5V
PP5V_S5_P1V05S0_V5FILTMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
P1V05S0_PGNDMIN_LINE_WIDTH=0.6 mm
VOLTAGE=0VMIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mmP1V25ENET_PGND
VOLTAGE=0VMIN_NECK_WIDTH=0.2 mm
=PPVIN_S0_P1V05S0
=PPVIN_ENET_P1V25ENET
MIN_LINE_WIDTH=0.6 mmP1V25ENET_LL
MIN_NECK_WIDTH=0.2 mmSWITCH_NODE=TRUE
=P1V05S0_PGOOD
=PP5V_S5_P1V05S0
MIN_NECK_WIDTH=0.2 mmVOLTAGE=5V
MIN_LINE_WIDTH=0.6 mmPP5V_S5_P1V25ENET_V5FILT
P1V05S0_VFB
MIN_LINE_WIDTH=0.6 mmGATE_NODE=TRUEP1V25ENET_DRVL
MIN_NECK_WIDTH=0.2 mm
=P1V25ENET_PGOOD
P1V25ENET_TRIP
P1V25ENET_VFB
MIN_NECK_WIDTH=0.2 mm
P1V25ENET_VBSTMIN_LINE_WIDTH=0.25 mm
=P1V25ENET_EN
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0V
GND_P1V25ENET_SGND
R74051
2
R74011 2
XW7400
1
2
U7400
13
9
1
7
12
8
6
15
2
11
10
4
14
5
3
C7401 1
2
C74001
2
Q7411
5
4
1 2 3
C7420 1
2
Q7410
5
4
1 2 3L7410
1 2
R74211
2
C7440 1
2
C74451
2
R74311
2
R74301
2
C74301
2
XW7430
1
2
C7415 1
2
R74551
2
R74511 2
XW7450
1
2
U7450
13
9
1
7
12
8
6
15
2
11
10
4
14
5
3
C7451 1
2
C74501
2
Q7461
5
4
1 2 3
C7470 1
2
Q7460
5
4
1 2 3L7460
1 2
R74711
2
C7490 1
2
C74951
2
R74811
2
R74801
2
C74801
2
XW7480
1
2
C7465 1
2
C7410
C74601
23
XW7401
1
2
XW7451
1
2
62
62 62
62 8
8
8 8
8
8
8
8
Page 63
MODE
VDDQSNSCOMP
NC0
NC1
VTTSNS
VTT
VTTREF
PGOOD
S3
S5
VTTGND THRM_PAD GND CS_GNDPGND
CS
LL
DRVL
DRVH
VDDQSET
VBST
VLDOINV5FILTV5IN
SYM (2 OF 2)
IN
IN
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM
(P1V8S3_DRVL)
(P1V8S3_LL)
Place next toC7545
(P1V8S3_DRVH)
VTT Enable
VDDQ/VTTREF Enable
VDDQ PGOOD
Vout = 1.80V or 1.825V18A max output
Vout = 0.75V * (1 + Ra / Rb)
(P1V8S3_CSGND)
<Ra>
Place at pin 23
(L7530 limit)
<Rb>
(P1V8S3_FB)
Vout = VDDQSNS/2
10mA max load
NCNC
(P1V8S3_VDDQSNS)
Vout = VTTREF
0.1UF
805X7R-CERM
10%50V
402MF-LF1/16W
21.5K0.1%
P1V8S3_1V825
0.1%
MF-LF1/16W
15.0K
402
CASE-C2
CRITICAL
330UF2.5VPOLY
20%
2.5V
CASE-C2POLY
20%
CRITICAL
330UF
25VX5R
1UF
603
10%
5%
CERM
NO STUFF
402
50V
100PF
QFNTPS51116
CRITICAL
402
1UF10V10%
X5R
1/16W
4.7
5%
MF-LF402
CRITICAL
20%6.3V
22UF
CERM-X5R805-3
CRITICAL
20%6.3V
22UF
CERM-X5R805-3
SM
SM
16VX5R402
10%0.033UF
66
805-2
10UF
CERM
20%10V
66
MF-LF402
1%6.81K1/16W
66
POLYCASE-D2-LF
20%25V
22UF
CRITICAL
25V
CASE-D2-LFPOLY
22UF20%
CRITICAL
CRITICAL
RJK0305DPBLFPAK
RJK0303DPBLFPAK
CRITICAL
CRITICAL
1.0UH-20A
IHLP4040DZ11-SM
10UF20%
X5R603
6.3V
LFPAKRJK0303DPB
CRITICAL
SM
20%
603X5R6.3V
10UF
SM
MF-LF
5%
1
1/10W
603
R7520RES,MTL FILM,21K,0.1,0402,SM,LF103S0192 P1V8S3_1V8CRITICAL1
SYNC_MASTER=M75_MLB
1.8V DDR2 Supply
051-7261
63 92
A.0.0
SYNC_DATE=12/04/2006
=PP1V8_S3_REG
=PP5V_S5_P1V8DDRREG
=PP0V9_S3_VTTR_BUF
MIN_LINE_WIDTH=0.6 mmGATE_NODE=TRUE
P1V8S3_DRVH_R
MIN_NECK_WIDTH=0.2 mm
=P1V8S3_EN=P1V8S3_PGOOD
=PP0V9_S0_VTT_LDO
DDRREG_VTTSNS
=PP1V8_S3_REG
VOLTAGE=5VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmPP5V_S5_P1V8DDRREG_V5FILT
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
P1V8S3_VBST
=P0V9S0_EN
P1V8S3_DRVLGATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
=PPVIN_S3_P1V8S3
VOLTAGE=0VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmGND_P1V8DDRREG_SGND
GATE_NODE=TRUEP1V8S3_DRVH
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
P1V8S3_LLSWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
P1V8S3_CSGND
P1V8S3_FB
VOLTAGE=1.8VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
P1V8S3_VDDQSNS
P1V8S3_CS
C7525
R75201
2
R75211
2
C7540 1
2
C75411
2
C75321
2
C7520 1
2
U7500
6
16
17
21
19
3
20
4
7
12
18
13
10
11
25
14
15
22
9
8
23
24
1
5
2
C7505 1
2
R75051 2
C7561 1
2
C75601
2
XW75601 2
XW75351 2
C7550 1
2
C7500 1
2
R75101
2
C7530 1
2
C7531 1
2
Q7530
5
4
1 2 3
Q7535
5
4
1 2 3
L7530
1 2
C75451
2Q7536
5
4
1 2 3
XW7545
1
2
C75011
2
XW7500
1
2
R75261 2
63
63
8
8
8
8
8 8
9
Page 64
IN
OUT
THRM_PAD
VFB
TRIP
VOUT
EN_PSV
GND PGND
V5DRVV5FILT
DRVL
DRVH
LL
TON
VBSTPGOOD
SYM (2 OF 2)
S
D
G
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Vout = 1.50V8A max output(L7620 limit)
(GND)
Vout = 0.75V * (1 + Ra / Rb)(P1V5S0_VFB)
<Rb>
<Ra>
(P1V5S0_TON)
NO STUFF
100PF50V
402
5%
CERM
0.1UF
X7R603-1
10%50V
CASE-D2-LF
22UF25V20%
POLY
CRITICAL
CRITICAL
2.5V
330UF
CASE-D2E-LF
20%
POLY
66
66
10%10V
1UF
X5R402
200
1/16WMF-LF402
1%
16V
2.2UF10%
603X5R
1/16WMF-LF402
1%200K
QFNTPS51117RGY_QFN14
CRITICAL
X5R25V
1UF10%
603
PWRPK-1212-8SI7114DN
CRITICAL
SI7108DNSPWRPK-1212-8
CRITICAL
SM
PLACEMENT_NOTE=Place XW7620 close to L7620.
SM
6.04K
MF-LF
1%
402
1/16W
603X5R
10UF20%6.3V
1/16W1%
10K
402MF-LF
1/16WMF-LF
402
10K1%
1.0UH-22A
IHLP2525CZ-SM
CRITICAL
A.0.0051-7261
64 92
SYNC_MASTER=M75_MLB SYNC_DATE=03/05/2007
1.5V Power Supply
P1V5S0_TON
P1V5S0_VBSTMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mmSWITCH_NODE=TRUEP1V5S0_LL
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUEP1V5S0_DRVH
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mmP1V5S0_DRVL
MIN_NECK_WIDTH=0.2 mm
P1V5S0_VFB
=PP5V_S5_P1V5S0
=P1V5S0_EN
=PPVIN_S0_P1V5S0
=P1V5S0_PGOOD
VOLTAGE=5V
MIN_LINE_WIDTH=0.6 mmPP5V_S5_P1V5S0_V5FILT
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmGND_P1V5S0_SGND
=PP1V5_S0_REG
P1V5S0_TRIP
=PP1V5_S0_REG
PP1V5_S0_VDDQSNS
C76301
2
R76101
2
R76111
2
C7601 1
2
R76051
2
L7620
1 2
C76101
2
C7615 1
2
C7620 1
2
C76321
2
C76001
2
R76011 2
R76191
2U7600
13
9
1
7
12
8
6
15
2
11
10
4
14
5
3
C76211
2
Q7620
5
4
1 2 3
Q7625
5
4
1 2 3
XW7620
1
2XW76001 2
64 64
8
8
8 8
Page 65
OUTINNR
NC THRML
EN
GND PAD
FB
BIAS
SWSHDN*
NC
VIN BOOST
GND
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(Switcher limit)200mA max output
<Ra>NC
<Rb>
Vout = 3.316V
Vout = 1.25V * (1 + Ra / Rb)
3.3V FW PHY Supply
NC
Backup power in case of FW busVP short to keep PHY powered.
1.95V FW PHY Supply
4V20%
402X5R
2.2uF16V10%
402CERM
0.01uF6.3V10%
402CERM
1uF
SONTPS799195
CRITICAL
402MF-LF1/16W1%324K
1/16W1%
402MF-LF
196K
50V5%
402CERM
22pF
402
20%
X5R6.3V
0.22uF50V
X7R-CERM
10%
1206
4.7UF
CRITICAL
TSOT23-8LT3470
SMD20E40C-X-F
SC-59
33uH
CDPH4D19F-SM
CRITICAL
CRITICAL
6.3V20%22UF
CERM-X5R805-3
SYNC_MASTER=M75_MLB
FW PHY Power SuppliesSYNC_DATE=12/04/2006
051-7261 A.0.0
9265
=PP1V95_FW_LDO
P1V95FW_NR
P3V3FW_SW
SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
VOLTAGE=33VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPPVIN_FW_P3V3FW
=PPVP_FW_P3V3FW
=PPVIN_FW_P1V95FW
=PPBU_S0_P3V3FWP3V3FW_BOOST
P3V3FW_FB
=PP3V3_FW_REG
C77221
2
C7721 1
2
C7720 1
2
U7720
4
3
6
5
2
1
7
R77101
2
R77111
2
C7710 1
2
C7705 1
2
C7700 1
2 U7700
7
6
8
4
2
1 5
3
D77001
2
3
L7700
1 2
C77011
2
8
8
8
8
8
Page 66
FB
BIAS
SWSHDN*
NC
VIN BOOST
GND
OUT
OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTIN
IN
OUT
OUT
OUT
OUT
IN
OUT
VPG
V2
V4
V3
VREF RST*
CRT
THRM_PADGND
PBR*
V1
OUT
OUT
G
D
S
OUT
G
D
S
Y
B
A
Y
B
A
IN
G
D
S
OUT
G
D
S
IN
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Power Control Signals
Other S0 Rails PWRGD CircuitNOTE: 0.9V/2.5V is not checked!(PM_S4_STATE_L)
Need to ensure that
first via RC control
before 99ms SMC timer expires.
not be necessary to stuff if GPU
200mA max output(Switcher limit)
LTC2900 typical threshold is 93.5% (4.675V, 3.086V, 1.685V, 1.120V)
PP1V2_GPU needs to ramp
Fast wake glitch filter. Should
TPS51117 PGOOD threshold 92.5-97.5% (0.98 - 1.02V)
TPS51117 PGOOD threshold 92.5-97.5% (1.36 - 1.46V)
G84M GPU requires rails to come
1) 1.2V
Trst = 216msTrst = 4.6ms/nF
NC
Does not include GFX rails
3.425V "G3Hot" Supply
<Ra>
Unused PGOOD Signals
Vout = 1.25V * (1 + Ra / Rb)
NC
<Rb>
Vout = 3.425
1000
11
00
11
10Battery Off (G3Hot)
Sleep (S3)
Soft-Off (S5)
State
Supply needs to guarantee 3.31V delivered to SMC VRef generator
Run (S0)
SMC_PM_G2_ENABLE PM_SLP_S4_L PM_SLP_S3_L
Reports when 1.5V S0 and 1.05V S0 are in regulation
To CPU IMVP6
GPU core voltage.
supplies and PGOOD revalidate
R7853 acts as pull-up for open-drain GPIO.
(EXTGPU_PWR_EN)
4) 1.8V3) Vcore2) 3.3V
up in the following order:
(PM_SLP_S3_L)
VIDs are changingdeassert while GPU
(PM_ENET_EN)
SB GPIO has ability to force all GPU rails off
1.5V / 1.05V PWRGD Circuit
TPS51117 PGOOD does not
CRITICAL
LT3470TSOT23-8
25V10%
1206-1X5R
10UF
805-3CERM-X5R
22UF20%6.3V
1/16W1%
402MF-LF
200K
1/16WMF-LF
5%
402
100K
58
58 62
35
63
49
64
34
58
58
58
63
MC74VHC1G08SC70
43
34
61
58
58
0.1UF
CERM402
20%10V
7 36
23 28
49 59
CERM402
10%16V
0.047UF
NO STUFF
62
61
61
64
61
ISL9504A
01/16W5%
402MF-LF
10V20%
CERM402
0.1UF 93.1K
MF-LF402
1/16W1%
9.53K1/16W
402MF-LF
1%
LTC2900DFN
CRITICAL
16V
0.047UF10%
402CERM
MF-LF
1%1/16W
100K
402
MF-LF402
1%1/16W
124K
402CERM10V20%
0.1UF10K5%
402MF-LF1/16W
0.1UF20%
402
10VCERM
402CERM
20%10V
0.1uF
58
58
SOT-3632N7002DW-X-F
74 76
2N7002DW-X-FSOT-363
MF-LF1/16W
5%
402
100K
MF-LF1/16W
5%
402
10K
SC70MC74VHC1G09
5%
402
1/16WMF-LF
10K
10K
1/16WMF-LF
5%
402
CERM-X5R402
10%0.47UF6.3V
NO STUFF
CERM402
10%16V
0.047UF
SC70MC74VHC1G09
NO STUFF
1/16WMF-LF
5%
402
0
62
100K
402
1/16WMF-LF
5%10K
1/16W5%
MF-LF402
2N7002DW-X-FSOT-363
28 45 46
1/16W1%
402MF-LF
348K
33UH-0.39A
S1024AS-SM
CRITICAL
SOT-3632N7002DW-X-F
76
50V5%
402CERM
22pF
1/16W
402
5%
MF-LF
100K
7 25 36 40 45
1/16W5%
402MF-LF
10K
7 25 45
5%1/16W
402MF-LF
100K
45
6.3V20%
402X5R
0.22uF
10K
MF-LF402
5%1/16W
3.425V G3Hot Supply & Power Control
051-7261
9266
A.0.0
SYNC_MASTER=M75_MLB SYNC_DATE=04/02/2007PM_G2_ENMAKE_BASE=TRUE
=PP3V42_G3H_PWRCTL
SMC_PM_G2_EN
P3V42G3H_SWMIN_LINE_WIDTH=0.5 mm
SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.25 mm
=PP3V42_G3H_REG
=P5VP3V3_EN3=P5VP3V3_EN5
=P5VS5_EN=P3V3S5_EN
S0PGOOD_PWROK
MAKE_BASE=TRUEEXTGPU_PWR_EN
MAKE_BASE=TRUEPM_S4_STATE_L
P1V8S3_ENMAKE_BASE=TRUE
LIO_S3_EN=USB_EXTA_EN
=P1V8S3_EN
MAKE_BASE=TRUEPM_ENET_EN
MAKE_BASE=TRUEPM_SLP_S3_L
=P1V8S0_EN
LIO_S0_EN_L=PP3V3_S0_PWRCTL
=P5VS0_EN=P3V3S0_EN
=PP5V_S5_PWRCTL
=GPUVCORE_PGOOD
=ENET_VMAIN_AVLBL
=P1V25S0_EN
=PBUSVSENS_EN
=P1V05S0_EN
=P1V5S0_EN
=PP3V3_GPU_PWRCTL
PVCOREGPU_EN_L
MAKE_BASE=TRUEPM_GPUP1V8FET_EN =P1V8GPU_EN
PM_GPUVCORE_ENMAKE_BASE=TRUE
=GPUVCORE_EN
S0PGOOD_P1V2_DIV
S0PGOOD_VREF
PP3V3_S0
=PP3V3_S0_ALLSYSPG=PP3V3_S5_P1V5P1V05PG
=P5VS3_EN
=PPVIN_G3H_P3V42G3HP3V42G3H5_BOOST
P3V42G3H_FB
=P1V25ENET_PGOOD
=P3V3S3_EN
=P1V8S3_PGOOD
=P3V3ENET_ENALL_SYS_PWRGD
MAKE_BASE=TRUETP_P1V25ENET_PGOOD
TP_P1V8S3_PGOODMAKE_BASE=TRUE
PP1V25_S0
PP5V_S0
S0PGOOD_VPG
S0PGOOD_CRT
IMVP6_IMON
P1V5P1V05S0_PGOODMAKE_BASE=TRUE
=P1V5S0_PGOOD
=P1V05S0_PGOOD
=P1V25GPU_EN
=P0V9S0_EN
PP1V8_S0
=PVCOREGPU_EN=P3V3GPU_EN
=P1V25ENET_EN
=PM_SLP_S3_DELAY_L
=PP3V3_S5_PWRCTL
PM_SLP_S3_DELAY_LMAKE_BASE=TRUE
PM_SLP_S3_LS5VMAKE_BASE=TRUE
R78101
2
L7810
1 2
C7810 1
2
C7805 1
2U7800
7
6
8
4
2
1 5
3C7800 1
2
C78151
2
R78111
2
R78651
2
U7880
3
2
1
4
5
C78801
2
R78511
2
R78501
2
Q78506
2
1
Q78503
5
4
R78561
2
R78571
2
R78581
2
R78531
2
C78531
2
R78661
2
C7873 1
2
R78711
2
R78701
2
U7870
3
6
5
4
11
2 10
1
9
7
8
C7875 1
2
R78741
2
R78731
2
C787212
R78751
2
C7871 1
2
C7870 1
2
Q78513
5
4
Q78516
2
1
R78521
2
R78541
2
U7850
3
2
1
4
5
R78591
2
R78551 2
C78551
2
C7859 1
2
U7858
3
2
1
4
5
R786012
91
8
8
8
8 8
8
8
8
8
62
63
8
8
7
8
8
Page 67
S3
S2
D1D2
D3D4
GATE
S1
V-
V++
-
VDDPVDD
ACLIM
ICM
ICOMP
VCOMP
VADJ
CELLS
CSOP
CHLIM
CSON
ACPRN
VREF
SGATE
CSIN
DCIN
BGATE
BOOT
UGATE
LGATE
PHASE
DCSET
PGND
THRML_PAD
DCPRN
CSIP
EN
ACSET
GND
D
SG
D
SG
D
SG
D
SG
D
SG
D
SG
D
SGD
S G
D
G S
GND
VCC
PGOOD
OUT
FB
IN
SHDN*
I.C.THRMLPAD
S3
S2
D1D2
D3D4
GATE
S1
S3
S2
D1D2
D3D4
GATE
S1
S3
S2
D1D2
D3D4
GATE
S1
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
As shown, Ichg = 4.5A max
Adapter Input Current Limit
353S1244
NCARE PROVIDED WITH SUFFICIENT CURRENT WITHOUT
Battery Charge FETs
Energy Star LDO
PBus Supply & Battery Charger
10A MAX, LIMITED BY L7900, Q7901
VOLTAGE FOLLOWER GUARANTEES CURRENT LIMIT CIRCUITS
As shown, Isys =~4.6A max
SINKING CURRENT FROM VREF.
Battery Charge Current Limit
SM
3.01K
1%1/16WMF-LF402
402
6.3V
1uF
CERM
10%
1uF
CERM402
10%6.3V
G
D
S
SMIRLML5203-2.6A
0.1UF
603
20%
CERM25V
402
1%1/16W
3.01K
MF-LF
0.047UF
CERM402
10%16V
1/16W1%
402MF-LF
17.8K
16V10%
402CERM
0.01UF
20.0K
MF-LF402
1%1/16W
402MF-LF1/16W1%11.3K
MF
5%3W
27
CRITICAL
2525
1/16WMF-LF
402
1%11.3K
110K1%
MF-LF402
1/16W
SI4413ADY-E3SO-8
CRITICAL
1206
CRITICAL
8AMP-24V
MF-LF402
1%1/16W
158K
CERM
10%50V
680pF
NOSTUFF
402
2.2
1/16WMF-LF402
5%
1/16W5%
402MF-LF
270
ISL6255A
CERM603
20%25V
0.1UF
NOSTUFF
0.22uF
CERM402
10%10V
470K
MF-LF402
1%1/16W
MF-LF
49.9
603
0.5%1/16W
50V
0.0022uF
603
10%
CERM
MF-LF402
1%1/16W
100K
47
805
5%1/8WMF-LF
100K
MF-LF402
1%1/16W
0.02
MF0612
0.5%1W
SM SM
SOD-323
1SS355
CASE-D2-LF
22UF20%25VPOLY
CRITICAL
1UF
X5R603
10%16V
CRITICAL
RJK0305DPBLFPAK
LFPAKRJK0305DPB
CRITICAL
3.48K
MF-LF402
1%1/16W
10K5%1/16WMF-LF402
0.1uF
X5R402
16V10%
10K
MF-LF402
5%1/16W
SM SM
ISL6257H
56.2K
MF-LF402
1%1/16W
1/16W1%
402MF-LF
34.8K
ISL6255A
CRITICAL
HPA00141AIDCKRSC70-5 CERM
402
20%10V
0.1UF
CRITICAL
22UF
POLYCASE-D2-LF
20%25V
CRITICAL
2.2UF
X5R-CERM805
10%25V
805
10%25VX5R-CERM
2.2UF
CRITICAL CRITICAL
22UF
POLYCASE-D2-LF
20%25V
CRITICAL
6.3X5.5SM1
NOSTUFF
100UF16V20%
ELEC
FDA1254-SM
4.7UH-10.2A
CRITICAL
50V10%470PF
CERM402
ISL6257H
CERM
0.0033uF
ISL6255A
50V10%
402
QFN
CRITICAL
ISL6255AHRZ
ISL6255A
SSM6N15FESOT563 SOT563
SSM6N15FE
SSM6N15FESOT563
SOT563SSM6N15FE
SOT-523-3BAV99T-X-F
SSM6N15FESOT563
SSM6N15FESOT563
SSM6N15FESOT563
SOT563SSM6N15FE
SSM3K15FVSOD-VESM
402
1%1/16W
100K
MF-LF
25V10%
603X5R
1UF
1UF
X5R
10%25V
603MF-LF
1%200K
402
1/16W
1/16W
402MF-LF
1%19.6K
BAT54CW-X-FSOT-323
TDFNMAX8719
100K
MF-LF402
5%1/16W
1%
MF-LF1/16W
402
3.57K
SOT23
CRITICAL
MMBZ5235B
CRITICAL
SI4413ADY-E3SO-8
1/16WMF-LF
5%
470K
402
5%
402MF-LF1/16W
330K
10%
X5R25V
402
0.1UF
X5R
402
10%
16V
0.033uF
X7R
10%
402
25V
1000PF
SO-8SI4413ADY-E3
CRITICAL
100K
MF-LF402
1%1/16W
NOSTUFF
0.1UF
CERM402
20%10V
SOD-123
B0530WXF
CRITICAL
4.7
MF-LF402
5%1/16W
0.1UF
CERM603
20%25V
X7R
10%25V
402
0.0082uF
MF-LF1/16W
18
402
5%
0.01
MF0612
0.5%1W
2.2
402
5%1/16WMF-LF
CRITICAL
SO-8SI4413ADY-E3
330K
MF-LF402
5%1/16W
MF-LF
39.2K
402
1%1/16W
35.7K
MF-LF402
1%1/16W
0.01uF
CERM402
10%16V16V
X5R
10%0.1uF
402
0.01UF
CERM402
20%16V
NOSTUFF
0.01UF
CERM402
10%16V
NOSTUFF
50VCERM402
0.001UF10%
SYNC_DATE=03/08/2007
67 92
A.0.0051-7261
SYNC_MASTER=M75_LIO
PBus Supply & Batt. Charger
ISL6257H1 R7904116S0004 0 OHM,5%,1/16W,0402,SMD,LF
ISL6257HCRITICAL1 U7900353S1510 ISL6257H,BATT CHGR,28P,QFN,LF
SMC_SYS_ISET_LCHGR_SGND
CHGR_SGND
CHGR_VREF_VF
=PP18V5_G3H_CHGR
PPVBAT_G3H_CHGR_OUT
CHG_EN_DIV_LMIN_LINE_WIDTH=0.2mmMIN_NECK_WIDTH=0.2mm
CHGR_ACSET
MIN_NECK_WIDTH=0.25mm
PPVBATT_G3H_FETMIN_LINE_WIDTH=0.6mm
VOLTAGE=12.6V
CHGR_SGND
=PPVBAT_G3H_CHGR_REG
CHGR_ICM_R
CHGR_SGNDSWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.2mm
CHGR_PHASE
MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.6mm
CHGR_LGATE
CHGR_SGND
CHGR_ICOMPCHGR_ACLIM
CHGR_ICM
CHGR_VDD
CHGR_VCOMP
CHGR_DCIN
CHGR_CHLIM
CHGR_VREF
LDO_FDBK
=PPVBAT_G3H_CHGR_REG
PPVBATT_G3H_PREMIN_LINE_WIDTH=0.6mm
VOLTAGE=12.6VMIN_NECK_WIDTH=0.25mm
VOLTAGE=12.6VMIN_NECK_WIDTH=0.25mmMIN_LINE_WIDTH=0.6mmPPVBATT_G3H_FET_D
INRUSH_EN_DIV_L
MIN_NECK_WIDTH=0.25mmMIN_LINE_WIDTH=0.6mm=BATT_POS
=PPVBATT_G3H_LIO_CONN
=BATT_NEG
=GND_BATT_CHGND
CHGR_ACSET_D
SMC_BATT_TRICKLE_EN_L
CHGR_UGATE
MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.2mm
CHGR_ACPRNCHGR_ACSET
MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.6mmCHGR_BOOT
CHGR_SGATE
MIN_LINE_WIDTH=0.2mmMIN_NECK_WIDTH=0.2mm
CHGR_VDDP
CHGR_CSI_N
CHGR_DCIN
PPVDCIN_G3H_RMIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mm
CHGR_CSI_R_NNO_TEST=TRUE
=PP3V42_G3H_ACIN
=PP3V42_G3H_ACIN
=PP3V42_G3H_ACIN
=PP3V42_G3H_ACIN
CHGR_VREF
CHGR_PHASE_R
NO_TEST=TRUE
CHGR_CSI_P
CHGR_CSO_R_P
CHGR_BOOT_R
CHGR_VDD
CHGR_SGND
SMC_SYS_ISET
SMC_BATT_ISET
PPVDCIN_G3H_PREMIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mm
CHGR_CSO_P
CHGR_CSO_N
CHGR_VREF_VF
MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mm
PPVBAT_G3H_CHGR_OUT
CHGR_VCOMP_C
NO_TEST=TRUECHGR_CSO_R_N
NC_CHGR_BGATE NO_TEST=TRUE
CHGR_ACLIM_R CHGR_ACLIM
TP_CHGR_DCSET
TP_CHGR_VADJCHGR_VDDP
CHGR_ACPRN
TCHG_EN_DIV2_L
SMC_BC_ACOK
SMC_BATT_CHG_EN
CHG_EN_DIV2_L
CHGR_ACPRN
MIN_LINE_WIDTH=0.5mm
VOLTAGE=12.6V
PPVBATT_G3H_DIOMIN_NECK_WIDTH=0.25mm
TP_CHGR_DCPRN
CHGR_EN
NC
PBUS_LDO_EN
=PP18V5_G3H_CHGR
NC
MIN_LINE_WIDTH=0.5MMLDO_OUTMIN_NECK_WIDTH=0.2MM
CHGR_VDD
CHGR_CSO_R_N
CHGR_EN
CHGR_CHLIM_R
SMC_BATT_ISET_L
CHGR_CSO_NCHGR_CSO_P
CHGR_SGND
CHGR_CHLIM
CHGR_VREF_VF
TCHG_EN_DIV_LMIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.2mm
C79401
2
R79411
2
R79441
2
C79411
2
R79501
2
C7900
12
C790112
Q7900
5
6
7
8
4
1
2
3
R79101
2
C79041
2
D790012
R79001 2
C79031 2
C7902 1
2
R79051 2
R79081 2
R79061 2
Q7920
5
6
7
8
4
1
2
3
R79311
2
R79221
2
R79231
2
C7920 1
2
C7921 1
2
C7924 1
2
C7922 1
2 C79271
2
XW79001 2
R79021 2
C7912 1
2
C79111 2
Q7940
3
1
2
R79601 2
C79611
2
R79621 2
C79621
2
R79631
2
R79661
2
R79201 2
R79401
2
Q7921
5
6
7
8
4
1
2
3
F79021 2
R79671
2
C79151 2
R79031 2
R79041 2
C79071
2
C79251
2
R79301
2
R79701 2
C79701
2
R79211 2
R79241
2
R79071 2
XW7901
1
2
XW7902
1
2
D79211 2
C79081
2
C79101
2
Q7901
5
4
1 2 3
Q7902
5
4
1 2 3
R79681
2
R79691
2
R79791
2
XW7904
1
2
XW7903
1
2
R79921
2
R79931
2
U79011
3
4
2
5
C79801
2
C79061
2
C79161
2
C79171
2
C79051
2
C7909 1
2
L7900
1
2
3C79901
2
C79911
2
U79008
23
27
17
142
7
20
19
22
21
25
24
28
1
10
5
3
12
11
16
18
29
15
9
4
26
13
6
Q7960 6
2 1
Q7960 3
5 4
Q7961 6
2 1
Q7961 3
5 4
D7940
12
3
Q7924 3
5 4
Q7922 3
5 4
Q7922 6
2 1Q79246
21
Q79503
1 2
C7950 1
2
C79511
2R79521
2
R79531
2
D7950
1
2
3
U7950
32
7
1 8
56
9
4
R79541
2
R79641
2
D79031 3
Q7970
5
6
7
8
4
1
2
3
R79711 2
R79721 2
C79711 2
57
67
67
67
67
46
67
67
67
57
57
46
57
57
57
57
67
45
46
67
67
67
67
67
57
67
67
67
8
67
67
67
67
67
67
67
8
7
8
7
9
45
67
67
67
67
53
8
8
8
8
67
53
53
67
67
45
45
67
67
67
67
53
67
67
67
34
45
67
67
9
57
67
53
67
67
67
67
67
67
Page 68
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PEX_TX0
PEX_TX0_L
PEX_RX4
PEX_RX0
PEX_TX1PEX_RX1
PEX_RX2 PEX_TX2
PEX_RX3 PEX_TX3
PEX_TX4
PEX_TX5PEX_RX5
PEX_TX6PEX_RX6
PEX_RX7 PEX_TX7
PEX_TX8PEX_RX8
PEX_TX9PEX_RX9
PEX_TX10PEX_RX10
PEX_TX11PEX_RX11
PEX_TX12PEX_RX12
PEX_TX13PEX_RX13
PEX_TX14PEX_RX14
PEX_TX15PEX_RX15
PEX_TSTCLK_OUTPEX_REFCLK
PEX_TX1_L
PEX_TX2_L
PEX_TX3_L
PEX_TX4_L
PEX_TX5_L
PEX_TX6_L
PEX_TX7_L
PEX_TX8_L
PEX_TX9_L
PEX_TX10_L
PEX_TX11_L
PEX_TX12_L
PEX_TX13_L
PEX_TX14_L
PEX_TX15_L
PEX_TSTCLK_OUT_L
PEX_RST_L
PEX_REFCLK_L
PEX_RX15_L
PEX_RX14_L
PEX_RX13_L
PEX_RX12_L
PEX_RX11_L
PEX_RX10_L
PEX_RX9_L
PEX_RX8_L
PEX_RX7_L
PEX_RX6_L
PEX_RX5_L
PEX_RX4_L
PEX_RX3_L
PEX_RX2_L
PEX_RX1_L
PEX_RX0_L
PCI-EXPRESS BUS INTERFACE
NC
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_PLLAVDD
PEX_PLLDVDD
PEX_PLLGND
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
- =PP1V2_GPU_PEX_PLLXVDD- =PP1V2_GPU_PEX_IOVDDQ- =PP1V2_GPU_PEX_IOVDD
Signal aliases required by this page:
BOM options provided by this page:
1500mA
20mA
180mA
(NONE)
(NONE)
Power aliases required by this page:
Page Notes
250mA
PEX 1.2V Current = 2A
15 84
10% 16V
0.1uF
402X5R
40210% 16V X5R
0.1uF
15 84
15 84
X5R10% 16V 402
0.1uF
10% 16V X5R
0.1uF
402
15 84
15 84
10% 16V X5R
0.1uF
4020.1uF
10% 16V X5R 402
15 84
15 84
10% 16V X5R
0.1uF
402
10% 16V X5R
0.1uF
402
15 84
15 84
10% 16V X5R
0.1uF
402
10% 16V X5R
0.1uF
402
15 84
0.1uF
X5R16V10% 402
15 84
10% 16V X5R
0.1uF
402
10% 16V X5R
0.1uF
402
15 84
15 84
10% 16V X5R
0.1uF
402
10% 16V X5R
0.1uF
402
15 84
15 84
10% 16V X5R
0.1uF
402
402X5R16V
0.1uF
10%
10% 16V X5R
0.1uF
402
15 84
15 84
10% 16V X5R
0.1uF
402
10% 16V X5R
0.1uF
402
15 84
15 84
10% 16V X5R
0.1uF
402
10% 16V X5R
0.1uF
402
15 84
402
0.1uF
X5R16V10%
15 84
10% 16V X5R
0.1uF
402
10% 16V X5R 402
0.1uF
15 84
15 84
10% 16V X5R
0.1uF
402
10% 16V X5R
0.1uF
402
15 84
15 84
10% 16V X5R
0.1uF
402
0.1uF
402X5R16V10%
10% 16V X5R 402
0.1uF
402
0.1uF
X5R16V10%
402
0.1uF
X5R16V10%
402
0.1uF
10% X5R16V
OMIT
(1 OF 8)BGA
NB8P-GS-W-A2
OMIT
(2 OF 8)BGA
NB8P-GS-W-A2
CERM
4.7UF
603
20%6.3V
CERM402
1UF10%6.3V
402CERM
20%0.1UF10V
0.1uF
X5R16V10% 402
20%
CERM402
0.1UF10V
CERM
4.7UF20%6.3V
603 603
6.3V20%
4.7UF
CERM
20%
805
6.3V
22UF
CERM-X5R
0.1uF
402X5R16V10%
1UF6.3V10%
402CERM
22UF6.3V
805
20%
CERM-X5RCERM6.3V20%
603
4.7UF
CERM
10%6.3V
1UF
402
6.3V10%1UF
402CERM
10V
0.1UF20%
CERM402
CERM
20%10V
0.1UF
402
0.1UF20%10V
402CERM
16V 402
0.1uF
X5R10%
603
6.3V20%4.7UF
CERMCERM402
10V20%0.1UF
603
6.3V20%
4.7UF
CERM
10NH-600MA
0603
10NH-600MA
0603
402
0.1uF
X5R16V10%
402
0.1uF
X5R16V10%
402
0.1uF
X5R16V10%
402
0.1uF
X5R16V10%
402
0.1uF
X5R16V10%0.1uF
402X5R16V10%
402
0.1uF
X5R16V10%
402
0.1uF
X5R16V10%
402
0.1uF
X5R16V10%
402
0.1uF
X5R16V10%
402
0.1uF
X5R16V10%
16V 402
0.1uF
X5R10%
402
0.1uF
X5R16V10%0.1uF
402X5R16V10%
402
0.1uF
X5R16V10%
402
0.1uF
X5R16V10%
402
0.1uF
X5R16V10%
402X5R16V10%
0.1uF
10% 402
0.1uF
X5R16V
402
0.1uF
X5R16V10%
16V 402X5R10%
0.1uF
402X5R16V10%
0.1uF
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
9 30
9 30
7 28
402
0.1uF
X5R16V10%
402
0.1uF
X5R16V10%
15 84
15 84
15 84
15 84
10% 16V X5R
0.1uF
4020.1uF
10% 16V X5R 402
15 84
15 84
10% 16V X5R
0.1uF
402
10% 16V X5R
0.1uF
402
15 84
NV G84M PCI-ESYNC_DATE=03/19/2007SYNC_MASTER=M75_MLB
68 92
A.0.0051-7261
PEG_R2D_C_P<1>
=PP1V2_GPU_PEX_IOVDD=PP1V2_GPU_PEX_IOVDDQ
PP1V2_GPU_PEX_PLLAVDD_FMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.2V
MIN_LINE_WIDTH=0.25 mm
VOLTAGE=1.2VMIN_NECK_WIDTH=0.25 mm
PP1V2_GPU_PEX_PLLDVDD_F
PEG_R2D_N<10>
PEG_R2D_P<11>PEG_R2D_N<11>
PEG_D2R_C_P<13>
PEG_R2D_C_N<11>
PEG_R2D_N<13> PEG_D2R_C_N<13>
PEG_R2D_C_P<12>
PEG_R2D_C_N<12>
PEG_CLK100M_GPU_NTP_GPU_PEXTSTCLK_P
PEG_D2R_C_N<15>PEG_D2R_C_P<15>
GPU_RESET_L
PEG_CLK100M_GPU_P
PEG_R2D_C_N<14>
PEG_R2D_C_P<15> PEG_R2D_P<15>
PEG_R2D_C_N<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<13>
PEG_R2D_C_P<11>
PEG_R2D_C_P<10>
PEG_R2D_C_N<10>
PEG_R2D_C_P<9>
PEG_R2D_C_N<9>
PEG_R2D_C_P<8>
PEG_R2D_C_N<8>
PEG_R2D_C_N<7>
PEG_R2D_C_N<6>
PEG_R2D_C_N<5>
PEG_R2D_C_P<6>
PEG_R2D_P<14>
PEG_R2D_P<13>
PEG_R2D_P<12>
PEG_R2D_P<10>
PEG_R2D_P<9>
PEG_R2D_P<8>
PEG_R2D_P<7>
PEG_R2D_P<6>
PEG_R2D_C_N<4>
PEG_R2D_C_P<5>
PEG_R2D_C_P<4>
PEG_R2D_C_P<3>
PEG_R2D_C_P<2>
PEG_R2D_C_N<2>
PEG_R2D_C_N<1>
PEG_R2D_C_P<0>
PEG_R2D_C_N<0>
PEG_R2D_P<4>
PEG_R2D_P<2>
PEG_R2D_P<1>
PEG_R2D_P<0>
PEG_R2D_N<14>
PEG_R2D_N<15>
PEG_R2D_N<12>
PEG_R2D_N<5>
PEG_R2D_N<9>
PEG_R2D_N<8>
PEG_R2D_N<7>
PEG_R2D_N<4>
PEG_R2D_N<1>
PEG_R2D_N<2>
PEG_R2D_N<3>
PEG_R2D_N<0>
PEG_D2R_C_N<14>
PEG_D2R_C_N<12>
PEG_D2R_C_N<10>
PEG_D2R_C_N<9>
PEG_D2R_C_N<7>
PEG_D2R_C_N<6>
PEG_D2R_C_N<5>
PEG_D2R_C_N<4>
PEG_D2R_C_N<3>
PEG_D2R_C_N<2>
PEG_D2R_C_N<1>
PEG_D2R_C_P<12>
PEG_D2R_C_P<11>
PEG_D2R_C_P<10>
PEG_D2R_C_P<9>
PEG_D2R_C_P<8>
PEG_D2R_C_P<6>
PEG_D2R_C_P<5>
PEG_D2R_C_P<4>
PEG_D2R_C_P<3>
PEG_D2R_C_P<2>
PEG_D2R_C_P<1>
PEG_D2R_C_N<0>PEG_D2R_C_P<0>
PEG_D2R_N<13>
PEG_D2R_N<15>
PEG_D2R_N<14>
PEG_D2R_P<15>
PEG_D2R_P<14>
PEG_D2R_P<12>
PEG_D2R_P<11>
PEG_D2R_N<11>
PEG_D2R_N<10>
PEG_D2R_N<9>
PEG_D2R_P<8>
PEG_D2R_N<7>
PEG_D2R_P<7>
PEG_D2R_P<6>
PEG_D2R_P<5>
PEG_D2R_P<4>
PEG_D2R_N<4>
PEG_D2R_P<3>
PEG_D2R_N<3>
PEG_D2R_P<2>
PEG_D2R_N<2>
PEG_D2R_P<1>
PEG_D2R_N<0>
PEG_D2R_P<0>
PEG_D2R_N<12>
PEG_D2R_N<1>
PEG_D2R_C_P<7>
PEG_D2R_N<6>
PEG_D2R_P<13>
PEG_D2R_P<10>
PEG_D2R_P<9>
PEG_D2R_N<8>
PEG_D2R_C_P<14>
PEG_D2R_N<5>
PEG_D2R_C_N<11>
PEG_D2R_C_N<8>
PEG_R2D_N<6>
PEG_R2D_C_P<7>
PEG_R2D_C_N<15>
=PP1V2_GPU_PEX_PLLXVDD
TP_GPU_PEXTSTCLK_N
PEG_R2D_C_N<3>
PEG_R2D_P<3>
PEG_R2D_P<5>
C8020 1 2
C8021 1 2
C8050 1 2
C8051 1 2
C8048 1 2
C8049 1 2
C8046 1 2
C8047 1 2
C8044 1 2
C8045 1 2
C8042 1 2
C8043 1 2
C8040 1 2
C8041 1 2
C8038 1 2
C8039 1 2
C8036 1 2
C8037 1 2
C8034 1 2
C8035 1 2
C8032 1 2
C8033 1 2
C8030 1 2
C8031 1 2
C8028 1 2
C8029 1 2
C8026 1 2
C8027 1 2
C8024 1 2
C8025 1 2
C8022 1 2
C8023 1 2
C8055 1 2
C8056 1 2
C8085 1 2
C8086 1 2
C8083 1 2
C8084 1 2
C8081 1 2
C8082 1 2
C8079 1 2
C8080 1 2
C8077 1 2
C8078 1 2
C8075 1 2
C8076 1 2
C8073 1 2
C8074 1 2
C8071 1 2
C8072 1 2
C8069 1 2
C8070 1 2
C8067 1 2
C8068 1 2
C8065 1 2
C8066 1 2
C8063 1 2
C8064 1 2
C8061 1 2
C8062 1 2
C8059 1 2
C8060 1 2
C8057 1 2
C8058 1 2
U8000
AH14
AJ14
AH15
AK13
AK14
AM14
AM15
AL23
AL24
AM24
AM25
AK25
AK26
AL26
AL27
AM27
AM28
AL28
AL29
AL15
AL16
AK16
AK17
AL17
AL18
AM18
AM19
AK19
AK20
AL20
AL21
AM21
AM22
AK22
AK23
AM12
AM11
AJ15
AK15
AH16
AG16
AG23
AH23
AK24
AJ24
AJ25
AH25
AH26
AG26
AK27
AJ27
AJ28
AH27
AG17
AH17
AG18
AH18
AK18
AJ18
AJ19
AH19
AG20
AH20
AG21
AH21
AK21
AJ21
AJ22
AH22
U8000
A26
M5
U6
V1
V3
V4
V5
V6
W1
W3
W4
A28
W5
Y5
Y6
AC26
AD26
AE26
AG12
AH13
AH31
AH32
B32
AM8
AM9
D1
D31
D32
F1
F6
G8
AD23
AF23
AF24
AF25
AG24
AG25
AC16
AF21
AF22
AC17
AC21
AC22
AE18
AE21
AE22
AF12
AF18
AF15
AE15
AE16
C80011
2
C80031
2
C80041
2
C80051
2
C80161
2
C8015 1
2
C80001
2
C80021
2
C80061
2
C80071
2
C80081
2
C80091
2
C80101
2
C80111
2
C80171
2
C80131
2
C80141
2
C8012 1
2
L8015
1 2
L8012
1 2
8
8
84
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84 84
84
84 84
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84
84
84
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Page 69
FBVTT
FBVDDQ
GND_SENSE
VDD_SENSE
VDD_LP
VDD
FBVDD
GND GND
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
???A @ ???MHz 1.8V GDDR3
Page NotesPower aliases required by this page:
Signal aliases required by this page:
(NONE)BOM options provided by this page:
(NONE)
- =PP1V8_GPU_FBVDDQ- =PPVCORE_GPU
???A @ ???/???MHz Core/Mem Clk for VDD
CERM6.3V
1UF10%
402CERM6.3V
1UF10%
402
OMIT
(7 OF 8)BGA
NB8P-GS-W-A2
OMIT
BGA(8 OF 8)
NB8P-GS-W-A2
CERM6.3V
1UF10%
402
0.1UF20%10V
402CERM
20%
CERM402
0.1UF10V
20%10V
402CERM
0.1UF
10V
0.1UF20%
CERM402
10V
0.1UF20%
402CERM
20%10VCERM
0.1UF
402
20%
402CERM
0.1UF10V
20%10VCERM402
0.1UF20%10V
402CERM
0.1UF
10V
0.1UF
CERM402
20%
20%10VCERM402
0.1UF
20%10V
402CERM
0.1UF20%10VCERM402
0.1UF
20%10V
402CERM
0.1UF
10VCERM
0.1UF20%
402
402CERM-X5R
10%6.3V
0.47UF
402
0.47UF6.3V10%
CERM-X5R
CERM402
10V20%
0.1UF
4.7UF
603
20%6.3VCERM
CERM402
10V20%
0.1UF
CERM402
0.1UF20%10V
CERM402
0.1UF20%10V
4.7UF
603
20%6.3VCERM
CERM402
10V20%
0.1UF
402CERM
0.1UF20%10V
CERM402
0.1UF20%10V
CERM402
10V20%
0.1UF
0.1UF
402CERM
20%10V
CERM402
20%10V
0.1UF
402CERM
20%10V
0.1UF
402CERM10V
0.1UF20%
CERM402
20%10V
0.1UF
402CERM-X5R
10%6.3V
0.47UF
402
0.47UF6.3V10%
CERM-X5R
CERM-X5R
10%6.3V
0.47UF
402CERM-X5R
10%6.3V
0.47UF
402CERM-X5R
10%6.3V
0.47UF
402CERM-X5R
10%6.3V
0.47UF
402
SYNC_DATE=03/19/2007
A.0.0051-7261
9269
NV G84M Core/FB PowerSYNC_MASTER=M75_MLB
=PP1V8_GPU_FBVDDQ
=PPVCORE_GPU
TP_GPU_VDD_SENSETP_GPU_GND_SENSE
C81011
2
C81001
2
U8000
A12
A9
AA32
AD32
AG32
AK32
C32
F32
J32
M32
R32
A18
A21
A24
A27
A3
A30
A6
AA25
G22
H11
H12
H15
H18
H21
H22
L25
L26
M25
AA26
M26
R25
R26
V25
V26
AB25
AB26
G11
G12
G15
G18
G21
AA23
K12
K21
K22
K24
K9
L23
M23
T25
U25
AB23
H16
H17
J10
J23
J24
J9
K11
M21
K16
P16
P17
P19
R16
R17
T13
T14
T15
T18
T19
K17
U13
U14
U15
U18
U19
V16
V17
W13
W14
W16
N13
W17
W19
Y13
Y14
Y16
Y17
Y19
Y20
N14
N16
N17
N19
P13
P14
P20
T20
T23
U20
U23
W20
N20
U8000
AE17
AG11
J16
J17
J2
J31
K10
K23
K29
K4
L27
L6
AB27
M12
M2
M31
N15
N18
N29
N4
P15
P18
P27
AB6
P6
R13
R14
R15
R18
R19
R2
R20
R31
T16
AC10
T17
T24
T29
T4
U16
U17
U24
U29
U8
V13
AC23
V14
V15
V18
V19
V2
V20
V31
W15
W18
W27
AC29
W6
Y15
Y18
Y29
Y4
AC4
AD16
AD17
AD2
AE27
AD31
AA12
AA2
AA21
AA31
AG13
AG14
AG15
AG19
AG2
AE6
AG22
AG31
AG8
AH24
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AF11
AJ26
AJ29
AJ4
AJ7
AK2
AK28
AK31
AL10
AL11
AL14
AF26
AL19
AL22
AL25
AL3
AL6
AL9
AM10
AM13
AM16
AM17
AF29
AM20
AM23
AM26
AM29
B12
B15
B18
B21
B24
B27
AF4
B3
B30
B6
B9
C2
C31
D10
D13
D16
D17
AF7
D20
D23
D26
D29
D4
D7
F11
F14
F19
F2
AG10
F22
F25
F31
F8
G26
G29
G4
G7
H27
H6
C81021
2
C81071
2
C81121
2
C81171
2
C81061
2
C81051
2
C81101
2
C81111
2
C81161
2
C81151
2
C81041
2
C81091
2
C81141
2
C81131
2
C81081
2
C81031
2
C8160 1
2
C8166 1
2
C8159 1
2
C8151 1
2
C8158 1
2
C8165 1
2
C8164 1
2
C8150 1
2
C8157 1
2
C8163 1
2
C8162 1
2
C8156 1
2
C81221
2
C81211
2
C81201
2
C81191
2
C81181
2
C8161 1
2
C8167 1
2
C8169 1
2
C8168 1
2
C8171 1
2
C8170 1
2
8
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Page 70
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
FBAD20
FBAD22
FBAD1
FBAD2
FBAD18
FBAD0
FBAD3
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD19
FBAD21
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD29
FBAD30
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
FBA_PLLAVDD
FBA_PLLGND
FBAD31
FBCAL_PD_VDDQ
FBCAL_PU_GND
FBAD28
FBAD4
FBADQS_WP0
FBADQS_WP1
FBADQS_WP3
FBADQS_WP2
FBADQS_WP6
FBADQS_WP5
FBADQS_WP4
FBADQS_WP7
FBA_DEBUG
FBADQS_RN2
FBADQS_RN1
FBADQS_RN0
FBADQS_RN4
FBADQS_RN3
FBADQS_RN5
FBADQS_RN7
FBADQS_RN6
FBA_CLK0
FBA_CLK0_L
FBA_CLK1_L
FBA_CLK1
FBADQM1
FBADQM0
FBADQM3
FBADQM2
FBADQM6
FBADQM5
FBADQM4
FBADQM7
FBA_CMD0
FBA_CMD2
FBA_CMD1
FBA_CMD5
FBA_CMD3
FBA_CMD4
FBA_CMD7
FBA_CMD6
FBA_CMD8
FBA_CMD10
FBA_CMD9
FBA_CMD13
FBA_CMD12
FBA_CMD11
FBA_CMD15
FBA_CMD14
FBA_CMD18
FBA_CMD17
FBA_CMD16
FBA_CMD20
FBA_CMD19
FBA_CMD23
FBA_CMD22
FBA_CMD21
FBA_CMD25
FBA_CMD24
FBA_CMD28
FBA_CMD26
FBA_CMD27
READ STROBE
WRITE STROBE
MEMORY INTERFACE A
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
FB_VREF
FBCAL_TERM_GND
FBC_PLLGND
FBC_PLLAVDD
FBCD63
FBCD62
FBCD61
FBCD60
FBCD59
FBCD58
FBCD57
FBCD56
FBCD55
FBCD53
FBCD51
FBCD50
FBCD49
FBCD48
FBCD47
FBCD46
FBCD45
FBCD44
FBCD43
FBCD41
FBCD40
FBCD39
FBCD38
FBCD37
FBCD36
FBCD35
FBCD34
FBCD33
FBCD32
FBCD31
FBCD30
FBCD29
FBCD28
FBCD27
FBCD26
FBCD25
FBCD24
FBCD23
FBCD22
FBCD21
FBCD20
FBCD19
FBCD18
FBCD17
FBCD16
FBCD15
FBCD11
FBCD9
FBCD8
FBCD7
FBCD6
FBCD5
FBCD4
FBCD3
FBCD2
FBCD1
FBCD10
FBCD42
FBCD0
FBCD54
FBCD52
FBCD13
FBCD12
FBCD14
FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3
FBCDQS_RN4
FBCDQS_RN5
FBCDQS_RN6
FBCDQS_RN7
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_WP0
FBCDQS_WP4
FBCDQS_WP3
FBCDQS_WP6
FBCDQS_WP7
FBCDQS_WP5
FBC_DEBUG
FBCDQM7
FBC_CLK1
FBC_CLK0
FBC_CLK0_L
FBC_CLK1_L
FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBC_CMD4
FBC_CMD3
FBC_CMD6
FBC_CMD5
FBC_CMD9
FBC_CMD8
FBC_CMD7
FBC_CMD11
FBC_CMD10
FBC_CMD14
FBC_CMD13
FBC_CMD12
FBC_CMD16
FBC_CMD15
FBC_CMD19
FBC_CMD18
FBC_CMD17
FBC_CMD21
FBC_CMD20
FBC_CMD22
FBC_CMD24
FBC_CMD23
FBC_CMD27
FBC_CMD26
FBC_CMD25
FBC_CMD28
FBC_CMD1
FBC_CMD0
FBC_CMD2
MEMORY INTERFACE B
WRITE STROBE
READ STROBE
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
G
D
SIN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Page Notes
BOM options provided by this page:
Signal aliases required by this page:
Power aliases required by this page:
- =PP1V8_GPU_FBIO
(NONE)
(NONE)
- =PP1V2_GPU_FBPLLAVDD
NCNC
71 90
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74
71 90
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(3 OF 8)
OMIT
BGANB8P-GS-W-A2
20%0.1UF10VCERM402
71 90
74
71 90
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74
72 90
72 90
72 90
72 90
72 90
72 90
72 90
72 90
72 90
72 90
72 90
74
5%1/16WMF-LF402
10K
72 90
5%1/16WMF-LF402
10K
40.2
402
1%
MF-LF1/16W
1%
MF-LF402
1/16W
24.9
OMIT
(4 OF 8)BGA
NB8P-GS-W-A2
16V
0.1uF10%
X5R402
1.07K
MF-LF402
1/16W1%
0402
FERR-220-OHM
402
1%
MF-LF1/16W
45.3
4.7UF20%
603CERM6.3V
402
5%1/16WMF-LF
10K5%1/16WMF-LF402
10K
71 90
71 90
71 90
71 90
71 90
71 90
71 90
71 90
71 90
71 90
71 90
71 90
71 90
71 90
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72 90
72 90
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72 90
72 90
72 90
72 90
72 90
72 90
72 90
72 90
72 90
72 90
2N7002DW-X-FSOT-363
402MF-LF1/16W
1%2.49K
402MF-LF1/16W
1%1.02K
71 72 74 SYNC_MASTER=M75_MLB
NV G84M Frame Buffer I/FSYNC_DATE=03/19/2007
70 92
051-7261 A.0.0
=PP1V2_GPU_FBPLLAVDD
VOLTAGE=1.2V
PP1V2_GPU_FBA_PLL_FMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
FB_A_DQ<3>
FB_A_DQ<6>
FB_A_DQ<9>
FB_A_DQ<23>
FB_A_DQ<27>
FB_A_DQ<24>
FB_A_DQ<22>
FB_B_DRAM_RST
FB_B_CKEFB_B_MA<0>FB_B_MA<9>
FB_B_DQ<48>FB_B_DQ<47>
FB_A_MA<6>
FB_A_MA<1>
FB_A_MA<8>FB_A_LMA<3>
FB_B_DQ<53>
FBCAL_TERM_GND
TP_FB_A_MA12
FB_A_BA<0>
FB_A_CAS_L
FB_A_DRAM_RST
FB_A_WE_L
FB_A_UMA<5>
FB_A_MA<7>FB_A_MA<10>
FB_A_LMA<4>
FB_B_DQ<55>
FB_B_DQ<51>
FB_B_DQ<43>
FB_A_UMA<2>
FB_B_CS0_L
FB_B_UMA<3>
FB_B_BA<0>
FB_A_UMA<4>
FB_B_DQ<21>FB_B_DQ<20>
FB_B_DQ<18>FB_B_DQ<17>
FB_A_BA<1>FB_A_LMA<5>FB_A_RAS_L
FB_A_UMA<3>
FB_A_MA<11>
FB_A_MA<0>
TP_FB_A_MA13
FB_A_LMA<2>
FB_A_MA<9>
TP_FB_B_MA13FB_B_MA<1>FB_B_LMA<3>FB_B_MA<8>FB_B_LMA<2>FB_B_MA<6>
FB_B_MA<10>FB_B_MA<7>
TP_FB_B_MA12FB_B_UMA<5>
FB_B_WE_LFB_B_CAS_LFB_B_MA<11>
FB_B_LMA<5>FB_B_RAS_L
FB_B_DQ<61>
FB_B_DQ<59>FB_B_DQ<58>FB_B_DQ<57>
FB_B_DQ<50>FB_B_DQ<49>
FB_B_DQ<46>FB_B_DQ<45>FB_B_DQ<44>
FB_B_DQ<41>FB_B_DQ<40>FB_B_DQ<39>FB_B_DQ<38>FB_B_DQ<37>FB_B_DQ<36>FB_B_DQ<35>FB_B_DQ<34>FB_B_DQ<33>
FB_B_DQ<30>FB_B_DQ<29>FB_B_DQ<28>FB_B_DQ<27>FB_B_DQ<26>FB_B_DQ<25>FB_B_DQ<24>FB_B_DQ<23>FB_B_DQ<22>
FB_B_DQ<19>
FB_B_DQ<16>FB_B_DQ<15>
FB_B_DQ<11>
FB_B_DQ<9>FB_B_DQ<8>FB_B_DQ<7>FB_B_DQ<6>FB_B_DQ<5>FB_B_DQ<4>FB_B_DQ<3>FB_B_DQ<2>FB_B_DQ<1>
FB_B_DQ<10>
FB_B_LMA<4>
FB_B_DQ<42>
FB_B_BA<1>
FB_B_DQ<0>
FB_B_BA<2>
FB_B_UMA<4>FB_B_UMA<2>
FB_B_DQ<54>
FB_B_DQ<13>FB_B_DQ<12>
FB_B_DQ<14>
FB_B_DQ<60>
FB_B_DQ<52>
FB_B_DQ<56>
FB_B_DQ<62>
FB_A_DQ<0>
FB_A_DQ<12>FB_A_DQ<11>FB_A_DQ<10>
FB_A_DQ<8>FB_A_DQ<7>
FB_A_DQ<4>
FB_A_DQ<21>FB_A_DQ<20>FB_A_DQ<19>FB_A_DQ<18>FB_A_DQ<17>FB_A_DQ<16>FB_A_DQ<15>FB_A_DQ<14>FB_A_DQ<13>
FB_A_DQ<32>FB_A_DQ<31>FB_A_DQ<30>FB_A_DQ<29>FB_A_DQ<28>
FB_A_DQ<26>FB_A_DQ<25>
FB_A_DQ<33>
FB_A_DQ<43>FB_A_DQ<42>FB_A_DQ<41>FB_A_DQ<40>FB_A_DQ<39>FB_A_DQ<38>FB_A_DQ<37>FB_A_DQ<36>
FB_A_DQ<34>
FB_A_DQ<53>FB_A_DQ<52>FB_A_DQ<51>FB_A_DQ<50>FB_A_DQ<49>FB_A_DQ<48>FB_A_DQ<47>FB_A_DQ<46>FB_A_DQ<45>FB_A_DQ<44>
FB_A_DQ<62>FB_A_DQ<61>FB_A_DQ<60>FB_A_DQ<59>FB_A_DQ<58>FB_A_DQ<57>FB_A_DQ<56>FB_A_DQ<55>FB_A_DQ<54>
FB_A_DQ<63> FB_B_DQ<63>
FB_A_DQ<1>FB_A_DQ<2>
FB_A_CS0_LFB_A_BA<2>
FB_A_DQ<5>
FB_A_CKE
FBCAL_PD_VDDQ
TP_FBA_DEBUG
FBCAL_PU_GND
FB_A_DQM_L<0>FB_A_DQM_L<1>FB_A_DQM_L<2>FB_A_DQM_L<3>FB_A_DQM_L<4>FB_A_DQM_L<5>FB_A_DQM_L<6>FB_A_DQM_L<7>
FB_A_RDQS<0>FB_A_RDQS<1>FB_A_RDQS<2>FB_A_RDQS<3>FB_A_RDQS<4>FB_A_RDQS<5>FB_A_RDQS<6>FB_A_RDQS<7>
FB_A_WDQS<0>FB_A_WDQS<1>FB_A_WDQS<2>FB_A_WDQS<3>FB_A_WDQS<4>FB_A_WDQS<5>FB_A_WDQS<6>FB_A_WDQS<7>
FB_A_CLK_P<0>FB_A_CLK_N<0>
TP_FBA_CMD27TP_FBA_CMD28
FB_A_CLK_P<1>FB_A_CLK_N<1>
FB_A_DQ<35>
=PP1V8_GPU_FBIO
TP_FBC_DEBUG
FB_B_CLK_P<1>
FB_B_CLK_P<0>FB_B_CLK_N<0>
FB_B_DQM_L<0>FB_B_DQM_L<1>FB_B_DQM_L<2>
FB_B_CLK_N<1>
FB_B_DQM_L<3>
FB_B_DQM_L<5>FB_B_DQM_L<6>FB_B_DQM_L<7>
FB_B_DQM_L<4>
FB_B_RDQS<4>FB_B_RDQS<3>FB_B_RDQS<2>FB_B_RDQS<1>FB_B_RDQS<0>
FB_B_WDQS<0>
FB_B_RDQS<7>FB_B_RDQS<6>FB_B_RDQS<5>
FB_B_WDQS<5>
FB_B_WDQS<3>FB_B_WDQS<4>
FB_B_WDQS<2>FB_B_WDQS<1>
FB_B_WDQS<6>
TP_FBC_CMD27TP_FBC_CMD28
FB_B_DQ<31>FB_B_DQ<32>
FB_B_WDQS<7>
=PP1V8_GPU_FBIO
GPU_FB_VREF
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmGPU_FB_VREF_UNTERM_L
FB_VREF_UNTERM
U8000
P28
R28
Y27
AA27
P32
U27
T31
U32
W29
W30
T27
V28
V30
U31
R27
V29
P31
T30
W28
R29
R30
P29
U28
Y32
Y30
V32
U30
Y31
W32
W31
T32
V27
T28
AC27
G25
G24
N27
M27
N30
N32
L31
L30
J30
L32
H30
K30
H31
F30
N28
H32
E31
D30
E30
H28
H29
E29
J27
F27
E27
L29
E28
F28
AD29
AE29
AD28
AC28
AB29
AA30
Y28
AB30
K27
AM30
AF30
AJ31
AJ30
AJ32
AK29
AM31
AL30
AE32
AE30
K28
AE31
AD30
AC31
AC32
AB32
AB31
AG27
AF28
AH28
AG28
J29
AG29
AD27
AF27
AE28
J28
P30
N31
M29
M30
G30
F29
AA29
AK30
AC30
AG30
M28
K32
G31
G27
AA28
AL31
AF31
AH29
L28
K31
G32
G28
AB28
AL32
AF32
AH30
K26
H26
C82011
2
R82001
2
R82501
2
R829212
R82911
2
U8000
E32
E13
F13
F18
E17
C13
A16
C15
B16
F17
C19
D15
C17
A17
C16
D14
F16
A13
C14
C18
E14
B13
E15
F15
A20
C20
A15
B17
B20
A19
B19
B14
E16
A14
F12
G10
G9
J26
B7
A7
D12
D9
E12
D11
E8
D8
E7
F7
D6
D5
C7
D3
E4
C3
B4
C10
B10
C8
A10
C11
C12
A2
A11
B11
B28
C27
C26
B26
C30
B31
C29
A31
B2
D28
D27
F26
D24
E23
E26
E24
F23
B23
A23
C4
C25
C23
A22
C22
C21
B22
E22
D22
D21
E21
A5
E18
D19
D18
E19
B5
F9
F10
A4
E11
F5
C9
C28
F24
C24
E20
C6
E9
E6
A8
B29
E25
A25
F21
C5
E10
E5
B8
A29
D25
B25
F20
C8296 1
2
R82951
2
L8200
1 2
R829012
C8200 1
2
R82011
2
R82511
2
Q82953
5
4
R82961
2
R82971
2
70
70
8
74
74
8
74
74
8
Page 71
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
BI
BI
IN
IN
G
D
S G
D
SIN IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
BOM options provided by this page:
Signal aliases required by this page:
Power aliases required by this page:
Page Notes
Connect to designated pin, then GND
NCNC
- =PP1V8_S0_FB_VDDQ- =PP1V8_S0_FB_VDD
(NONE)
(NONE)
U8400.J1 U8400.J12 U8400.J1 U8400.J12
NCNC
Connect to designated pin, then GND
2.37K
MF-LF402
1%1/16W
5.49K
MF-LF
1%1/16W
402
16V10%
402X5R
0.1uF0.1uF16V10%
402X5R
16V10%
402X5R
0.1uF16V10%
X5R
0.1uF
402
0.1uF
X5R
10%16V
402
0.1uF
402
10%16VX5R X5R
402
10%16V
0.1uF16V10%
402X5R
0.1uF 0.1uF16V10%
402X5R
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
FBGA
OMITCRITICAL
FBGA
K4J52324QC-BC20
16MX32-GDDR3-500MHZ
CRITICALOMIT
1001/16W5%
402MF-LF
1/16W1%
402MF-LF
243
1211/16W1%
402MF-LF
1/16W1%
402MF-LF
121
402
10%0.0047uF25VCERM
402X5R
10%16V
0.1uF
16V10%
402X5R
0.1uF10%16V
402X5R
0.1uF
5%1K
MF-LF402
1/16W
1/16W
402MF-LF
1%121
1%121
MF-LF402
1/16W
1/16W
402
1211%
MF-LF
1%121
MF-LF402
1/16W
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 71 90
70 71 90
70 71 90
70 71 90
70 71 90
70 71 90
70 71 90
70 71 90
70 71 90
70 90
70 90
70 71 90
70 71 90
70 71 90
70 71 90
70 71 90
70 71 90
70 71 90
70 90
70 90
70 90
70 90
70 71 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 71 90
70 71 90
70 71 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 71 90
70 71 90
70 71 90
70 71 90
70 71 90
70 90
70 71 90
70 90
70 71 90
70 71 90
70 71 90
70 71 90
70 71 90
70 71 90
70 90
70 90
70 90
70 90
70 71 90
70 71 90
MF-LF402
1/16W
1K5% 1%
121
MF-LF402
1/16W
10%0.1uF
X5R402
16V
0.1uF
X5R402
10%16V
243
MF-LF402
1%1/16W
100
MF-LF402
5%1/16W
OMIT
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
FBGA
CRITICAL1/16W
402MF-LF
1211%
MF-LF402
1%1/16W
121
1%121
MF-LF402
1/16W
1%
MF-LF402
1/16W
121
MF-LF402
1%1/16W
121
0.1uF
X5R402
10%16V
0.1uF
X5R402
10%16V
0.1uF
X5R402
10%16V
FBGA
K4J52324QC-BC20
16MX32-GDDR3-500MHZ
OMITCRITICAL
0.1uF
X5R402
10%16V
X5R
0.1uF
402
10%16V
402
0.1uF
X5R
10%16V
0.1uF
X5R402
10%16V
0.1uF
X5R402
10%16V
0.1uF
X5R402
10%16V
0.1uF
X5R402
10%16V
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
6.3V20%
805CERM-X5R
22UF
22UF
805
6.3V20%
CERM-X5R
CERM-X5R
22UF
805
6.3V20%
CERM-X5R
22UF6.3V20%
805
CERM
0.01UF
402
10%16V
CERM
0.01UF
402
10%16V
402MF-LF
1%1/16W
2.21K
2N7002DW-X-FSOT-363
10%
402
0.0047uF25VCERM
SOT-3632N7002DW-X-F
CERM25V
0.0047uF10%
402402MF-LF
1%1/16W
2.21K
1/16W1%
402MF-LF
2.37K
402
1/16W1%
MF-LF
5.49K
70 71 72 74
70 71 72 74
CERM25V
0.0047uF
402
10%
SYNC_DATE=04/02/2007SYNC_MASTER=M75_MLB
GDDR3 Frame Buffer A
71
A.0.0051-7261
92
FB_A0_MF
FB_A_LMA<5>
FB_A_MA<0>
=PP1V8_GPU_FB_VDD
FB_A_RDQS<6>FB_A_RDQS<4>
=PP1V8_GPU_FB_VDDQ
FB_A1_VREF_UNTERM_LMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
FB_A_UMA<4>
FB_A_UMA<2>
FB_A_CLK_P<1>
FB_A1_MF
FB_A_LMA<4>
FB_A_CLK_P<0>
FB_A_LMA<2>
FB_A_MA<6>
FB_A_BA<2>
FB_A_DQ<28>
FB_A_DQ<0>
FB_A_MA<11>
FB_A_CS0_L
FB_A_CAS_LFB_A_RAS_L
FB_A1_ZQ
FB_A_MA<8>
FB_A_MA<11>
FB_A_RDQS<2>
FB_A_MA<10>
FB_A_MA<8>
FB_A_DQM_L<7>FB_A_DQM_L<5>FB_A_DQM_L<6>FB_A_DQM_L<4>
FB_A_BA<1>FB_A_BA<0>
FB_A_WDQS<4>
FB_A_WDQS<7>FB_A_WDQS<5>FB_A_WDQS<6>
FB_A_MA<1>
FB_A_MA<7>FB_A_MA<6>
FB_A_MA<9>
FB_A_DRAM_RSTFB_A1_SEN
FB_A_RDQS<7>FB_A_RDQS<5>
FB_A_DQ<38>FB_A_DQ<39>FB_A_DQ<37>
FB_A_DQ<35>FB_A_DQ<33>
FB_A_DQ<54>
FB_A_DQ<34>
FB_A_DQ<48>FB_A_DQ<50>FB_A_DQ<43>FB_A_DQ<41>FB_A_DQ<44>
FB_A_DQ<61>
FB_A_DQ<59>
FB_A_DQ<62>
FB_A_MA<10>
FB_A_DQM_L<0>
FB_A_DQM_L<2>FB_A_DQM_L<3>
FB_A_BA<1>
FB_A_DQ<30>FB_A_DQ<29>
FB_A_DQ<31>FB_A_DQ<26>
FB_A_DQ<24>
FB_A_DQ<27>
FB_A_DQ<22>FB_A_DQ<23>FB_A_DQ<25>
FB_A_DQ<19>FB_A_DQ<21>FB_A_DQ<20>FB_A_DQ<16>FB_A_DQ<18>FB_A_DQ<17>FB_A_DQ<13>FB_A_DQ<14>FB_A_DQ<15>FB_A_DQ<12>FB_A_DQ<11>FB_A_DQ<10>FB_A_DQ<9>
FB_A_DQ<6>FB_A_DQ<8>
FB_A_DQ<5>
FB_A_DQ<3>FB_A_DQ<7>
FB_A_DQ<2>
FB_A_DQ<1>FB_A_DQ<4>
FB_A_BA<2>
FB_A_DQM_L<1>
FB_A_RDQS<3>
FB_A_RDQS<1>FB_A_RDQS<0>
FB_A_DQ<56>FB_A_DQ<58>
FB_A_DQ<57>FB_A_DQ<63>FB_A_DQ<60>
FB_A_DQ<40>FB_A_DQ<47>FB_A_DQ<46>FB_A_DQ<45>FB_A_DQ<42>
FB_A_RAS_L
FB_A_CKE
FB_A_WE_L
FB_A_CKE
FB_A_CLK_N<1>
FB_A_UMA<5>
=PP1V8_GPU_FB_VDD
FB_A0_SEN
FB_A_BA<0>
FB_A_WDQS<3>FB_A_WDQS<2>FB_A_WDQS<1>FB_A_WDQS<0>
FB_A_CAS_LFB_A_WE_LFB_A_CS0_L
FB_A_DQ<52>FB_A_DQ<51>FB_A_DQ<55>FB_A_DQ<49>
FB_A_DQ<53>
FB_A_DQ<36>FB_A_DQ<32>
FB_A_DRAM_RST
FB_A0_ZQ
FB_A_CLK_N<0>
FB_A_MA<9>
FB_A_MA<7>
FB_A_LMA<3>
FB_A_MA<1>
=PP1V8_GPU_FB_VDDQ
FB_A_CLK0_TERMMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
FB_A0_VREF_UNTERM_L
FB_VREF_UNTERM
FB_A_CLK1_TERM
FB_VREF_UNTERM
FB_A_UMA<3>
FB_A_MA<0>
FB_A0_VREFMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
FB_A1_VREF
C84311
2
R84301
2
R84311
2
C84031
2
C84021
2
C84041
2
C84011
2
C84221
2
C84231
2
C84241
2
C84251
2
C84261
2
U8400K9
H11
K11
L9
K10
M9
K4
H2
K3
L4
K2
M4
G9
G4
H3
F9
J11
J10
H9
F4
E3
E10
N10
N3
B2
B3
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
C2
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
C3
T2
T3
E2
F3
F2
G3
B11
B10
A9
H10
D3
D10
P10
P3
V9
J2
J3
V4
D2
D11
P11
P2
H4
A4
U8400A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
C1
V1
V12
C4
C9
C12
E1
E4
E9
E12
H1
H12
A3
A10
G1
G12
L1
L12
V3
V10
J1
J12
B1
B4
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
B9
B12
D1
D4
D9
D12
G2
G11
R84491
2
R84481
2
R84451
2
R84461
2
C84331
2
C84211
2
C84151
2
C84101
2
R84401
2
R84471
2
R84441
2
R84431
2
R84421
2
R84901
2
R84921
2
C84711
2
C84721
2
R84981
2
R84991
2
U8450K9
H11
K11
L9
K10
M9
K4
H2
K3
L4
K2
M4
G9
G4
H3
F9
J11
J10
H9
F4
E3
E10
N10
N3
B2
B3
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
C2
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
C3
T2
T3
E2
F3
F2
G3
B11
B10
A9
H10
D3
D10
P10
P3
V9
J2
J3
V4
D2
D11
P11
P2
H4
A4
R84931
2
R84951
2
R84941
2
R84971
2
R84961
2
C84731
2
C84741
2
C84751
2
U8450A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
C1
V1
V12
C4
C9
C12
E1
E4
E9
E12
H1
H12
A3
A10
G1
G12
L1
L12
V3
V10
J1
J12
B1
B4
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
B9
B12
D1
D4
D9
D12
G2
G11C84761
2
C84511
2
C84521
2
C84601
2
C84531
2
C84651
2
C84541
2
C8400 1
2
C8420 1
2
C8450 1
2
C8470 1
2
C8446 1
2
C8496 1
2
R84321
2
Q84003
5
4
C84831
2
Q84006
2
1
C84811
2
R84821
2
R84801
2
R84811
2
72
72
72
72
71
71
71
71
8
8
8
8
Page 72
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
BI
BI
IN
IN
G
D
S G
D
SIN IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
U8500.J12U8500.J1U8500.J12U8500.J1Connect to designated pin, then GND
NCNCNC
NC
- =PP1V8_S0_FB_VDDQ- =PP1V8_S0_FB_VDD
(NONE)
(NONE)Signal aliases required by this page:
BOM options provided by this page:
Power aliases required by this page:
Page Notes
Connect to designated pin, then GND
402
0.1uF
X5R
10%16V
0.1uF
X5R402
10%16V
0.1uF
X5R402
10%16V
0.1uF
X5R
10%16V
402
0.1uF
X5R402
10%16V
0.1uF
X5R402
10%16V
0.1uF
X5R402
10%16V
0.1uF
X5R402
10%16V 16V
402
0.1uF
X5R
10%
CRITICALOMIT
FBGA
K4J52324QC-BC20
16MX32-GDDR3-500MHZ
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
FBGA
OMITCRITICAL
100
MF-LF402
5%1/16W
243
MF-LF402
1%1/16W
402
0.1uF
X5R
10%16V
0.1uF
X5R402
10%16V
0.1uF
X5R402
10%16V
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 72 90
70 72 90
70 72 90
70 72 90
70 72 90
70 72 90
70 72 90
70 72 90
70 72 90
70 90
70 90
70 72 90
70 72 90
70 72 90
70 72 90
70 72 90
70 72 90
70 72 90
70 90
70 90
70 90
70 90
70 72 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 72 90
70 72 90
70 72 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 72 90
70 72 90
70 72 90
70 72 90
70 72 90
70 90
70 72 90
70 90
70 72 90
70 72 90
70 72 90
70 72 90
70 72 90
70 72 90
70 90
70 90
70 90
70 90
70 72 90
70 72 90
0.1uF16V10%
402X5R
0.1uF16V10%
402X5R
1%243
MF-LF402
1/16W
1005%
MF-LF402
1/16W
FBGA
CRITICALOMIT
K4J52324QC-BC20
16MX32-GDDR3-500MHZ
0.1uF16VX5R402
10%0.1uF
X5R402
10%16V
0.1uF16V10%
402X5R
16MX32-GDDR3-500MHZ
FBGA
CRITICALOMIT
K4J52324QC-BC20
0.1uF16V10%
402X5R
16V10%
402X5R
0.1uF16V10%
402X5R
0.1uF
0.1uF
X5R402
10%16V
0.1uF
X5R402
10%16V
0.1uF
X5R402
10%16V
16V10%
402X5R
0.1uF
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
70 90
CERM-X5R
22UF
805
6.3V20%
22UF
805
6.3V20%
CERM-X5R
22UF
805
6.3V20%
CERM-X5R
805
6.3V20%
22UF
CERM-X5R
MF-LF1/16W
402
1%121
1/16W
402MF-LF
1%121
402MF-LF
1%121
1/16W
1211/16W1%
402MF-LF
1/16W1%
121
MF-LF402
1K1/16W
402MF-LF
5%
1/16W
402
1211%
MF-LF
1/16W1%
402MF-LF
121
1/16W
402MF-LF
1%121
1/16W1%121
402MF-LF
1/16W
402MF-LF
1211%
1/16W
402MF-LF
1211%
1211%
MF-LF402
1/16W
5%1K
1/16W
402MF-LF CERM
0.01UF
402
10%16V16V
10%
402CERM
0.01UF
402
1/16W1%
MF-LF
5.49K
402MF-LF
1%1/16W
2.21K
CERM25V
0.0047uF10%
402
10%
402
0.0047uF25VCERM
SOT-3632N7002DW-X-F
1/16W1%
402MF-LF
2.37K
5.49K
MF-LF
1%1/16W
402
1/16W1%
MF-LF402
2.21K
2.37K
MF-LF402
1%1/16W
CERM25V
0.0047uF
402
10%
402
10%0.0047uF25VCERM
2N7002DW-X-FSOT-363
70 71 72 74
70 71 72 74
SYNC_DATE=04/02/2007SYNC_MASTER=M75_MLB
051-7261 A.0.0
9272
GDDR3 Frame Buffer B
=PP1V8_GPU_FB_VDDQ
FB_VREF_UNTERMFB_VREF_UNTERM
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmFB_B0_VREF_UNTERM_L
FB_B_CLK0_TERM
=PP1V8_GPU_FB_VDD =PP1V8_GPU_FB_VDD
FB_B1_MFFB_B0_MF
FB_B_RAS_L
FB_B_DRAM_RST
FB_B_RDQS<2>
FB_B_UMA<2>FB_B_LMA<3>FB_B_LMA<2>
FB_B_LMA<4>FB_B_LMA<5>
FB_B_RAS_LFB_B_CAS_LFB_B_WE_LFB_B_CS0_L
FB_B_CKE
FB_B_CAS_L
FB_B1_SEN
FB_B_DQ<35>
FB_B_RDQS<5>
FB_B_BA<2>FB_B_BA<2>
FB_B_DQM_L<6>
FB_B_DQM_L<7>
FB_B_BA<1>FB_B_BA<0>
FB_B_WDQS<7>
FB_B_WDQS<6>FB_B_WDQS<5>
FB_B_DRAM_RST
FB_B_RDQS<6>
FB_B_RDQS<7>
FB_B_DQ<57>
FB_B_DQ<62>FB_B_DQ<59>FB_B_DQ<61>
FB_B_DQ<33>FB_B_DQ<63>
FB_B_DQ<32>FB_B_DQ<34>FB_B_DQ<38>FB_B_DQ<37>
FB_B_DQ<47>FB_B_DQ<46>FB_B_DQ<43>
FB_B_DQ<41>FB_B_DQ<42>
FB_B_DQ<52>
FB_B_DQ<54>FB_B_DQ<55>
FB_B_DQ<51>FB_B_DQ<48>
FB_B_DQ<49>FB_B_DQ<50>
FB_B_MA<8>
FB_B_DQM_L<2>FB_B_DQM_L<1>
FB_B_WDQS<0>
FB_B_WDQS<1>FB_B_WDQS<3>
FB_B_MA<0>
FB_B_MA<6>
FB_B_DQ<3>
FB_B_DQ<7>FB_B_DQ<0>FB_B_DQ<6>FB_B_DQ<1>
FB_B_DQ<26>FB_B_DQ<27>FB_B_DQ<2>
FB_B_DQ<30>FB_B_DQ<31>FB_B_DQ<29>FB_B_DQ<28>FB_B_DQ<24>FB_B_DQ<11>
FB_B_DQ<14>FB_B_DQ<13>FB_B_DQ<10>FB_B_DQ<9>FB_B_DQ<12>
FB_B_DQ<22>FB_B_DQ<8>
FB_B_DQ<21>
FB_B_DQ<20>FB_B_DQ<23>
FB_B_BA<1>FB_B_BA<0>
FB_B_DQ<56>FB_B_DQ<60>
FB_B_MA<1>
FB_B_DQ<45>
FB_B_DQ<58>
FB_B1_ZQFB_B_DQ<15>
FB_B0_SEN
FB_B0_ZQ
FB_B_RDQS<1>FB_B_RDQS<3>FB_B_RDQS<0>
FB_B_DQM_L<3>
FB_B_DQ<18>
FB_B_DQ<19>FB_B_DQ<16>
FB_B_DQ<25>
FB_B_DQ<4>FB_B_DQ<5>
FB_B_RDQS<4>
FB_B_DQ<17>
FB_B_MA<11>
FB_B_WDQS<2>
FB_B_WE_LFB_B_CS0_LFB_B_CLK_N<0>
FB_B_CKE
FB_B_MA<10>FB_B_MA<9>
FB_B_MA<7>
FB_B_MA<1>
FB_B_DQ<39>FB_B_DQ<36>FB_B_DQ<44>
FB_B_DQ<40>
FB_B_CLK_N<1>FB_B_CLK_P<1>
FB_B_MA<6>
FB_B_UMA<3>FB_B_UMA<4>FB_B_UMA<5>
FB_B_MA<7>FB_B_MA<8>FB_B_MA<9>FB_B_MA<10>FB_B_MA<11>
FB_B_DQ<53>
FB_B_DQM_L<5>FB_B_DQM_L<4>
FB_B_MA<0>
FB_B_CLK_P<0>
FB_B_CLK1_TERM
FB_B_WDQS<4>
FB_B_DQM_L<0>
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
FB_B1_VREF_UNTERM_L
=PP1V8_GPU_FB_VDDQ
FB_B0_VREFMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
FB_B1_VREFMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
C85031
2
C85021
2
C85041
2
C85011
2
C85221
2
C85231
2
C85241
2
C85251
2
C85261
2
U8500K9
H11
K11
L9
K10
M9
K4
H2
K3
L4
K2
M4
G9
G4
H3
F9
J11
J10
H9
F4
E3
E10
N10
N3
B2
B3
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
C2
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
C3
T2
T3
E2
F3
F2
G3
B11
B10
A9
H10
D3
D10
P10
P3
V9
J2
J3
V4
D2
D11
P11
P2
H4
A4
U8500A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
C1
V1
V12
C4
C9
C12
E1
E4
E9
E12
H1
H12
A3
A10
G1
G12
L1
L12
V3
V10
J1
J12
B1
B4
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
B9
B12
D1
D4
D9
D12
G2
G11
R85491
2
R85481
2
C85211
2
C85151
2
C85101
2
C85711
2
C85721
2
R85981
2
R85991
2
U8550K9
H11
K11
L9
K10
M9
K4
H2
K3
L4
K2
M4
G9
G4
H3
F9
J11
J10
H9
F4
E3
E10
N10
N3
B2
B3
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
C2
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
C3
T2
T3
E2
F3
F2
G3
B11
B10
A9
H10
D3
D10
P10
P3
V9
J2
J3
V4
D2
D11
P11
P2
H4
A4
C85731
2
C85741
2
C85751
2
U8550A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
C1
V1
V12
C4
C9
C12
E1
E4
E9
E12
H1
H12
A3
A10
G1
G12
L1
L12
V3
V10
J1
J12
B1
B4
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
B9
B12
D1
D4
D9
D12
G2
G11C85761
2
C85511
2
C85521
2
C85601
2
C85531
2
C85651
2
C85541
2
C8500 1
2
C8520 1
2
C8550 1
2
C8570 1
2
R85461
2
R85471
2
R85441
2
R85451
2
R85421
2
R85401
2
R85431
2
R85961
2
R85971
2
R85951
2
R85941
2
R85921
2
R85931
2
R85901
2
C8596 1
2
C8546 1
2
R85311
2
R85321
2
C85311
2
C85331
2
Q85003
5
4
R85301
2
R85811
2
R85821
2
R85801
2
C85811
2
C85831
2
Q85006
2
1
72
72 72
72 71
71 71
71 8
8 8
8
Page 73
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDD33_6
VDD33_7
VDD33_8
VDD33_9
VDD33_10
VDD33_11
VDD33_12
VDD33_13
ROM_SCLK
ROM_SI
ROM_SO
TESTMODE
SWAPRDY_A
MIOA_VDDQ_1
MIOA_VDDQ_2
MIOA_VDDQ_3
MIOA_VDDQ_4
MIOA_VDDQ_5
MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3
MIOB_VDDQ_4
MIOB_VDDQ_5
MIOA_VREF
MIOB_VREF
MIOACAL_PD_VDDQ
MIOACAL_PU_GND
MIOBCAL_PD_VDDQ
MIOBCAL_PU_GND
PLLVDD
PLLGND
H_PLLVDD
VID_PLLVDD
XTALIN
XTALOUT
XTALOUTBUFF
XTALSSIN
GPIO0
GPIO1
GPIO2
GPIO3
GPIO9
GPIO11
SPDIF
STEREO
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
MIOA_CLKOUT
MIOA_CTL3
MIOA_DE
MIOAD0
MIOAD1
MIOAD2
MIOAD3
MIOAD4
MIOAD5
MIOAD6
MIOAD7
MIOAD8
MIOAD9
MIOAD10
MIOAD11
MIOA_HSYNC
MIOA_VSYNC
MIOB_CLKIN
MIOB_CLKOUT
MIOB_CTL3
MIOB_DE
MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7
MIOBD8
MIOBD9
MIOBD10
MIOBD11
MIOB_HSYNC
MIOB_VSYNC
THERMDP
THERMDN
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO10
GPIO12
GPIO13
GPIO14
BUFRST_L
JTAG_TRST_L
MIOA_CLKOUT_L
MIOB_CLKOUT_L
ROMCS_L
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
BOM options provided by this page:
(NONE)Signal aliases required by this page:
40mA
40mA
(IPD)
(NONE)
- =PP1V2_GPU_VID_PLLVDD- =PP1V2_GPU_H_PLLVDD- =PP1V2_GPU_PLLVDD- =PP3V3_GPI_MIO- =PP3V3_GPU_VDD33Power aliases required by this page:
Page Notes
40mA
Typically <??mA
BGA(6 OF 8)
OMIT
NB8P-GS-W-A2
10K
1/16WMF-LF
5%
402
100K
402
1/16W5%
MF-LF
402
0.47UF10%6.3VCERM-X5R
402
0.47UF10%6.3VCERM-X5R
0.1uF
X5R16V
402
10%4.7UF
603CERM6.3V20%
FERR-220-OHM
0402
0402
FERR-220-OHM
0.1uF10%16VX5R402
MF-LF
5%1/16W
402
10K
5%
MF-LF402
1/16W
10K
49.91%
1/16WMF-LF
402
1/16WMF-LF
49.91%
402
49.91%1/16WMF-LF402
402X5R16V10%0.1uF
402MF-LF1/16W5%10K
1/16WMF-LF402
5%10K
6.3V10%1UF
CERM402
6.3V
402
10%1UF
CERM
49.9
402MF-LF1/16W1%
10%
402
16VX5R
0.1uF20%
6.3VCERM603
4.7UF
FERR-220-OHM
0402
20%6.3VCERM603
4.7UF
0.1uF
X5R16V
402
10%4.7UF
603CERM6.3V20%20%
6.3VCERM603
4.7UF
4.7UF
603CERM6.3V20%
402
0.47UF10%6.3VCERM-X5R
SYNC_MASTER=M75_MLB
051-7261 A.0.0
9273
SYNC_DATE=03/19/2007
NV G84M GPIO/MIO/Misc
=PP3V3_GPU_VDD33
GPU_SWAPRDY_A
=PP3V3_GPU_MIO
=PP1V2_GPU_VID_PLLVDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm
PP1V2_GPU_VID_PLLVDD_F
=PP1V2_GPU_H_PLLVDD
PP1V2_GPU_PLLVDD_FMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.2V
=PP3V3_GPU_MIO
GPU_MIOA_VREFGPU_MIOB_VREF
GPU_MIOA_VSYNC
GPU_MIOA_D<6>
GPU_XTALOUTBUFF
GPU_XTALOUTGPU_XTALIN
GPU_MIOA_D<7>GPU_MIOA_D<8>
GPU_MIOA_PU_GNDGPU_MIOB_PU_GND
GPU_MIOB_PD_VDDQGPU_MIOA_PD_VDDQ
GPU_MIOB_PU_GNDGPU_MIOB_PD_VDDQ
GPU_MIOA_PU_GNDGPU_MIOA_PD_VDDQ
GPU_ROM_SI
GPU_XTALSSIN
GPU_MIOB_D<10>
GPU_MIOB_CLKOUT_PGPU_MIOB_CLKOUT_NGPU_MIOB_CTL3GPU_MIOB_DE
GPU_MIOB_D<2>GPU_MIOB_D<3>GPU_MIOB_D<4>GPU_MIOB_D<5>GPU_MIOB_D<6>GPU_MIOB_D<7>GPU_MIOB_D<8>GPU_MIOB_D<9>
GPU_MIOB_D<11>
GPU_MIOB_VSYNC
GPU_MIOA_HSYNCGPU_MIOA_D<11>GPU_MIOA_D<10>GPU_MIOA_D<9>
GPU_MIOA_D<5>GPU_MIOA_D<4>GPU_MIOA_D<3>GPU_MIOA_D<2>GPU_MIOA_D<1>GPU_MIOA_D<0>GPU_MIOA_DEGPU_MIOA_CTL3GPU_MIOA_CLKOUT_NGPU_MIOA_CLKOUT_P
GPU_GPIO_6
GPU_GPIO_1
GPU_GPIO_11
GPU_GPIO_14
GPU_ROM_SCLK
GPU_ROM_SO
GPU_TESTMODE_PD
TP_GPU_BUFRST_LGPU_STEREO
GPU_GPIO_0
GPU_GPIO_2
GPU_GPIO_9
GPU_SPDIF
TP_GPU_JTAG_TCKTP_GPU_JTAG_TDITP_GPU_JTAG_TDOTP_GPU_JTAG_TMS
GPU_THERMD_N
GPU_GPIO_4
GPU_GPIO_8
GPU_GPIO_10
GPU_GPIO_12
TP_GPU_JTAG_TRST_L
GPU_MIOB_HSYNC
GPU_THERMD_P
GPU_MIOB_CLKIN
GPU_MIOB_D<0>GPU_MIOB_D<1>
GPU_GPIO_13
GPU_ROM_CS_L
MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm
PP1V2_GPU_H_PLLVDD_F
VOLTAGE=1.2V
=PP1V2_GPU_PLLVDD
GPU_GPIO_3
GPU_GPIO_5
GPU_GPIO_7
U8000
F3
K3
H1
H5
F4
E3
U3
U4
K5
G5
E2
J5
G6
K6
E1
D2
G23
AJ11
AK12
AL12
AK11
AL13
R4
P4
P3
P1
R3
M7
M8
R8
T8
U9
L2
R1
L1
L3
P2
N2
L4
L5
N1
N3
M1
M3
P5
N6
N5
M4
AE4
AD4
AD5
AD3
AD1
AF3
AA8
AB7
AB8
AC6
AC7
Y2
AE3
Y1
Y3
AC3
AC1
AB4
AA5
AC2
AB2
AB1
AA1
AB3
AA3
AC5
AB5
U10
T9
AA7
W2
AA6
AA4
J6
T3
M6
H2
J1
K1
AC11
L10
L7
L8
M10
AC12
AC24
AD24
AE11
AE12
H7
J7
K7
T10
U1
U2
T2
T1
R86961 2
R86951
2
C86011
2
C86021
2
C86361
2
C8635 1
2
L8635
1 2
L8640
1 2
C86171
2
R86161
2
R86171
2
R86201
2
R86221
2
R86211
2
C86191
2
R86181
2
R86191
2
C8611 1
2
C8610 1
2
R86231
2
C86311
2
C8630 1
2
L8630
1 2
C8633 1
2
C86411
2
C8640 1
2
C8643 1
2
C8637 1
2
C86001
2
74
74
73
73
8
8
8
8
8
74
74
74
74
74
74
74
73
73
73
73
73
73
73
73
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
8
74
74
74
Page 74
IN
IN
IN
IN
IN
IN
IN
DB
DC
DD
EN_L
INS2D
S1D
S2C
S1C
S2B
S1B
S2A
S1A DA
VCC
GNDTHRMLPAD
OUT
OUT
OUT
OUT
OUT
OUT
IN
G
D S
G
D
S
OUT
OUT
BI
BI
GND
VCC
NC
NC
SDA
SCL
NC
NC
OUT
OUT
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONETABLE_ALT_ITEM
TABLE_5_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
3GIO_PADCFG2
PCI_DEVID<4>
PCI_DEVID3
near GPU
ROMTYPE<1..0>USER<3..0>
PCI_IOBARBAR2_SIZE
PWR_CTL1
LCD0_VDD
LCD0_BL_EN
IS
NC
HDCP Support
HPD0
(I2CS requires pullups even if not used)I2CS ties into SMBus connection page
LCD0_BL_PWM
Config Straps
Unused I2C Buses
Unused signalsRenamed signals
Place Rs
Native Func
THERM
FAN_PWM
VID0
HPD1
GPIOs
PWR_CTL0
AC_DET
SLI_SYNC
MEM_VREF
MEM_VID
NC
VID1
RAMCFG1
Unused Clocks
near GPUPlace Rs
PCI_DEVID3
(BIOS ROM PRESENT)
TMDS Backdrive ProtectionPCI_DEVID0
PEX_PLL_EN_TERM3GIO_PADCFG3
RAMCFG33GIO_PADCFG0
PCI_DEVID0
SLOT_CLOCK_CFG
Straps not supported:
Analog Video Mux
Supported straps:
RAMCFG0
RAMCFG2
3GIO_PADCFG1
SUBVENDOR
MIOB_D<7>
MIOB_CTL3, MIOB_D<3,5>MIOB_DE
MIOA_HSYNCMIOB_VSYNC, MIOB_D<10>MIOA_D<5..2>
78
5%
MF-LF402
1K1/16W
NO STUFF
402
5%1/16WMF-LF
10K5%
1/16WMF-LF
402
10K
VRAM_128
MF-LF402
5%1/16W
10K10K5%
1/16WMF-LF
402
VRAM_SAMSUNG
1/16W
402MF-LF
10K5%
VRAM_256
5%1/16WMF-LF
402
10K
NO STUFF
5%10K
402
1/16WMF-LF
VRAM_HYNIX
1/16W
10K5%
MF-LF402
5%1/16WMF-LF
402
1K
NO STUFF
402MF-LF1/16W
5%1K
NO STUFF
402MF-LF1/16W
NO STUFF
5%1K
NO STUFF
1/16W5%
MF-LF402
1K
MF-LF1/16W
1K5%
402
GPU_SS_INT
10K
MF-LF1/16W
5%
402MF-LF1/16W
5%
402
10K
1%150
402MF-LF1/16W1/16W
1%150
MF-LF402402
MF-LF1/16W
1%150
75 90
75 90
75 90
75 90
75 90
75 90
1%150
402MF-LF1/16W
1%150
MF-LF1/16W
402
1/16W1%
150
402MF-LF
OMITCRITICAL
TS3V330
QFN
78 90
78 90
78 90
10V
0.1UF
20%
402CERM
1/16WMF-LF402
10K5%
76
76
76
66 76
5%
MF-LF402
1/16W
100K
CRITICAL
SOT-23SI2305DS
SOT-3632N7002DW-X-F
MF-LF402
5%1/16W
10K
76
76
HDCP
10V
0.1UF
20%
402CERM
HDCP
1/16W5%
MF-LF402
10K
10K
402MF-LF
5%1/16W
HDCP
75
75
CRITICAL
SOIAT88SC080C
HDCP
70 71 72
MF-LF1/16W
5%
402
1K
NO STUFF
402MF-LF1/16W
5%1K
MF-LF402
5%1/16W
1K5%1K
1/16W
402MF-LF
79
79
79
353S1718 1 U8700 CRITICALIC,TS3V340,QUAD VIDEO SW,QFN16
353S1579 353S1718 ALL (U8700) TS3V330 alt to TS3V340
SYNC_MASTER=M75_MLB SYNC_DATE=04/02/2007
051-7261 A.0.0
9274
GPU Straps
GPU_MIOB_D<0>
GPU_MIOA_D<0>GPU_MIOA_D<1>
=PP3V3_GPU_MIO
GPU_MIOB_D<9>
GPU_MIOA_D<8>
GPU_VGA_G
GPU_VGA_R
GPU_GPIO_9
GPU_GPIO_14
GPU_TV_Y
GPU_TV_COMP
GPU_MIOB_HSYNC
GPU_GPIO_0
MAKE_BASE=TRUETP_GPU_MIOA_D<11..10>
MAKE_BASE=TRUETP_GPU_MIOA_VSYNC
MAKE_BASE=TRUETP_GPU_MIOB_CLKIN
MAKE_BASE=TRUETP_GPU_MIOB_CTL3
MAKE_BASE=TRUETP_GPU_MIOB_DE
MAKE_BASE=TRUETP_GPU_MIOB_D<2> GPU_MIOB_D<2>
GPU_MIOB_DE
GPU_MIOB_D<11>
MAKE_BASE=TRUETP_GPU_MIOA_DE
MAKE_BASE=TRUETP_GPU_MIOA_D<5..2>
MAKE_BASE=TRUETP_GPU_MIOA_D<7>
MAKE_BASE=TRUETP_GPU_MIOA_HSYNC
GPU_MIOB_CLKOUT_N
MAKE_BASE=TRUETP_GPU_MIOB_D<7..6>
GPU_MIOA_VSYNC
GPU_MIOB_CLKIN
GPU_MIOB_CLKOUT_P
GPU_MIOB_CTL3
GPU_MIOB_D<7..6>
GPU_MIOB_D<10>
=PP3V3_GPU_VIDEOMUX
GPU_MIOB_D<5>GPU_MIOB_D<3>
GPU_VGA_B
GPU_MIOA_D<9>
GPU_GPIO_1
GPU_GPIO_2
GPU_GPIO_12
GPU_MIOB_D<8>
GPU_XTALSSINGPU_XTALOUTBUFF
MAKE_BASE=TRUETP_GPU_MIOB_VSYNC GPU_MIOB_VSYNCMAKE_BASE=TRUETP_GPU_MIOB_D<10>
MAKE_BASE=TRUE NO_TEST=TRUENC_GPU_IFPD_CLK_N GPU_IFPD_CLK_N
NO_TEST=TRUEMAKE_BASE=TRUENC_GPU_IFPD_CLK_P GPU_IFPD_CLK_P
GPU_TV_CGPU_VGA_EN_L
GPU_GPIO_8
MAKE_BASE=TRUEFB_VREF_UNTERM
MAKE_BASE=TRUEGPU_VCORE_VID1
GPU_I2CH_SCL
=PP3V3_GPU_HDCP
GPU_I2CH_SDA
GPU_GPIO_13
GPU_MIOB_D<1>
MAKE_BASE=TRUE NO_TEST=TRUENC_GPU_ROM_CS_L GPU_ROM_CS_L
NO_TEST=TRUEMAKE_BASE=TRUENC_GPU_ROM_SCLK GPU_ROM_SCLK
MAKE_BASE=TRUE NO_TEST=TRUENC_GPU_ROM_SI GPU_ROM_SI
MAKE_BASE=TRUE NO_TEST=TRUENC_GPU_ROM_SO GPU_ROM_SO
NO_TEST=TRUEMAKE_BASE=TRUENC_FBC_CMD28 TP_FBC_CMD28MAKE_BASE=TRUE NO_TEST=TRUENC_FBA_CMD28 TP_FBA_CMD28
TP_FBA_CMD27
TP_FBC_CMD27MAKE_BASE=TRUE NO_TEST=TRUENC_FBC_CMD27MAKE_BASE=TRUE NO_TEST=TRUENC_FBA_CMD27
MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_U_DATAP<3> LVDS_U_DATA_P<3>
MAKE_BASE=TRUETP_GPU_MIOB_CLKOUT_NMAKE_BASE=TRUETP_GPU_MIOB_CLKOUT_P
NO_TEST=TRUEMAKE_BASE=TRUENC_GPU_V2SYNC GPU_V2SYNC
GPU_MIOA_HSYNC
GPU_MIOA_DEMAKE_BASE=TRUETP_GPU_MIOA_CTL3 GPU_MIOA_CTL3MAKE_BASE=TRUETP_GPU_MIOA_CLKOUT_N GPU_MIOA_CLKOUT_N
MAKE_BASE=TRUE NO_TEST=TRUENC_GPU_H2SYNC GPU_H2SYNC
NO_TEST=TRUEMAKE_BASE=TRUENC_GPU_R2 GPU_R2
NO_TEST=TRUEMAKE_BASE=TRUENC_GPU_B2 GPU_B2MAKE_BASE=TRUE NO_TEST=TRUENC_GPU_G2 GPU_G2
GPU_MIOA_D<11..10>
GPU_MIOA_D<5..2>
GPU_MIOA_D<7>
MAKE_BASE=TRUETP_GPU_MIOA_CLKOUT_P GPU_MIOA_CLKOUT_P
MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_L_DATAN<3> LVDS_L_DATA_N<3>
MAKE_BASE=TRUE NO_TEST=TRUENC_GPU_CSYNC GPU_CSYNC
MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_L_DATAP<3> LVDS_L_DATA_P<3>MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_U_DATAN<3> LVDS_U_DATA_N<3>
MAKE_BASE=TRUEGPU_TDIODE_N GPU_THERMD_N
GPU_I2CB_SCL
NO_TEST=TRUEMAKE_BASE=TRUENC_GPU_XTALOUT
NO_TEST=TRUEMAKE_BASE=TRUENC_GPU_STEREO
NO_TEST=TRUEMAKE_BASE=TRUENC_FB_A_MA12 TP_FB_A_MA12
MAKE_BASE=TRUEGPU_VCORE_PWRCTL1MAKE_BASE=TRUEGPU_VCORE_PWRCTL0
GPU_TMDS_PWREN_L
=PP3V3_GPU_TMDS_FET
=GPUVCORE_EN
MAKE_BASE=TRUEGPU_VCORE_VID2
GPU_GPIO_10
GPU_VCORE_VID0MAKE_BASE=TRUE
TP_GPU_GSTATE<1>MAKE_BASE=TRUE
MAKE_BASE=TRUE NO_TEST=TRUENC_GPU_GPIO_8MAKE_BASE=TRUEGPU_VGA_EN_L
GPU_PANEL_ENMAKE_BASE=TRUE
MAKE_BASE=TRUEGPU_BKLT_EN
MAKE_BASE=TRUEGPU_BL_PWMMAKE_BASE=TRUE NO_TEST=TRUENC_GPU_GPIO_1
MAKE_BASE=TRUEGPU_HPD
GPU_TV_C_VGA_R
GPU_TV_COMP_VGA_B
GPU_TV_Y_VGA_G
MAKE_BASE=TRUEGPU_PANEL_DDC_DATA
MAKE_BASE=TRUEGPU_DVI_DDC_DATAMAKE_BASE=TRUEGPU_DVI_DDC_CLK
MAKE_BASE=TRUEGPU_PANEL_DDC_CLK
MAKE_BASE=TRUEGPU_CLK27M_GATED GPU_XTALIN
MAKE_BASE=TRUEGPU_TDIODE_P GPU_THERMD_PMAKE_BASE=TRUE
GPU_CLK27M_SS_GATED GPU_XTALSSIN
GPU_STEREONO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_SPDIF GPU_SPDIF
GPU_XTALOUT
GPU_I2CB_SDA
GPU_I2CC_SCL
GPU_I2CC_SDAMAKE_BASE=TRUE NO_TEST=TRUENC_FB_B_MA13
MAKE_BASE=TRUE NO_TEST=TRUENC_FB_B_MA12
MAKE_BASE=TRUE NO_TEST=TRUENC_FB_A_MA13
TP_FB_B_MA13
TP_FB_B_MA12
TP_FB_A_MA13
GPU_I2CA_SCLNO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_I2CA_SCL
GPU_I2CA_SDAMAKE_BASE=TRUE NO_TEST=TRUENC_GPU_I2CA_SDA
=PP3V3_GPU_TMDS
TP_GPU_GSTATE<0>MAKE_BASE=TRUE
GPU_GPIO_4
GPU_GPIO_5
GPU_GPIO_6
GPU_GPIO_7
GPU_MIOB_D<4>
GPU_GPIO_11
GPU_GPIO_3
=PP3V3_GPU_MIO
GPU_MIOA_D<6>
R87281
2
R87261
2
R87241
2
R87221
2
R87201
2
R87271
2
R87251
2
R87231
2
R87211
2
R87291
2
R87301
2
R87311
2
R87321
2
R87331
2
R87811
2
R87801
2
R87451
2
R87441
2
R87431
2
R87421
2
R87411
2
R87401
2
U87004
7
9
12
15
8
1
2
5
11
14
3
6
10
13
17
16
C87001 2
R87001
2
R87911
2
Q8790
3
1
2
Q89253
5
4
R87901
2
C87701 2
R87701
2
R87711
2
U8770
4
12
3
76
5
8
R87371
2
R87341
2
R87351
2
R87361
2
74
74
73
74
90
90
90
90
90
91
90 74
73
73
73
73
8
73
73
73
73
73
73
7
7
73
73
73
73
73
73
73
73
73
73
8
73
73
73
73
73
73
73
73
73
73
75
75
74
73
8
73
73
73
73
73
73
70
70
70
70
75
7
75
73
73
73
73
75
75
75
75
73
73
73
73
75
75
75
75
51 73
75 70
8
73
74
79
78
78
79
30 73
51 73
30 73
73
73
73
75
75
75 70
70
70
75
75
8
73
73
73
73
73
73
73
8
73
Page 75
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IFPA_TXD0
I2CB_SDA
I2CB_SCL
I2CA_SDA
I2CA_SCL
DACC_VSYNC
DACC_HSYNC
DACC_BLUE
DACC_GREEN
DACC_RED
DACB_CSYNC
DACB_BLUE
DACB_GREEN
DACB_RED
DACA_VSYNC
DACA_HSYNC
DACA_BLUE
DACA_GREEN
DACA_RED
IFPD_TXD6
IFPD_TXD5
IFPD_TXD4
IFPD_TXC
IFPC_TXD2
IFPC_TXD1
IFPC_TXD0
IFPC_TXC
IFPB_TXD7
IFPB_TXD6
IFPB_TXD5
IFPB_TXD4
IFPB_TXC
IFPA_TXD3
IFPA_TXD2
IFPA_TXD1
IFPA_TXC
I2CS_SDA
I2CS_SCL
I2CH_SDA
I2CH_SCL
I2CC_SDA
I2CC_SCL
DACC_RSET
DACC_VREF
DACC_IDUMP
DACC_VDD
DACB_RSET
DACB_VREF
DACB_IDUMP
DACB_VDD
DACA_RSET
DACA_VREF
DACA_IDUMP
DACA_VDD
IFPCD_RSET
IFPCD_VPROBE
IFPCD_PLLGND
IFPCD_PLLVDD
IFPD_IOVDD
IFPC_IOVDD
IFPAB_RSET
IFPAB_VPROBE
IFPAB_PLLGND
IFPB_IOVDD
IFPA_IOVDD
IFPAB_PLLVDD
IFPA_TXC_L
IFPA_TXD0_L
IFPA_TXD1_L
IFPA_TXD2_L
IFPA_TXD3_L
IFPB_TXC_L
IFPB_TXD4_L
IFPB_TXD5_L
IFPB_TXD6_L
IFPB_TXD7_L
IFPC_TXC_L
IFPC_TXD0_L
IFPC_TXD1_L
IFPC_TXD2_L
IFPD_TXC_L
IFPD_TXD4_L
IFPD_TXD5_L
IFPD_TXD6_L
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Power aliases required by this page:
Signal aliases required by this page:
Sum of peak currents: 240mA20mA peak per diff pair
200mA peak for all pairs20mA peak per diff pair
Place at AD6
BOM options provided by this page:
- =PP3V3_GPU_IFPCD_IOVDD
120mA peak
150mA peak
40mA peak
Place at AE7
40mA peak
Place at AF9 Place at AF8
Composite/S-Video VGA Component
Comp B PbY G YC R Pr
(NONE)
(NONE)
- =PP1V8_GPU_IFPX
- =PP3V3_GPU_DAC
I2CS must be pulled up if not usedI2CS addr fixed at 0x9E,0x9F
Page Notes160mA peak for all pairs
Sum of peak currents: 390mA
120mA peak
MF-LF402
1%1/16W
1K
NO STUFF
FERR-220-OHM
0402
20%0.1UF
10V
402CERM
FERR-220-OHM
0402
FERR-220-OHM
0402
FERR-220-OHM
0402
FERR-220-OHM
0402
NO STUFF
74 90
74 90
74 90
79 90
79 90
79 90
74 90
74 90
79 90
79 90
79 90
79 90
79 90
79 90
7 79 90
7 79 90
79 90
79 90
79 90
79 90
79 90
74 90
74 90
78 90
78 90
78 90
78 90
78 90
78 90
78 90
78 90
78 90
78 90
78 90
78 90
78 90
78 90
78 90
78 90
74
74
74
74
4.7UF20%
CERM6.3V
603
4.7UF
603CERM6.3V20%
74
74
74
74
74
74 90
74 90
74 90
NB8P-GS-W-A2BGA
OMIT
(5 OF 8)
74
74
1/16W
402MF-LF
1241%
1/16W
402MF-LF
1241%
1/16WMF-LF402
1241%
74
0.1UF
CERM402
20%10V
0.1UF10V20%
CERM402
0.1UF10V20%
CERM402
74
74
74
74
48
48
20%0.1UF10V
402CERM
20%0.1UF10VCERM402
20%6.3VCERM603
4.7UF
20%10VCERM402
0.1UF4.7UF
603CERM6.3V20%
NO STUFF
20%6.3VCERM603
4.7UF
4.7UF
CERM603
6.3V20%
20%0.1UF
10V
402CERM
4.7UF20%
CERM6.3V
603
0402
FERR-220-OHM
402CERM10V
0.1UF20%
CERM402
0.01UF16V20%
NO STUFF
CERM402
0.01UF16V20%
NO STUFF
402CERM10V
0.1UF20%20%
0.1UF10V
402CERM
20%6.3V
603CERM
4.7UF
0402
FERR-220-OHM
20%0.1UF
10V
402CERM
MF-LF402
1%1/16W
1K
NO STUFF
051-7261 A.0.0
9275
NV G84M Video InterfacesSYNC_MASTER=M75_MLB SYNC_DATE=03/19/2007
MIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm
PP1V8_GPU_IFPCD_PLLVDD_F
VOLTAGE=1.8V
LVDS_U_CLK_N
=PP3V3_GPU_DAC
=PP1V8_GPU_IFPX
GPU_VGA_G
GPU_G2GPU_B2
GPU_I2CC_SDAGPU_I2CC_SCL
GPU_DACC_RSETGPU_DACC_VREF
GPU_IFPAB_VPROBEGPU_IFPCD_VPROBE
GPU_DACB_VREFGPU_DACC_VREF
GPU_DACA_RSET GPU_DACA_VREF
GPU_IFPAB_RSETGPU_IFPCD_RSET
GPU_DACC_RSETGPU_DACB_RSET
=PP3V3_GPU_IFPCD_IOVDD
MIN_LINE_WIDTH=0.4 mmPP1V8_GPU_IFPAB_IOVDD_F
MIN_NECK_WIDTH=0.2 mmVOLTAGE=1.8V
PP1V8_GPU_IFPAB_PLLVDD_FMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.8V
MIN_LINE_WIDTH=0.4 mmPP3V3_GPU_IFPCD_IOVDD_F
MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V
PP3V3_GPU_DACA_VDD_FMIN_LINE_WIDTH=0.35 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=3.3V
PP3V3_GPU_DACB_VDD_FMIN_LINE_WIDTH=0.35 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=3.3V
PP3V3_GPU_DACC_VDD_FMIN_LINE_WIDTH=0.35 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=3.3V
LVDS_L_DATA_P<0>
GPU_I2CB_SDAGPU_I2CB_SCL
GPU_I2CA_SDAGPU_I2CA_SCL
GPU_V2SYNCGPU_H2SYNC
GPU_R2
GPU_CSYNC
GPU_TV_COMPGPU_TV_YGPU_TV_C
GPU_VGA_VSYNCGPU_VGA_HSYNC
GPU_VGA_B
GPU_VGA_R
TMDS_DATA_P<5>
TMDS_DATA_P<4>
TMDS_DATA_P<3>
GPU_IFPD_CLK_P
TMDS_DATA_P<2>
TMDS_DATA_P<1>
TMDS_DATA_P<0>
TMDS_CLK_P
LVDS_U_DATA_P<3>
LVDS_U_DATA_P<2>
LVDS_U_DATA_P<1>
LVDS_U_DATA_P<0>
LVDS_U_CLK_P
LVDS_L_DATA_P<3>
LVDS_L_DATA_P<2>
LVDS_L_DATA_P<1>
LVDS_L_CLK_P
GPU_DACB_RSETGPU_DACB_VREF
GPU_DACA_RSETGPU_DACA_VREF
GPU_IFPCD_RSETGPU_IFPCD_VPROBE
GPU_IFPAB_RSETGPU_IFPAB_VPROBE
LVDS_L_CLK_N
LVDS_L_DATA_N<0>
LVDS_L_DATA_N<1>
LVDS_L_DATA_N<2>
LVDS_L_DATA_N<3>
LVDS_U_DATA_N<0>
LVDS_U_DATA_N<1>
LVDS_U_DATA_N<2>
LVDS_U_DATA_N<3>
TMDS_CLK_N
TMDS_DATA_N<0>
TMDS_DATA_N<1>
TMDS_DATA_N<2>
GPU_IFPD_CLK_N
TMDS_DATA_N<3>
TMDS_DATA_N<4>
TMDS_DATA_N<5>
=GPU_I2CS_SDA=GPU_I2CS_SCLGPU_I2CH_SDAGPU_I2CH_SCL
R88511
2
R88501
2
L8805
1 2
C8806 1
2
L8815
1 2
L8830
1 2
L8820
1 2
L8840
1 2
C8805 1
2
C88201
2
U8000
AH12
AJ12
AF10
AG9
AH11
AH9
AD10
AH10
AK10
T6
U5
T5V7
R6
R7
V8
R5
AE5
AG6
AG7
AG4
AF6
AF5
AD7
AH4
AG5
K2
J3
H4
J4
G2
G1
G3
H3
C1
B1
AF9 AK9
AJ9
AH6
AJ6
AH8
AH7
AJ8
AK8
AJ5
AH5
AD9
AC9
AL5
AM4
AF8
AK4
AL4
AM6
AM5
AM7
AL7
AK6
AK5
AK7
AL8
AD6 AM2
AM3
AE2
AE1
AF1
AF2
AG1
AH1
AB10
AA10
AH3
AK3
AE7
AG3
AH2
AK1
AJ1
AL2
AL1
AJ2
AJ3
R88521
2
R88531
2
R88541
2
C88521
2
C88531
2
C88541
2
C88211
2
C88311
2
C88301
2
C88411
2
C88401
2
C8845 1
2
C8815 1
2
C8801 1
2
C8800 1
2
L8800
1 2
C8803 1
2
C88561
2
C88551
2
C8813 1
2
C8811 1
2
C8810 1
2
L8810
1 2
C8816 1
2
8
8
75
75
75
75
75
75
75 75
75
75
75
75
8
75
75
75
75
75
75
75
75
Page 76
OUT
V-
V++
-
THRM_PAD
VFB
TRIP
VOUT
EN_PSV
GND PGND
V5DRVV5FILT
DRVL
DRVH
LL
TON
VBSTPGOOD
SYM (2 OF 2)IN
OUT
G
D
S
G
D
S
G
D
S
IN
IN
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
Vout = 0.75V * (1 + Ra / Req)
(L8920 limit)18A max outputVout = 1.25V - 0.96V
<Rb>
(GPUVCORE_VFB)
Vout(min) = 0.75V * (1 + Ra / Rb)R8931 are for M76 only
differences. They should be removedif layout can be changed
and not present in M75 due to layout
XW8921, C8944, R8928, C8945, R8930,
(=PPVCORE_GPU_REG)
GPU VCore Regulator
1.250V (max perf)
1.125V (balanced)
1.050V (max batt)
1.050V (rsvd state)
GPU VCore Setpoints
FOR GOOD THERMAL COUPLING
Y Y Y
StateC D E
- - -
All other states not defined
(GPUVCORE_VFB)
0 0
0
Place near C8940
<Ra>
AwAY FROM THE EDGE OF THE BOARD/FANPLACE R8997 CLOSE TO L8920 &
<Rc> Req = Rb || Rc || Rd || Re
(GPUVCORE_TON)
1
GPU VCore Current Sense
(GND)
(=PPVCORE_GPU_REG)
1
11
1
0
10
0
VID2
Y - -
Y Y -
VID0VID1
<Rd> <Re>
GPU_XW1
2.87K
402MF-LF1/16W
1%
1/16WMF-LF
1%
402
7.15K
603X5R
20%6.3V
10UF
10%1000pF
X7R25V
402
NO STUFF
NO STUFF
61.9K1/16WMF-LF402
1%
50V
402CERM
470pF
10%
49
402
470pF
50V10%
CERM
402MF-LF
1M
1%1/16W
1/16W
402MF-LF
1%
1M
1uF
CERM402
10%6.3V
1/16W1%
20.0K
402MF-LF
MF-LF402
1%1/16W
20.0K
PLACEMENT_NOTE=Place R8990 close to L8920402MF-LF
1%1/16W
649PLACEMENT_NOTE=Place R8994 close to L8920
1/16WMF-LF402
1K
1%
NO STUFF
10%6.3V
402
PLACEMENT_NOTE=Place C8990 close to L8920
0.47UF
CERM-X5R
0603-LF
10KOHM-5%
CRITICAL
PLACEMENT_NOTE=Place R8997 close to L8920
402
1%1K
1/16WMF-LF
NO STUFF
5%
402
50VCERM
100PF
POLY
20%25V
CASE-D2-LF
22UF
CRITICAL
LFPAKRJK0305DPB
CRITICAL
CRITICAL
RJK0301DPBLFPAK
CRITICAL
LFPAKRJK0301DPB
1.0UH-20A
IHLP4040DZ11-SM
CRITICAL
0.22UF
PLACEMENT_NOTE=Place C8991 close to L8920
10%
402CERM-X5R
6.3V
CRITICAL
HPA00141AIDCKRSC70-5
200K1%1/16WMF-LF402
0.1UF
X7R603-1
10%50V
1uF16VX5R603
10%
CRITICAL
TPS51117RGY_QFN14QFN
X5R603
16V10%
2.2UF
SM
66 74
66
1/16W
402
1%10.5K
MF-LF
1%
MF-LF402
2001/16W
MF-LF
7.5K
402
5%1/16W
2N7002DW-X-FSOT-363
2N7002DW-X-FSOT-3637.5K
1/16W5%
MF-LF402
SOT-3632N7002DW-X-F
MF-LF1/16W5%
402
7.5K
74
402
1/16WMF-LF
5%100K 100K
5%
402MF-LF1/16W
74
1%28K1/16WMF-LF402
1%
402
16.9K1/16WMF-LF
0.1UF
402CERM10V20%
402
0.1UF
CERM10V20%
0.1UF
402CERM10V20%
1/16W
100K
MF-LF402
5%
74
603
10%
X5R25V
1UF22UF
CASE-D2-LF
25V20%
POLY
CRITICAL
D2T
2.0VTANT
CRITICAL
330UF10%
TANT2.0V10%
D2T
CRITICAL
330UF
SM
74
74
5%
402MF-LF1/16W
1.5K
NO STUFF
402
1/16WMF-LF
5%1K
NO STUFF
402MF-LF
4.99K
1/16W1%
NO STUFF
1/16WMF-LF402
4.99K
1%
NO STUFF
16V10%
0.01UF
CERM402
NO STUFF
402
0.01UF
10%
CERM16V
NO STUFF
1K5%
1/16WMF-LF
402
NO STUFF
402
1/16WMF-LF
5%1K
NO STUFF NO STUFF
1.5K5%
MF-LF1/16W
402
NO STUFF
1K
MF-LF
5%
402
1/16W
10K
1/16W5%
MF-LF402
NO STUFF
10K
1/16W
402MF-LF
5%
NO STUFF
NO STUFF
MMDT3904XFSOT-363-LF
SOT-363-LFMMDT3904XF
NO STUFF
SM
SM
GPU_XW2
1%1/16W
2.87K
402MF-LF
CASE-B2POLY2.0V
GPU_LOADCAP
20%330UF
CRITICAL
330UF
POLY2.0V20%
CASE-B2
GPU_LOADCAPCRITICAL
1/16W
402MF
GPU_XW1
0
5%GPU_XW2
1/16W
0
5%
402MF
RES,5.76K,1%,1/16W,0402,LF114S0292 GPU_XW3R8921,R89282
76
A.0.0051-7261
92
SYNC_DATE=03/21/2007SYNC_MASTER=M75_MLB
GPU (G84M) Core Supply
MIN_LINE_WIDTH=0.6 mmPP5V_S5_GPUVCORE_V5FILT
VOLTAGE=5VMIN_NECK_WIDTH=0.2 mm
GPUVCORE_VFB_C
GPUVCORE_DRVLMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
GPU_VCORE_VID0_RC
PC1_DIV
PC0_DIV PC0_BIAS
GPU_VCORE_PWRCTL1 PC1_BIAS_B
GND_GPUVCORE_SGND
NC_GPUVCORE_VFB_PC1
GPUVCORE_TRIP
=PPVIN_GPU_GPUVCORE
GND_GPUVCORE_SGND
=GPUVCORE_EN
GPUVCORE_IOUT
=PP3V3R5V_GPU_GPUISENSGPUISENS_NTC
GND_GPUVCORE_SGND
GPU_VCORE_VID1_RC
GPU_VCORE_PWRCTL0
GPUVCORE_LLSWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
GPUVCORE_TON
GPUISENS_RC
GPUISENS_NEG
PVCORE_GPU_NTC
MIN_LINE_WIDTH=0.25 mmPPVCORE_GPU_XWMIN_NECK_WIDTH=0.20 mmVOLTAGE=1.25V
GPUISENS_POS
GPUVCORE_VFB_D
GPUVCORE_VFB_E
GPU_VCORE_VID2_RC
=PP3V3_GPU_VCORELOGIC
=PP5V_S5_GPUVCORE
GND_GPUVCORE_SGND
PC1_BIAS
=PP1V2_GPU_VCOREPWRCTL
NC_GPUVCORE_VFB_PC0
GPU_VCORE_VID2
GPU_VCORE_VID0
=GPUVCORE_PGOOD
PPVCORE_GPULOAD_XW
GPUVCORE_VFB
PC0_BIAS_B
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mmGND_GPUVCORE_SGND
MIN_NECK_WIDTH=0.25 mm
GATE_NODE=TRUEGPUVCORE_DRVH
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
GPUVCORE_VBSTMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.2 mm
PPVCORE_GPULOAD_XW
=PPVCORE_GPU_REG
GPU_VCORE_VID1
GND_GPUVCORE_SGND
R89211
2
R89221
2
C89401
2
C8921 1
2
R89231
2
C899812
C899212
R89981 2
R89921 2
C89951
2
R89931 2
R89911 2
R89901
2
R89941 2
C899012
R8997
1
2
R89961
2
C89201
2
C8930 1
2
Q8920
5
4
1 2 3
Q8922
5
4
1 2 3
Q8921
5
4
1 2 3
L8920
1 2
C899112
U89951
3
4
2
5
R89191
2C8915 1
2
C89001
2
U8900
13
9
1
7
12
8
6
15
2
11
10
4
14
5
3
C8901 1
2
XW89001 2
R89051
2
R89011
2
R89731 2
Q89233
5
4
Q89236
2
1
R89741 2
Q89256
2
1
R89751 2
R89701
2
R89711
2
R89241
2
R89251
2
C89731
2
C89741
2
C89751
2
R89721
2
C89321
2
C8931 1
2
C8942 1
2 3
C89431
23
XW8920
1
2
R89671
2
R89621
2R89601 2
R89651 2
C89611 2
C89661 2
R89661
2
R89611
2
R89631
2
R89681
2
R89641 2
R89691 2
Q89275
3
4
Q89272
6
1
XW8901
1
2
XW8921
1
2
R89281
2
C89441
2
C89451
2
R89301 2
R89311 2
49 8
76
7
8
76
8
76
8
8
76
8
7
76
76
7
76
Page 77
D
S
G
G
D
SIN
SYM_VER-1
SYM_VER-1
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
LCD (LVDS) INTERFACE
100K pull-ups are for no-panel case (development).Panel has 2K pull-ups
518S0289
0.001uF
CERM402
20%50V
20%0.001uF
50VCERM402
CRITICAL
SM
FERR-250-OHM
0.0022uF
CERM402
10%50V
100K
MF-LF402
5%1/16W
100K
MF-LF402
5%1/16W
SI3443DVTSOP-LF
2N7002SOT23-LF
MF-LF
100K
402
5%1/16W
100K
MF-LF402
5%1/16W
402
100K
MF-LF
5%1/16W
79 MSC-RB30-5-FAF-RT-SM
CRITICAL
PLACEMENT_NOTE=Place close to connector.
90-OHM-100MA1210-4SM1
CRITICAL
CRITICAL
1210-4SM190-OHM-100MA
PLACEMENT_NOTE=Place close to connector.
SYNC_DATE=03/19/2007SYNC_MASTER=M75_MLB
LVDS Display Connector
051-7261 A.0.0
9277
=PP3V3_S0_LCD
LVDS_U_CLK_CONN_P
LVDS_U_CLK_CONN_N
LVDS_PANEL_EN
LVDS_L_CLK_CONN_P
LVDS_L_CLK_CONN_N
LVDS_U_DATA_CONN_P<2>LVDS_U_DATA_CONN_N<2>
LVDS_U_DATA_CONN_P<1>LVDS_U_DATA_CONN_N<1>
LVDS_U_DATA_CONN_P<0>
LVDS_L_DATA_CONN_N<1>LVDS_L_DATA_CONN_P<1>
LVDS_L_DATA_CONN_N<2>LVDS_L_DATA_CONN_P<2>
LVDS_U_DATA_CONN_N<0>
LVDS_L_DATA_CONN_N<0>LVDS_L_DATA_CONN_P<0>
LCD_PWREN_L
LCD_PWREN_L_RCVOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
PP3V3_SW_LCD_UF
LVDS_CONN_DDC_DATALVDS_CONN_DDC_CLK
=PP3V3_S0_DDC_LCD
LVDS_U_CLK_CONN_F_PLVDS_U_CLK_CONN_F_N
LVDS_L_CLK_CONN_F_PLVDS_L_CLK_CONN_F_N
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPP3V3_SW_LCD
VOLTAGE=3.3V
C9010 1
2
C9001 1
2
L9000
C90001 2
R9001
R90001
2
Q9000
1
2
5
63
4
Q90013
1
2R90941
2
R90111
2
R90101
2
J9000
33
34
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
4
5
6
7
8
9
L9010
1
2 3
4
L9011
1
2 3
4
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
8
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
8
91
91
Page 78
G
SD
G
SD
SYM_VER-1
G
SD
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
GS
D
GS
D
IN
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
514-0278
(55mA requirement per DVI spec)
DVI INTERFACEDVI DDC Current Limit
Isolation required for DVI->ADC Adapter
GPU Isolation / Level-Shift
(PP5V_S0_DDC)
VGA SYNC BuffersPLACE CLOSE TO CONNECTOR
ANALOG FILTERING(Place close to connector)
(DACB TV C)
(DACB TV COMP)
(DACB TV Y)
TMDS Filtering(Place close to GPU)
10K
MF-LF402
5%1/16W
10K
MF-LF402
5%1/16W
2N7002DW-X-FSOT-363
2N7002DW-X-FSOT-363
270K
MF-LF402
5%1/16W
50V5%
402CERM
100pF
1/16W5%
402MF-LF
4.7K1/16W
5%
402MF-LF
4.7K
100pF
CERM402
5%50V
50V20%
603CERM
0.01uF
400-OHM-EMI
SM-1
CRITICALCRITICAL
0.5AMP-13.2V
SM-LF
SOD-123
B0530WXF
50V5%
402CERM
100pF
1/16W5%
402MF-LF
100
1/16W5%
402MF-LF
100
100
MF-LF402
5%1/16W
50V0.25%
402CERM
3.3pF
VGA_TERM_FILTER
402MF-LF
1501/16W
1%
VGA_TERM_FILTER
1/16W1%
402MF-LF
150
VGA_TERM_FILTER
MF-LF402
1%1/16W
150
50V0.25%
402CERM
3.3pF
3.3pF
CERM402
0.25%50V
33
MF-LF402
5%1/16W
33
MF-LF402
5%1/16W
F-RT-TH-DVIQH11121-RIG02-4F
CRITICAL
20K
MF-LF402
5%1/16W
1/16W1%
49.9
SIGNAL_MODEL=EMPTY402
MF-LF
NO STUFF
SIGNAL_MODEL=EMPTY
MF-LF402
1%1/16W
NO STUFF
49.9
SIGNAL_MODEL=EMPTY
MF-LF402
1%1/16W
NO STUFF
49.9
1/16W5%
402MF-LF
0
0
MF-LF402
5%1/16W
SIGNAL_MODEL=EMPTY
1/16W1%
402MF-LF
NO STUFF
49.9
49.91/16W
SIGNAL_MODEL=EMPTY
1%
402MF-LF
NO STUFF
SM
PLACEMENT_NOTE=Place close to connector.
CRITICAL
370-OHM
0.1uF
CERM402
20%10V
0.1uF
CERM402
20%10V
PLACEMENT_NOTE=Place close to connector.
MC74VHC1G08SC70
MC74VHC1G08SC70
PLACEMENT_NOTE=Place close to connector.
SIGNAL_MODEL=EMPTY
NO STUFF
49.9
MF-LF402
1/16W1%
2N7002DW-X-FSOT-363
270K
MF-LF402
5%1/16W
90-OHM-100MA1210-4SM1
CRITICAL
PLACEMENT_NOTE=Place close to connector.
PLACEMENT_NOTE=Place close to connector.
CRITICAL
1210-4SM190-OHM-100MA
PLACEMENT_NOTE=Place close to connector.
CRITICAL
90-OHM-100MA1210-4SM1
90-OHM-100MA1210-4SM1
PLACEMENT_NOTE=Place close to connector.
CRITICAL
PLACEMENT_NOTE=Place close to connector.
90-OHM-100MA1210-4SM1
CRITICAL
CRITICAL
90-OHM-100MA
PLACEMENT_NOTE=Place close to connector.
1210-4SM1
24
75 90
75 90
75 90
75 90
75 90
75 90
75 90
75 90
75 90
75 90
75 90
75 90
75 90
75 90
75 90
75 90
74 90
74 90
74 90
74
74
2N7002DW-X-FSOT-3632N7002DW-X-FSOT-363
28
74
16VCERM402
10%0.01UF
NO STUFF
NO STUFF
16V
0.01UF10%
402CERM
10%
402CERM
NO STUFF
0.01UF16V
16V
0.01UF10%
402CERM
NO STUFF
16V
0.01UF10%
402CERM
NO STUFF
NO STUFF
CERM402
10%0.01UF
16V
NO STUFF
CERM402
10%0.01UF
16V
SIGNAL_MODEL=EMPTY
1/16W1%
402MF-LF
NO STUFF
49.9
CRITICAL
210MHZMEA2010P-SM
OMIT
402
NONE
SHORTNONE
NONE
OMIT
NONE402
NONE
SHORTNONE
OMIT
NONE
NONESHORTNONE
402NONE
NONESHORTNONE
402
OMIT
402NONE
NONESHORTNONE
OMITOMIT
NONE
SHORTNONE
NONE402
OMIT
SHORTNONENONE
NONE402
OMIT
NONE
SHORTNONE
NONE402
1/16W
NO STUFF
49.9
1% MF-LF 402
402MF-LF1/16W1%
49.9
NO STUFF
402MF-LF1/16W1%
49.9
NO STUFF
49.9
1% 1/16W MF-LF 402
NO STUFF
402MF-LF1/16W1%
49.9
NO STUFF
402MF-LF1/16W1%
49.9
NO STUFF
402MF-LF1%
49.9
NO STUFF
1/16W
VGA_TERM_CONN
402MF-LF
1501/16W
1%
VGA_TERM_CONN
1/16WMF-LF
1%150
402
VGA_TERM_CONN
1%1/16W
150
MF-LF402
SYNC_DATE=03/19/2007SYNC_MASTER=M75_MLB
DVI Display Connector
78 92
A.0.0051-7261
TMDS_CLK_R_P
TMDS_DATA_P<4>
TMDS_DATA_P<5>
TMDS_CLK_N
TMDS_DATA_R5
TMDS_DATA_R4
TMDS_DATA_R3
TMDS_DATA_P<3>
TMDS_DATA_P<1>
TMDS_DATA_P<2>
TMDS_CLK_CMF
TMDS_CLK_P
TMDS_DATA_P<0>
=PP3V3_GPU_TMDSBIAS
TMDS_CLK_R_N
=GND_CHASSIS_DVI_BOT
TMDS_DATA_F_N<3>
TMDS_DATA_F_P<3>DVI_DDC_CLK_R
MIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=5V
PP5V_S0_DDC
DVI_HPD
VGA_HSYNC
=PP3V3_GPU_TMDSBIAS
=PP3V3_GPU_TMDSBIAS
=PP3V3_GPU_TMDSBIAS
=PP3V3_GPU_TMDSBIAS
=PP3V3_GPU_TMDSBIAS
=PP3V3_GPU_TMDSBIAS
GPU_VGA_VSYNC
GPU_VGA_HSYNC
TMDS_DATA_F_P<0>
=PP3V3_GPU_VGASYNC
VGA_G
GPU_TV_COMP_VGA_B
VGA_R
VGA_B
TMDS_CLK_F_P
TMDS_DATA_F_N<2>
TMDS_DATA_F_N<1>
TMDS_DATA_F_P<1>
TMDS_DATA_F_N<3>
TMDS_DATA_F_P<3>
TMDS_DATA_N<3>
TMDS_DATA_F_N<4>
TMDS_DATA_F_P<4>
VGA_HSYNC_R VGA_HSYNC
VGA_VSYNC_R VGA_VSYNC
=PP3V3_GPU_VGASYNC
TMDS_DATA_F_P<5>
TMDS_DATA_F_N<5>
TMDS_DATA_F_P<4>
TMDS_DATA_F_N<4>
TMDS_DATA_F_P<1>TMDS_DATA_F_P<0> TMDS_DATA_F_P<2>
TMDS_DATA_F_N<0>TMDS_DATA_F_N<1>TMDS_DATA_F_N<2>
TMDS_CLK_F_N
TMDS_CLK_F_P
VGA_VSYNCDVI_HPD_R
=PP5V_S0_DVI_DDCPP5V_S0_DDC_PULLUPS
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=5V
DVI_DDC_CLK
DVI_DDC_DATA
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmPP5V_S0_DDC_F
VOLTAGE=5V
DVI_DDC_DATA_R
GPU_DVI_DDC_CLK
=PP5V_S0_SB_HPD
DVI_HOTPLUG_DET
=PP3V3_GPU_DVI
GPU_HPD_BILAT
GPU_DVI_DDC_DATA
GPU_HPD
=GPU_HPD_ENABLE
TMDS_DATA_F_N<0>
TMDS_DATA_F_P<5>
TMDS_DATA_F_N<5>
GPU_TV_Y_VGA_G
TMDS_CLK_F_N
TMDS_DATA_N<5>
TMDS_DATA_N<4>
GPU_TV_C_VGA_R
TMDS_DATA_F_P<2>TMDS_DATA_R2
=GND_CHASSIS_DVI_TOP
=GND_CHASSIS_DVI_BOT
VGA_R
VGA_G
VGA_B
TMDS_DATA_N<2>
TMDS_DATA_R1
TMDS_DATA_N<1>
TMDS_DATA_R0
TMDS_DATA_N<0>
R94211
2
R94201
2
Q9411
6
2
1
Q9411
3
5
4
R94221
2
C94131
2
R94121
2
R94101
2
C94111
2
C9410 1
2
L9410
1 2
F94101 2
D94101 2
C94141
2
R94111 2
R94131 2
R94141 2
C94411
2
R94421
2
R94401
2
R94411
2
C94421
2
C94401
2
R94501 2
R94511 2
J9400
C1
C2
C3
C4
C5AC5B
31
32
33
34
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
3
4
5
6
7
8
9
R94151
2
R94861
2
R94821
2
R94781
2
R94731 2
R94721 2
R94701
2
R94661
2
L9472
1
2 3
4
C9451 1
2
C9450 1
2
U9450
3
2
1
4
5
U9451
3
2
1
4
5
R94621
2
Q9415
6
2
1
R94231
2
L9460
1
2 3
4
L9464
1
2 3
4
L9468
1
2 3
4
L9480
1
2 3
4
L9476
1
2 3
4
L9484
1
2 3
4
Q9414
6
2
1
Q9414
3
5
4
C9462 1
2
C9466 1
2
C9470 1
2
C9478 1
2
C9482 1
2
C9486 1
2
C9474 1
2
R94741
2
FL9440
27
36
45
18
CX94911
2
CX94901
2
CX94921
2
CX94931
2
CX94031
2
CX94021
2
CX94011
2
CX94001
2
R946312
R946712
R947112
R947512
R947912
R948312
R948712
R94431
2
R94451
2
R94441
2
78
78
91
91
91
78
78
78
78
78
78
91
78
91
91
91
91
91
91
91
91
91
91
91
91
91
78
91
91
91
91
91
91 91
91
91
91
91
91
91
91
91
91
91
91
78
91
91
91
91
8
91
9
78
78
78
8
8
8
8
8
8
78
8
78
78
78
78
78
78
78
78
78
78
78
91 78
91 78
8
78
78
78
78
78
78 78
78
78
78
78
78
78
8
8
8
78
78
78
78
78
9
9
78
78
78
Page 79
SYM_VER-3
GND
SEL
DB19*
DB18*
DB17*
DB16*
DB15*
DB14*
DB13*
DB12*
DB11*
DB10*
DB9* DH19
DH14
DH13
DH12
DH11
DH10
DH9
DH15
DH16
DH17
DH18
DB4*
DB5*
DB6*
DB7*
DB8*
DB0*
DB1*
DB2*
DB3*
DH4
DH3
DH2
DH1
DH0
DH8
DH7
DH6
DH5
DA15
DA16
DA17
DA18
DA19
DA13
DA14
DA12
DA11
DA10
DA5
DA6
DA7
DA8
DA9
DA0
DA1
DA2
DA3
DA4
VDD
G
S D
G
S D
IN
IN
OUT
BIBI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
VPG
V2
V4
V3
VREF RST*
CRT
THRM_PADGND
PBR*
V1
OUT
G
D
S
G
D
S
IN
IN
IN
V+
V-
1B1
4B2
2B1
2B2
3B1
3B2
4B1
1B2
1A
2A
3A
4A
OE*
S
THRMLPADGND
VCC
SYM_VER-2
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
PGOOD Monitor for GPU RailsLTC2900 provides programmable reset delay which is required to play nice with ICHx PGOOD circuit
LVDS Data Mux Power Supply
GPU LVDS I/F
NC
NC
NC
NB LVDS I/F
LVDS I/F Mux
NC
NOTE: SEL = LOW selects port B
Fast wake condition is worst case. ICHxcan create an S3 duration of 1 RTC clock(32 us). If mux select is on core welland AND-gate is implemented, glitch filteror <99ms PGOOD assertion time is requiredfor PGOODs to be valid at end of 99 ms SMCtimer. If mux select on resume well, thenobserved PGOOD will not change during S3transitions and ICHx will honor whatever
be necessary before going to sleep to keep PGOODs valid.core well, this could mean powering up IG supply willa switch can occur. If mux select GPIO is still on a to guarantee that the "other" device is ready beforebe powered off if using external GPU. S/W will haveNOTE: New H/W and S/W challenge since NB gfx might
Panel/Backlight Control Mux
Alias to 3.3V if not used->
NOTE: NAND-gate required if EXTGPU_LVDS_EN GPIO is on SB core well. Keeps PGOOD looking at non-GPUrails until GPIO switches back to default state andGPU power rails have come up and are valid (whichshould be before platform reset deasserts). Couldbe eliminated if GPIO moved to resume well.
HI=xB2LO=xB1
Trst = 4.6ms/nF
(Int. GFX)
NC
(Int. GFX)
(Ext. GFX)
(Ext. GFX)
PGOOD delays are provided.
GPU DDC Pass FETs
Mux Select Conditioning
LTC2900 typical threshold is 93.5% (3.055V, 2.325V, 1.685V, 1.120V)
Trst = 1.5ms
470K1/16W5%
MF-LF402
CBTV4020
CRITICAL
BGA-LF
2N7002DW-X-FSOT-363
SOT-3632N7002DW-X-F
402CERM
0.1UF10V20%
CERM
0.1UF10V20%
402 5%
402MF-LF1/16W
1K
74
15
77
77 74
15
77 91
77 91
77 91
77 91
77 91
77 91
77 91
77 91
77 91
77 91
77 91
77 91
77 91
77 91
77 91
77 91
74
15
74
15
74
15
28 30 79
9
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
15 84
75 90
75 90
7 75 90
75 90
75 90
7 75 90
75 90
75 90
75 90
75 90
75 90
75 90
75 90
75 90
75 90
15 84
75 90
81
77
LTC2900DFN
CRITICAL
1%124K
402MF-LF1/16W
MF-LF
1%1/16W
402
100K
CERM402
50V10%
330PF
402CERM10V20%
0.1UF
28 30 79
1/16W5%
402MF-LF
10K
5%10K
1/16W
402MF-LF
1/16W
402MF-LF
10K5%
2N7002DW-X-FSOT-363
2N7002DW-X-FSOT-363
5%1/16W
0
MF-LF
LVDS_SEL_RESUME
402
LVDS_SEL_CORE
MF-LF
0
1/16W5%
402
20%10VCERM402
LVDS_SEL_CORE
0.1UF
7 9 24 28
25
13 24
0
402
5%1/16WMF-LF
LVDS_SEL_RESUME
LVDS_SEL_CORE
402
5%1/16W
0
MF-LF
SC70-5
LVDS_SEL_COREMC74VHC1G00
402MF-LF1/16W
1%10K
SOT23-6-LFMAX4236EUTTCRITICAL
402
10V
0.1UF
20%
CERM
1%1/16WMF-LF
402
31.6K20%10VCERM402
0.1UF
0.1UF
CERM402
20%10V
10V20%
402CERM
0.1UF
1/16W1%
402MF-LF
15.8K
1/16W
402MF-LF
1%15.8K
74CBTLV3257QFN
CRITICAL
10K
MF-LF402
5%1/16W1/16W
5%
402MF-LF
100K
0.1uF
402CERM
20%10V
28K1/16W
402MF-LF
1%
MF-LF
71.5K
402
1/16W1%
LVDS Interface Mux
9279
051-7261 A.0.0
SYNC_MASTER=M75_MLB SYNC_DATE=03/19/2007
RSVD_EXTGPU_LVDS_EN
=PP3V3_S0_LVDS_MUX
PP3V3_GPU
LVDS_DDC_CLK
GPU_PANEL_DDC_DATA
EXTGPU_LVDS_EN33_L
PP2V5_S0_LVDS_MUX
PP1V25_GPU
=PP3V3_GPU_LVDS_DDC
LVDS_CONN_DDC_CLKMAKE_BASE=TRUE
LVDS_CONN_DDC_DATAMAKE_BASE=TRUE
GPU_PANEL_DDC_CLK
=GPU_DDC_ENABLE
LVDS_DDC_DATA
=PP3V3_S0_LVDS_MUX
PLT_RST_L
=PP3V3_S0_LVDS_MUX
PM_ALL_NBGFX_PGOOD
LVDSCTRLMUX_SEL_GPU_L
LVDS_PANEL_EN
LCDBKLT_PWM_UNBUF
GPU_PANEL_EN
LCDBKLT_PWREN
TP_PM_ALL_GFX_PGOOD
LVDS_VDD_EN
LVDS_BKLT_CTLPM_ALL_GPU_PGOOD
GPU_PGOOD_CRT
PM_ALL_GPU_PGOOD
GPU_PGOOD_VPG
GPU_PGOOD_VREF
EXTGPU_LVDS_EN
EXTGPU_LVDS_EN_QUAL
EXTGPU_LVDS_SEL
GPU_PGOOD_P1V2_DIV
LVDSCTRLMUX_SEL_GPU_L
LVDSDATAMUX_SEL_GPU_L
PP2V5_S0_LVDS_MUX
LVDSDATAMUX_SEL_GPU_L
LVDS_U_DATA_CONN_P<2>LVDS_U_CLK_CONN_PLVDS_U_CLK_CONN_N
LVDS_U_DATA_CONN_N<1>LVDS_U_DATA_CONN_P<1>
LVDS_L_DATA_CONN_P<2>LVDS_L_DATA_CONN_N<2>LVDS_L_DATA_CONN_N<1>LVDS_L_DATA_CONN_P<1>
LVDS_L_CLK_CONN_PLVDS_L_CLK_CONN_N
LVDS_L_DATA_CONN_N<0>LVDS_L_DATA_CONN_P<0>
LVDS_U_DATA_CONN_N<0>LVDS_U_DATA_CONN_N<2>
LVDS_U_DATA_CONN_P<0>
LVDS_L_DATA_N<2>LVDS_L_DATA_N<1>LVDS_L_DATA_P<1>
LVDS_L_DATA_P<2>LVDS_L_DATA_P<0>LVDS_L_DATA_N<0>
LVDS_L_CLK_NLVDS_L_CLK_P
LVDS_U_DATA_N<2>LVDS_U_DATA_N<0>LVDS_U_DATA_P<0>
LVDS_B_DATA_N<1>
LVDS_B_CLK_NLVDS_B_CLK_PLVDS_B_DATA_P<2>
LVDS_B_DATA_P<1>
LVDS_A_DATA_N<2>LVDS_A_DATA_N<1>LVDS_A_DATA_P<1>
LVDS_A_CLK_N
LVDS_A_DATA_N<0>LVDS_A_DATA_P<0>LVDS_A_DATA_P<2>
LVDS_B_DATA_N<0>LVDS_B_DATA_N<2>
LVDS_B_DATA_P<0>
LVDS_A_CLK_P
LVDS_U_DATA_P<1>LVDS_U_DATA_N<1>
LVDS_U_CLK_NLVDS_U_CLK_PLVDS_U_DATA_P<2>
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.10 mm
PP2V5_S0_LVDS_MUX
VOLTAGE=2.5VP2V5_S0_VREF
=PP3V3_S0_LVDS_MUX
PP1V8_GPU=PP2V5_GPU_LTC2900
GPU_BL_PWMLVDS_BKLT_ENGPU_BKLT_EN
C95501
2
C9560 1
2R95701
2
R95711
2
U956042
3
75
6
911
10
1214
13
15
8
1
17
16
R95601
2
R95611
2
C9590 1
2
R95901
2
R95911
2
R95961
2
U9550
F1
H1
K1
K3
K4
K6
J7
K9
J10
G10
E10
C10
A10
A8
A7
A5
B4
A2
B1
D1
G1
J1
K2
J4
K5
K7
K8
K10
H10
F10
D10
B10
A9
B7
A6
A4
A3
A1
C1
E1
F2
H2
J2
J3
J5
J6
J8
J9
H9
F9
E9
C9
B9
B8
B6
B5
B3
B2
C2
E2
C5
C6
D2
D9
G2
G9
H5
H6
E3
E8
F3
F8
Q9570
6
2
1
Q9570
3
5
4
C9593 1
2
C9591 1
2R95951
2
U9590
3
6
5
4
11
2 10
1
9
7
8
R95931
2
R95941
2 C9595 1
2
C959212
R95621
2
R95451
2
R95441
2
Q95406
2
1
Q95403
5
4
R95411 2
R95421 2
C956112
R95431 2
R95631 2
U9561
3
2
1
4
5
R95551
2 U95553
4
1
5
6
2
C955512
R95561
2
C95561
2
79
79
79
79
8
8
79
8
8
28
8
8
79
79
79
79
79
79
8
8
8
Page 80
BI
BI
IN
IN
IN
OUT
OUT
BI
BI
SYM_VER-1
SYM_VER-1
OUT
IN
BI
BI
OUT
OUT
BI
BI
OUT
BI
BI
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Top-Case Connector
516S0350
Bluetooth (M13P) & SATA HDD Flex Connector
Classic Inverter
PBUS
Split Inverter
Bridge 2Bridge 1IFB (Current Sense)VFB (Voltage Sense)
No ConnectNo Connect
Inverter Connectors
"Antenna" Pad
INV_BYPASSBOM Options:
NC
IR & Sleep LED Connector
518S0487
518S0369
NC
516S0350
518S0474
INV_SPLIT
INV_17INCH?INV_15INCH
NC
NC
PWM+5VGND
No Connect
7 24 86
QT500166-L020M-ST-SM
CRITICAL
7 24 86
23 86
23 86
PLACEMENT_NOTE=Place C9661 next to C9660
10%
0.0047uF
CERM25V
402
PLACEMENT_NOTE=Place C9660 close to southbridge
402CERM
0.0047uF
25V10%
7 46
23 86
23 86
24 86
24 86
PLACEMENT_NOTE=Place FL9660 close to southbridge
90-OHM-100MA1210-4SM1
1210-4SM190-OHM-100MA
PLACEMENT_NOTE=Place FL9665 close to J9660
PLACEMENT_NOTE=Place C9665 close to J9660
10%
CERM402
0.0047uF
25V
PLACEMENT_NOTE=Place C9666 next to C9665
402
25VCERM
10%
0.0047uF
M-RT-SM
CRITICAL
HS8806F-B
54
54
48
48
M-ST-SM
CRITICAL
QT500166-L020
45 46
7 45 46
24 86
24 86
RCLAMP0502B
SC-75
CRITICAL
81
81 82
81 82
82
82
SM04B-ACHM-RT-SM
BM02B-ACHKS-GAN-TF-LF-SN-MM-RT-SM
INV_SPLIT
SYNC_DATE=(MASTER)
051-7261 A.0.0
9280
SYNC_MASTER=(MASTER)
M76 Specific Connectors
INV_PWM_HV_VFB
INV_PWR_HV
=GND_CHASSIS_LEFTCLUTCH
INV_GND_HVKBDLED_ANODE
INV_HV_PIN5
=I2C_TOPCASE_SCL
SMC_ONOFF_L
SMC_LID
=PP5V_S3_TOPCASE
SYS_LED_ANODE
USB_IR_N
=PP5V_S3_IR
SATA_A_D2R_P
SATA_A_D2R_UF_N
SATA_A_D2R_UF_P
SATA_A_R2D_UF_P
SATA_A_R2D_UF_NSATA_A_R2D_N
SATA_A_D2R_A_PSATA_A_D2R_N
=PP3V3_S3_BT
SATA_A_D2R_A_N
=PP5V_S0_HDD
USB_BT_NUSB_BT_P
SATA_A_R2D_C_N
SATA_A_R2D_C_P
USB_TPAD_PUSB_TPAD_N
=PP3V42_G3H_LIDSWITCH
USB_IR_P
INV_P5V_HV_IFB
=GND_CHASSIS_LEFTCLUTCH
SATA_A_R2D_P
=I2C_TOPCASE_SDA
KBDLED_RETURN
=PP3V3_S3_TOPCASE
J9660
1
10
1112
1314
1516
2
34
56
78
9
C96612 1
C96602 1
FL9665
FL9660
C96662 1
C96652 1
J9610
7
8
1
2
3
4
5
6
J9600
1
10
11 12
13 14
15 16
2
3 4
5 6
7 8
9
D9600
3
1
2
J9650
5
6
1
2
3
4
J9655
3
4
1
2
80
80
44
8
44
9
8
7
91
91
91
91 86
8
8
8
9
86
8
Page 81
IN
P-CHN
S
G
D
D
S
G
N-CHN
VEE
VCC
OUT
OUT
IN
IN
IN
OUT
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
PWM does not glitch during RESET.PLT_RST_L input ensures backlight
WF:Can we remove?
WF:Why 0603?
WF:0.92V? (15")
.
x.xV reference
WF:0.5V?x.xV reference
WF:1.12V? (17")
79
SOT-563NTZD3155C
NTZD3155CSOT-563
TA75S393FSSOP-5
INV_SPLIT
15.0K
INV_SPLIT
1%1/16W
402MF-LF
3.32K
402
INV_SPLIT
MF-LF1/16W1%
INV_SPLIT
0.022UF
CERM-X5R402
16V10%
INV_SPLIT
1%
MF-LF402
1/16W
100K
INV_SPLIT
332K1/16W1%
402MF-LF
402
INV_SPLIT
68.1K1%1/16WMF-LF
INV_SPLIT
MF-LF402
1%1/16W
47.0K
INV_SPLIT
MF-LF402
1%1/16W
10K
INV_SPLIT
100K
MF-LF402
1%1/16W
INV_SPLIT
402
50V
100PF5%
CERM
50V10%
603-1X7R
0.01UF
INV_SPLIT
3.32K1%
1/16W
402MF-LF
INV_SPLIT
SOD-5231SS387
INV_SPLIT
10%
402
50VCERM
INV_SPLIT
0.0022UF
INV_SPLIT
402
1/16WMF-LF
1M1%
1%1/16W
4.7K
INV_SPLIT
MF-LF402
5%
INV_SPLIT
1/10WMF-LF603
5.1M
1SS387
INV_SPLIT
SOD-523
INV_SPLIT
402
1/16W
100K1%
MF-LF
0.015UF
X7R
10%16V
402
INV_SPLIT
1%1/16WMF-LF402
3.65K
INV_SPLIT
INV_SPLIT
1.21K
402
1%1/16WMF-LF
50V
402
5%
CERM
INV_SPLIT
100PF
MF-LF1/16W
INV_SPLIT
20.0K1%
402
INV_SPLIT
MF-LF1/16W
402
100K1%
9.09K1%
402MF-LF1/16W
INV_SPLIT
MF-LF
1%
INV_SPLIT
15.0K1/16W
402
1/16W
402MF-LF
1%
20.0K
INV_SPLIT
CERM-X5R
10%16V
402
0.022UF
INV_SPLIT
1%
INV_SPLIT
1K1/16W
402MF-LF
CERM50V
402
INV_SPLIT
100PF5%
100K
402MF-LF1/16W1%
INV_SPLIT
MF-LF402
1%1/16W
INV_SPLIT
200K
SSOPTA75W393FUINV_SPLIT
TA75W393FUINV_SPLIT
SSOP
MA3S132D0LSC81
INV_SPLIT
INV_SPLIT
SSMINI6-F1UP04601
INV_SPLIT
SSMINI6-F1UP04601
82
82
82
HN2D01FUSOT-363
INV_SPLIT
SOT-363HN2D01FU
INV_SPLIT
HN2D01FUSOT-363
INV_SPLIT
INV_SPLIT
HN2D01FUSOT-363
80 82
80 82
82
80
6.3V
603X5R
20%10UF
11.3K1%
MF-LF402
1/16W
INV_SPLIT
402
100K5%1/16WMF-LF
100K1/16W
5%
402MF-LF
79
SC70MC74VHC1G08
CERM
20%10V
402
0.1uF
9
Inverter Support
81 92
A.0.0051-7261
SYNC_MASTER=M75_LIO SYNC_DATE=01/23/2007
LCDBKLT_PWM
INV_UNNAMED_K
LCDBKLT_PWREN
=PP5V_S0_LCDBKLT
LCDBKLT_PWREN_L
INV_UNNAMED_D
PXVX_UNNAMED_A
INV_UNNAMED_J
INV_VCHOP
INV_UNNAMED_I
INV_PWM_HV_VFB
INV_P5V_HV_IFB
PP4V5_SW_VREG
INV_UNNAMED_A
INV_UNNAMED_G
INV_UNNAMED_E
INV_UNNAMED_C
INVERTER_SGND
PP4V5_SW_VREG
INV_UNNAMED_L
PXVX_UNNAMED_B
INV_LOSC
INV_PWM_R
LCDBKLT_PWM_UNBUF
INVERTER_SGND
INV_DIM
INV_DIM_DIV
INVERTER_SGND
PP5V_SW_LCDBKLT
VOLTAGE=5VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.4 mm
INV_UNNAMED_H
INV_HV_PIN5
INV_STBY
PLT_RESET_L
=PP3V3_S0_LCDBKLTR98121
2
R98251
2
C9821 1
2
R98201
2
R98131
2
R98111 2
R98141
2
C98551
2
R98541
2
R98501
2
R98551
2
R98531
2
R98511
2
C9850 1
2
C9822 1
2
D98351
2
C98201
2
R98211
2
R98351
2
R98341 2
D98451 2
R98451
2
C98451
2
R98421
2
R98431
2
R98101
2
R98321
2
R98301
2
R98331 2
C98321
2
R98311
2
C9840 1
2
R98401
2
R98411
2
U98202
3
1
8
4
U98206
5
7
8
4
D9825
3
1
2
Q9850 2
6
1
Q98505
3
4
D9850
52
D9850
61
D9850
4 3
D99304
3
C9830 1
2
R98052
1
R98061
2
U9800
3
2
1
4
5
C9800 1
2
Q9805
3
5
4
Q9805
6
2
1
U98301
3
4
5
2
82
82
82
82
82
82
82
7
8
81
81
81
81
81
7
8
Page 82
BI
BI
BI
BI
D
S
G
N-CHN
P-CHN
S
G
D
IN
IN
LOSC
TIMER
ROSC
GND
STBY
ERRV
DIM
VCHOP
VREG
FREF
FRATE
LPC
FBI
OVP
NGATE2
PGATE2
PGND
NGATE1
VCC PGATE1
D
SG
N-CHN
SD
G
P-CHN
SD
G
P-CHN
D
SG
N-CHN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
(INV_LOSC)
(PPBUS_S0_LCDBKLT_FUSED)
Split Inverter: Bridge
Split Inverter: IFB (Current Sense)
Classic Inverter: PWM
Classic Inverter: PBUS
Classic Inverter: GND
Split Inverter: Bridge
Classic Inverter: +5V
Split Inverter: VFB (Voltage Sense)
INV_BYPASS
FERR-120-OHM-1.5A
CRITICAL
0402-LF
80 81
80 81
80
80
FERR-120-OHM-1.5A
INV_BYPASS
0402-LF
CRITICAL
0.001uF
CERM402
INV_BYPASS
50V20%
22UH-2.8A-129MOHM
INV_SPLIT
IHLP2525CZ-SM
INV_17INCH
402
15.0K1/16WMF-LF
1%
603
2AMP-32V-44MOHM
SOT-563NTZD3155C
INV_SPLIT
INV_SPLIT
SOT-563NTZD3155C
INV_SPLIT
50V
402
5%
CERM
100PF
33.2
INV_SPLIT
MF-LF
1%
402
1/16W
402
INV_SPLIT
33.2
1/16WMF-LF
1%
16V
10UF
TANT
20%
INV_SPLIT
CASE-B2
1/16W
402MF-LF
1%
INV_SPLIT
205
INV_SPLIT
10%
CERM
0.001UF
402
50V
1%
MF-LF402
1/16W
39.2K
INV_SPLIT
INV_SPLIT
0.0022UF
402
50V10%
CERM1/16WMF-LF
402
5%5.1M
INV_SPLIT
INV_SPLIT
511K1/16W
402MF-LF
1%
10%25VX5R-CERM805
2.2UF
INV_SPLIT
1/16W
10M
402MF-LF
5%
INV_SPLIT
10K
1%
402
1/16WMF-LF
INV_SPLIT
1UF
INV_SPLIT
402
10%10VX5R
INV_SPLIT
0.01UF
CERM402
16V10%
1M
MF-LF402
1%1/16W
INV_SPLIT
INV_SPLIT
150K1%
402MF-LF1/16W
INV_SPLIT
64.9K1/16W
1%
402MF-LF
NOSTUFF
10UF10%
0805X5R-CERM
16V
INV_SPLIT
5%
MF-LF402
100K1/16W
1%
20
1/16W
INV_SPLIT
MF-LF402
0.0033UF
CERM50V
402
10%
INV_SPLIT
MF-LF402
1%1/16W
INV_SPLIT
10K
81
INV_SPLIT
0.0022UF
CERM402
10%50V
603-1
0.01UF
INV_SPLIT
50VX7R
10%
75K
MF-LF1/16W
402
1%
INV_SPLIT
INV_SPLIT
402X5R10V10%1UF
INV_SPLIT
4.7UF
X5R-CERM6.3V10%
603
INV_SPLIT
CERM402
10%50V
0.0027UF
INV_SPLIT
5.111%
402MF-LF1/16W
81
6.3V
2.2UF20%
402-LFCERM
INV_SPLIT
1/16W5%
10M
MF-LF402
CRITICAL
INV_SPLIT
SSOPBD9828FV
INV_SPLIT
SOT-363HN2D01FU
HN2D01FUSOT-363
INV_SPLIT
402
1/16WMF-LF
1%1.43M
NO STUFF
402
1/16WMF-LF
5%
100K
INV_SPLIT
INV_SPLIT
402
1/16W
100K
MF-LF5%
PWRPK-1212-8
INV_SPLIT
SI7501DN
PWRPK-1212-8SI7501DN
INV_SPLIT
INV_SPLIT
PWRPK-1212-8SI7501DN
SI7501DNPWRPK-1212-8
INV_SPLIT
81
81
402CERM50V
0.001uF20%
INV_BYPASS
CRITICAL
0402-LF
INV_BYPASS
FERR-120-OHM-1.5A
SM
50V
402CERM
20%0.001uF
INV_BYPASS
402CERM50V20%0.001uF
INV_BYPASS
INV_BYPASSCRITICAL
FERR-120-OHM-1.5A
0402-LF
R99321 INV_15INCHRES,11.3K,1%,1/16W,MF,402,LF114S0319
Inverter Control ICSYNC_DATE=01/23/2007SYNC_MASTER=M75_LIO
A.0.0
92
051-7261
82
MIN_NECK_WIDTH=0.25 mm
INV_NGATE1MIN_LINE_WIDTH=0.25 mm
INV_PWR_EN_DIV_L
=PPBUS_S0_LCDBKLT
INV_PWM_HV_VFB
INV_VREG_RC
INV_FREF
PP5V_SW_LCDBKLT
INV_PWR_EN_L
VOLTAGE=12.6V
PPBUS_SW_INVERTERMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.4 mm
PP5V_SW_LCDBKLT
VOLTAGE=12.6V
MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.25 mm
INV_GND_HV
MIN_LINE_WIDTH=0.4 mm
SWITCH_NODE=TRUEVOLTAGE=12.6VMIN_NECK_WIDTH=0.25 mm
INV_PWR_HV
LCDBKLT_PWM
VOLTAGE=0V
MIN_LINE_WIDTH=0.4 mmINVERTER_SGNDMIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
INV_PGATE2
INV_NGATE1_R
INV_NGATE2_R
INV_OVP
INV_FBI
INV_FRATE
INV_LPC
INV_FBI_R
=GND_CHASSIS_INVERTER
INV_P5V_HV_IFB
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.4 mmINV_UNNAMED_Z
VOLTAGE=12.6V
INV_ROSC
MIN_LINE_WIDTH=0.25 mmINV_NGATE2MIN_NECK_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
INV_PGATE1MIN_LINE_WIDTH=0.25 mm
PP4V5_SW_VREGMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=4.5V
INV_TIMER
INVERTER_SGND
INV_STBY
INV_LOSC
INV_DIM
INV_ERRV
INV_VCHOP
PPBUS_S0_INVERTER_VCCMIN_LINE_WIDTH=0.4 mm
VOLTAGE=12.6VMIN_NECK_WIDTH=0.25 mm
PPBUS_S0_LCDBKLT_FUSEDMIN_LINE_WIDTH=0.4 mm
VOLTAGE=12.6VMIN_NECK_WIDTH=0.25 mm
R99321
2
R99301
2
C99241
2
R99241
2
C99251
2
R99251
2
R99601
2
C99001
2
R99121
2
R99231 2
C99231 2
C99221
2
R99221
2
R99211
2
R99201
2
C9950 1
2
R99101
2
R99001 2
C99101
2
R99111
2
C99191
2
C9918 1
2
R99171
2
C9916 1
2
C99151
2
C9914 1
2
R99131
2
C9913 1
2
R99501
2
U9900
16
17
7
9
10
15
11
8
2
5
6
1
4
3
12
14
13
20
19
18
D9930
61
D9930
52
R99311
2
R99051 2
R99061
2
Q9950
5
4
3
Q9950
6
2
1
Q9960
6
2
1
Q9960
5
4
3
C99921
2
L9991
1 2
XW995012
C99931
2
C99941
2
L9994
12
L9993
12
L9992
1 2
C99911
2
L9950
1 2
F99001 2
Q9905
6
2
1
Q9905
3
5
4
C9932 1
2
R99611
2
R99511 2
C99511
2
82 82
81 81
81
82
9
82
8
7 7
7
81
7
81
81
7
Page 83
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
FSB (Front-Side Bus) Constraints
Design Guide recommends each strobe/signal group is routed on the same layer.
CPU Signal Constraints
Most CPU signals with impedance requirements are 55-ohm single-ended.Some signals require 27.4-ohm single-ended impedance.
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1.
DSTB complementary pairs are spaced 1:1 and routed as differential pairs.
Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs.
(See above)
(See above)
CPU / FSB Net PropertiesPHYSICAL
NET_TYPE
SPACING
DG recommends at least 25 mils, >50 mils preferred
Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs.
Design Guide recommends FSB signals be routed only on internal layers.
NOTE: Design Guide allows closer spacing if signal lengths can be shortened.
All FSB signals with impedance requirements are 55-ohm single-ended.
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.2 & 4.3
ELECTRICAL_CONSTRAINT_SET
(See above)
NOTE: 7 mil gap is for VCCSense pair, whichIntel says to route with 7 mil spacing withoutspecifying a target differential impedance.
(See above)
(FSB_CPURST_L)
=2:1_SPACING ?FSB_DATA2DATA *
7 MIL7 MILCPU_27P4S =27P4_OHM_SE=27P4_OHM_SE=27P4_OHM_SEY*
=55_OHM_SE=55_OHM_SE* =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIRFSB_DSTB_55S =1:1_DIFFPAIR
25 MILCPU_GTLREF * ?
*CPU_COMP ?25 MIL
25 MIL*CPU_VCCSENSE ?
FSB_ADDR2ADSTB * =3:1_SPACING ?
*FSB_ADSTB =3:1_SPACING ?
*FSB_ADDR2ADDR =2:1_SPACING ?
=STANDARD=55_OHM_SE=55_OHM_SE* =55_OHM_SE =STANDARDFSB_55S =55_OHM_SE
051-7261 A.0.0
9283
SYNC_MASTER=T9_NOME
CPU/FSB ConstraintsSYNC_DATE=01/25/2007
=3:1_SPACING ?FSB_DATA2DSTB *
?FSB_DSTB * =3:1_SPACING
* =3:1_SPACINGFSB_ADDR ?
FSB_COMMON * =2:1_SPACING ?
*FSB_ADSTBFSB_ADDR FSB_ADDR2ADSTB
FSB_DATA *FSB_DATA FSB_DATA2DATA
FSB_ADDRFSB_ADDR * FSB_ADDR2ADDR
FSB_DATA2DSTB*FSB_DATA FSB_DSTB
=STANDARD=STANDARDY =55_OHM_SE* =55_OHM_SE =55_OHM_SECPU_55S
CPU_ITP * ?=2:1_SPACING
?*FSB_DATA =3:1_SPACING
*CPU_2TO1 ?=2:1_SPACING
CPU_2TO1CPU_55S NB_BSEL<1>
CPU_DPRSTP_LCPU_2TO1CPU_55SCPU_DPRSTP_L
CPU_27P4S CPU_COMPCPU_COMP CPU_COMP<2>CPU_55S CPU_COMP<1>CPU_COMP CPU_COMP
CPU_55S CPU_DPSLP_LCPU_FROM_SB
CPU_55S CPU_2TO1 CPU_BSEL<0>CPU_BSEL0
CPU_FROM_SB CPU_STPCLK_LCPU_55S
CPU_COMP CPU_COMP<0>CPU_27P4S CPU_COMP
CPU_55S CPU_SMI_LCPU_FROM_SB
CPU_INIT_L CPU_INIT_LCPU_55S
CPU_55S CPU_A20M_LCPU_FROM_SB
CPU_FROM_SB CPU_55S CPU_NMICPU_FROM_SB CPU_INTRCPU_55S
CPU_PWRGD CPU_55S CPU_PWRGDCPU_55S CPU_2TO1 CPU_PROCHOT_LCPU_PROCHOT_L
CPU_55S CPU_FERR_LCPU_FERR_L
FSB_ADSTB0 FSB_ADSTB_L<0>FSB_ADSTBFSB_55S
FSB_ADDRFSB_55SFSB_ADDR_GROUP1 FSB_A_L<35..17>FSB_55S FSB_ADSTB_L<1>FSB_ADSTB1 FSB_ADSTB
FSB_ADDR FSB_A_L<16..3>FSB_55SFSB_ADDR_GROUP0
FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_N<3>
FSB_DSTBFSB_DSTB_55S FSB_DSTB_L_N<2>FSB_DSTB_55SFSB_DSTB2 FSB_DSTB FSB_DSTB_L_P<2>FSB_55S FSB_DATAFSB_DATA_GROUP2 FSB_DINV_L<2>
FSB_COMMONFSB_55S FSB_HIT_LFSB_COMMON
FSB_DINV_L<1>FSB_55S FSB_DATAFSB_DATA_GROUP1
FSB_DSTB_55S FSB_DSTB_L_P<1>FSB_DSTBFSB_DSTB1
FSB_D_L<15..0>FSB_DATAFSB_DATA_GROUP0 FSB_55S
FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_N<1>
FSB_DATAFSB_55SFSB_DATA_GROUP3 FSB_DINV_L<3>
FSB_55S FSB_COMMON FSB_BNR_LFSB_COMMON
FSB_DSTB_55S FSB_DSTB_L_P<0>FSB_DSTBFSB_DSTB0
FSB_DSTB_55S FSB_DSTB_L_N<0>FSB_DSTB
FSB_DATAFSB_55SFSB_DATA_GROUP3 FSB_D_L<63..48>
FSB_DSTB_55SFSB_DSTB3 FSB_DSTB FSB_DSTB_L_P<3>
FSB_REQ_L<4..0>FSB_55SFSB_ADDR_GROUP0 FSB_ADDR
FSB_55S FSB_COMMON FSB_DEFER_LFSB_COMMON
FSB_55S FSB_COMMON FSB_CPURST_LFSB_CPURST_L
FSB_55S FSB_COMMON FSB_HITM_LFSB_COMMON
FSB_55S FSB_COMMON FSB_DPWR_LFSB_COMMON
FSB_55S FSB_COMMON FSB_DRDY_LFSB_COMMON
FSB_55S FSB_COMMON FSB_LOCK_LFSB_COMMON
FSB_55S FSB_COMMON FSB_RS_L<2..0>FSB_COMMON
FSB_DINV_L<0>FSB_DATAFSB_55SFSB_DATA_GROUP0
FSB_COMMON FSB_BREQ0_LFSB_55SFSB_COMMON
FSB_COMMON FSB_DBSY_LFSB_55SFSB_COMMON
FSB_55S FSB_COMMON FSB_ADS_LFSB_COMMON
FSB_COMMON FSB_BPRI_LFSB_55SFSB_COMMON
FSB_55S FSB_COMMON FSB_TRDY_LFSB_COMMON
FSB_55S FSB_D_L<31..16>FSB_DATAFSB_DATA_GROUP1
FSB_55S FSB_D_L<47..32>FSB_DATA_GROUP2 FSB_DATA
CPU_55SCPU_BSEL1 CPU_BSEL<1>CPU_2TO1
CPU_BSEL<2>CPU_2TO1CPU_BSEL2 CPU_55S
CPU_IERR_L CPU_55S CPU_IERR_L
CPU_55S CPU_IGNNE_LCPU_FROM_SB
PM_THRMTRIP_L CPU_55S CPU_2TO1 PM_THRMTRIP_LFSB_CPUSLP_LCPU_55SFSB_CPUSLP_L
CPU_55SPM_DPRSLPVR CPU_2TO1 PM_DPRSLPVRIMVP_DPRSLPVRCPU_55S CPU_2TO1
CPU_GTLREF CPU_GTLREFCPU_GTLREFCPU_55S
CPU_55S CPU_2TO1 NB_BSEL<0>
CPU_COMPCPU_55SCPU_COMP CPU_COMP<3>
CPU_2TO1 NB_BSEL<2>CPU_55S
XDP_BPM_L<5>XDP_BPM_L5 CPU_ITPCPU_55S
XDP_CLK_NCLK_FSB_100D CLK_FSB
CLK_FSBCLK_FSB_100D XDP_CLK_P
XDP_CPURST_LCPU_55S CPU_ITP
CPU_55S CPU_2TO1 IMVP6_VID<6..0>
CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_NCPU_VCCSENSE
CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_PCPU_VCCSENSE
CPU_VCCSENSE IMVP6_VSEN_NCPU_27P4S
CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_P
CPU_55S CPU_ITPXDP_BPM_L XDP_BPM_L<4..0>XDP_TRST_L XDP_TRST_LCPU_ITPCPU_55S
XDP_TCK XDP_TCKCPU_ITPCPU_55S
XDP_TMS XDP_TMSCPU_ITPCPU_55S
XDP_TDO XDP_TDOCPU_ITPCPU_55S
XDP_TDI XDP_TDICPU_ITPCPU_55S
CPU_55S CPU_VID<6..0>CPU_2TO1
59 23
23
14
46
59
30
16
23
23
47
13
59
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
13
14
14
14
14
14
14
14
14
14
14
23
14
25
30
30
88
88
59
16
10
10
30
10
23
23
23
23
23
10
46
23
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
14
10
10
10
10
10
14
10
10
10
10
14
14
10
10
30
30
23
16
10
16
59
16
16
13
30
30
12
59
59
13
13
13
13
13
13
12
13
7
10
10
7
10
7
10
10
10
10
10
10
7
10
10
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
10
7
7
7
7
7
10
7
7
7
7
10
10
7
7
10
10
10
10
10
7
7
7
10
13
10
13
10
13
13
13
7
11
11
59
59
10
10
10
10
10
10
11
Page 84
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
DG Says 30 mil spacing minimum
DG Says 40 mil spacing minimum
Video Signal Constraints
PCI-Express / DMI Bus ConstraintsELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
NET_TYPE
DG Says 40 mil spacing minimum
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 7.2, 9.2 & 10.5
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 8.1 - 8.3.
CRT & TVDAC signal single-ended impedence varies by location:
CRT_HSYNC/CRT_VSYNC signals are 55-ohm +/- 15% single-ended impedence.- 55-ohm +/- 15% from second termination resistor to connector.- 50-ohm +/- 15% from first to second termination resistor.- 37.5-ohm +/- 15% from GMCH to first termination resistor.
LVDS signals are 100-ohm +/- 20% differential impedence.
CRT_SYNC 25 MIL* ?
*TVDAC TVDAC TVDAC_2TVDAC
CRT_SYNC2SYNCCRT_SYNCCRT_SYNC *
CRT_50S =50_OHM_SE =STANDARD* =STANDARD=50_OHM_SE =50_OHM_SE=50_OHM_SE
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFFDMI_100D =100_OHM_DIFF* =100_OHM_DIFF
=100_OHM_DIFF* =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFFPCIE_100D =100_OHM_DIFF=100_OHM_DIFF
SYNC_MASTER=T9_NOME
051-7261 A.0.0
9284
SYNC_DATE=01/25/2007
NB Constraints
=STANDARD* =STANDARD=55_OHM_SECRT_55S =55_OHM_SE =55_OHM_SE=55_OHM_SE
?*PCIE 20 MIL
20 MIL ?*TVDAC_2TVDAC
20 MILCRT_SYNC2SYNC ?*
?* 25 MILCRT
=100_OHM_DIFFLVDS_100D * =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
?* 25 MILTVDAC
20 MIL ?*CRT_2CRT
?*LVDS 20 MIL
* ?20 MILDMI
*CRT CRT CRT_2CRT
TV_A_DAC TV_A_DACCRT_50S TVDAC
CRT_VSYNC_RCRT_SYNCCRT_55SCRT_SYNC
TV_C_DAC TVDAC TV_C_DACCRT_50S
TV_B_DAC TVDAC TV_B_DACCRT_50S
CRT_REDCRT_50S CRTCRT_REDCRT_GREENCRT_50S CRTCRT_GREENCRT_BLUECRT_50S CRTCRT_BLUE
CRT_TVO_IREF CRT_TVO_IREFCRT
DMI_N2S_N<3..0>DMIDMI_100D
DMI_S2N DMI_S2N_P<3..0>DMI_100D DMIDMI_S2N_N<3..0>DMI_100D DMI
LVDS LVDS_IBGLVDS_IBG
LVDS_B_DATA_N<3>LVDS_100D LVDSLVDS_B_DATA3
PEG_D2R_N<15..0>PCIE_100D PCIE
PCIE PEG_D2R_C_N<15..0>PCIE_100D
PEG_R2D_C_N<15..0>PCIE_100D PCIE
PEG_R2D_C_P<15..0>PCIE_100D PCIE
LVDS_100D LVDS_A_CLK_NLVDS_A_CLK LVDS
LVDSLVDS_100D LVDS_A_DATA_P<2..0>LVDS_A_DATA
LVDSLVDS_100D LVDS_A_DATA_N<2..0>LVDS_A_DATA
LVDS_100D LVDS LVDS_A_CLK_PLVDS_A_CLK
PEG_D2R_P<15..0>PEG_D2R PCIE_100D PCIE
PEG_R2D_N<15..0>PCIE_100D PCIE
PEG_R2D_P<15..0>PEG_R2D PCIE_100D PCIE
LVDS_100D LVDS LVDS_A_DATA_N<3>LVDS_A_DATA3
LVDS_100D LVDS LVDS_A_DATA_P<3>LVDS_A_DATA3
LVDS LVDS_B_CLK_PLVDS_B_CLK LVDS_100D
LVDSLVDS_100D LVDS_B_DATA_P<3>LVDS_B_DATA3
DMI_N2S_P<3..0>DMIDMI_N2S DMI_100D
PEG_D2R_C_P<15..0>PCIE_100D PCIE
CRT_HSYNC_RCRT_SYNC CRT_55S CRT_SYNC
LVDS_100D LVDS LVDS_B_CLK_NLVDS_B_CLK
LVDS LVDS_B_DATA_P<2..0>LVDS_B_DATA LVDS_100D
LVDS_100D LVDS LVDS_B_DATA_N<2..0>LVDS_B_DATA
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Page 85
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEMTABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
DDR2 Memory Bus Constraints
Need to support MEM_*-style wildcards!
PHYSICALELECTRICAL_CONSTRAINT_SET
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
SPACING
NET_TYPE
Memory Net Properties
MEM_CLKMEM_DATA MEM_DATA2MEM*
?*MEM_DATA2DATA =1.5:1_SPACING
?=3:1_SPACING*MEM_DQS2MEM
*MEM_CLK MEM_CTRL2MEMMEM_CTRL
MEM_DQS *MEM_CMD MEM_CMD2MEM
MEM_CMD2CMDMEM_CMDMEM_CMD *
?=3:1_SPACING*MEM_CMD2MEM
?* =2:1_SPACINGMEM_CTRL2CTRL
?* =3:1_SPACINGMEM_DATA2MEM
MEM_DATA MEM_CMD2MEMMEM_CMD *
SYNC_DATE=01/25/2007SYNC_MASTER=T9_NOME
Memory Constraints
051-7261 A.0.0
9285
* =STANDARD=45_OHM_SE =STANDARDMEM_45S =45_OHM_SE=45_OHM_SE=45_OHM_SE
=55_OHM_SE =STANDARD=STANDARDMEM_55S * =55_OHM_SE=55_OHM_SE=55_OHM_SE
MEM_70D =70_OHM_DIFF=70_OHM_DIFF* =70_OHM_DIFF=70_OHM_DIFF =70_OHM_DIFF=70_OHM_DIFF
MEM_CLK MEM_CMD2MEM*MEM_CMD
MEM_CTRL *MEM_CTRL MEM_CTRL2CTRL
MEM_CTRL * MEM_CTRL2MEMMEM_DATA
MEM_CTRL2MEM*MEM_CTRL MEM_DQS
?=3:1_SPACING*MEM_CTRL2MEM
MEM_CTRL MEM_DATA2MEMMEM_DATA *
MEM_CTRL MEM_CTRL2MEM*MEM_CMD
*MEM_DATA MEM_DATA MEM_DATA2DATA
MEM_DQS *MEM_DATA MEM_DATA2MEM
MEM_CMD *MEM_DATA MEM_DATA2MEM
?MEM_CLK2MEM =4:1_SPACING* MEM_CLK MEM_CLK MEM_CLK2MEM*
MEM_DATA *MEM_CLK MEM_CLK2MEM
=85_OHM_DIFF* =85_OHM_DIFF=85_OHM_DIFFMEM_85D =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF
?*MEM_2OTHER 25 MIL
* *MEM_CLK MEM_2OTHER
MEM_CLK MEM_CTRL MEM_CLK2MEM*
?=1.5:1_SPACING*MEM_CMD2CMD
MEM_DQS MEM_CLK2MEMMEM_CLK *
MEM_CMD MEM_CLK2MEMMEM_CLK *
MEM_CTRL MEM_CMD2MEMMEM_CMD *
MEM_CLK * MEM_DQS2MEMMEM_DQS
MEM_CTRL * MEM_DQS2MEMMEM_DQS
MEM_CMDMEM_DQS MEM_DQS2MEM*
MEM_DATA * MEM_DQS2MEMMEM_DQS
MEM_DQSMEM_DQS MEM_DQS2MEM** *MEM_DQS MEM_2OTHER
**MEM_DATA MEM_2OTHER
* *MEM_CMD MEM_2OTHER
**MEM_CTRL MEM_2OTHER
MEM_CKE<1..0>MEM_CTRLMEM_45SMEM_A_CNTL
MEM_CMDMEM_55S MEM_A_CAS_LMEM_A_CMD
MEM_55S MEM_A_WE_LMEM_A_CMD MEM_CMD
MEM_A_DQ<7..0>MEM_A_DQ_BYTE0 MEM_55S MEM_DATA
MEM_A_DQ<23..16>MEM_A_DQ_BYTE2 MEM_DATAMEM_55S
MEM_A_DQ<15..8>MEM_A_DQ_BYTE1 MEM_55S MEM_DATA
MEM_A_DQ<55..48>MEM_A_DQ_BYTE6 MEM_DATAMEM_55S
MEM_DATAMEM_55S MEM_A_DQ<63..56>MEM_A_DQ_BYTE7
MEM_A_DM<1>MEM_DATAMEM_A_DM1 MEM_55S
MEM_A_DM<0>MEM_A_DM0 MEM_55S MEM_DATA
MEM_A_DM<2>MEM_A_DM2 MEM_DATAMEM_55S
MEM_A_DM4 MEM_DATAMEM_55S MEM_A_DM<4>MEM_A_DM<3>MEM_A_DM3 MEM_DATAMEM_55S
MEM_A_DM6 MEM_DATAMEM_55S MEM_A_DM<6>
MEM_85D MEM_DQSMEM_A_DQS0 MEM_A_DQS_P<0>MEM_85D MEM_DQS MEM_A_DQS_N<0>
MEM_85D MEM_DQS MEM_A_DQS_N<1>MEM_85D MEM_DQSMEM_A_DQS1 MEM_A_DQS_P<1>
MEM_85D MEM_DQS MEM_A_DQS_P<3>MEM_A_DQS3
MEM_85D MEM_DQS MEM_A_DQS_P<2>MEM_A_DQS2
MEM_85D MEM_DQS MEM_A_DQS_N<2>
MEM_85D MEM_DQS MEM_A_DQS_P<4>MEM_A_DQS4
MEM_85D MEM_DQS MEM_A_DQS_N<3>
MEM_85D MEM_DQS MEM_A_DQS_N<5>
MEM_85D MEM_DQS MEM_A_DQS_N<4>MEM_85D MEM_DQS MEM_A_DQS_P<5>MEM_A_DQS5
MEM_85D MEM_DQS MEM_A_DQS_P<6>MEM_A_DQS6
MEM_CLK_N<5..3>MEM_CLKMEM_70D
MEM_B_CNTL MEM_45S MEM_CTRL MEM_CKE<4..3>MEM_B_CNTL MEM_CS_L<3..2>MEM_45S MEM_CTRL
MEM_B_CMD MEM_B_A<14..0>MEM_55S MEM_CMD
MEM_B_CMD MEM_B_WE_LMEM_55S MEM_CMD
MEM_B_DQ<15..8>MEM_B_DQ_BYTE1 MEM_DATAMEM_55S
MEM_B_DQ<7..0>MEM_B_DQ_BYTE0 MEM_55S MEM_DATA
MEM_B_DQ<31..24>MEM_B_DQ_BYTE3 MEM_DATAMEM_55S
MEM_B_DQ<23..16>MEM_B_DQ_BYTE2 MEM_DATAMEM_55S
MEM_B_DQ<39..32>MEM_B_DQ_BYTE4 MEM_DATAMEM_55S
MEM_B_DQ<55..48>MEM_B_DQ_BYTE6 MEM_DATAMEM_55S
MEM_B_DQ<47..40>MEM_B_DQ_BYTE5 MEM_DATAMEM_55S
MEM_B_DM<0>MEM_B_DM0 MEM_55S MEM_DATA
MEM_B_DQ<63..56>MEM_B_DQ_BYTE7 MEM_DATAMEM_55S
MEM_B_DM<2>MEM_B_DM2 MEM_DATAMEM_55S
MEM_B_DM<1>MEM_B_DM1 MEM_DATAMEM_55S
MEM_B_DM<3>MEM_B_DM3 MEM_DATAMEM_55S
MEM_B_DM<5>MEM_B_DM5 MEM_DATAMEM_55S
MEM_B_DM<4>MEM_B_DM4 MEM_DATAMEM_55S
MEM_B_DM<6>MEM_B_DM6 MEM_DATAMEM_55SMEM_B_DM<7>MEM_B_DM7 MEM_DATAMEM_55S
MEM_B_DQS_P<0>MEM_B_DQS0 MEM_85D MEM_DQS
MEM_B_DQS_P<1>MEM_B_DQS1 MEM_85D MEM_DQS
MEM_B_DQS_N<0>MEM_85D MEM_DQS
MEM_B_DQS_P<2>MEM_B_DQS2 MEM_85D MEM_DQS
MEM_B_DQS_N<1>MEM_85D MEM_DQS
MEM_B_DQS_N<2>MEM_85D MEM_DQS
MEM_B_DQS_N<3>MEM_85D MEM_DQS
MEM_B_DQS_P<3>MEM_B_DQS3 MEM_85D MEM_DQS
MEM_B_DQS_N<4>MEM_85D MEM_DQS
MEM_B_DQS_P<4>MEM_B_DQS4 MEM_85D MEM_DQS
MEM_B_DQS_P<5>MEM_B_DQS5 MEM_85D MEM_DQS
MEM_B_DQS_P<6>MEM_B_DQS6 MEM_85D MEM_DQS
MEM_B_DQS_N<5>MEM_85D MEM_DQS
MEM_B_DQS_P<7>MEM_B_DQS7 MEM_85D MEM_DQS
MEM_B_DQS_N<6>MEM_85D MEM_DQS
MEM_B_DQS_N<7>MEM_85D MEM_DQS
MEM_70D MEM_CLK MEM_CLK_N<2..0>
MEM_CTRLMEM_45S MEM_CS_L<1..0>MEM_A_CNTL
MEM_45S MEM_CTRL MEM_ODT<1..0>MEM_A_CNTL
MEM_CMD MEM_A_A<14..0>MEM_A_CMD MEM_55S
MEM_CMD MEM_A_BS<2..0>MEM_A_CMD MEM_55S
MEM_CMDMEM_55S MEM_A_RAS_LMEM_A_CMD
MEM_A_DQ<31..24>MEM_A_DQ_BYTE3 MEM_DATAMEM_55S
MEM_A_DQ_BYTE4 MEM_DATAMEM_55S MEM_A_DQ<39..32>MEM_A_DQ_BYTE5 MEM_DATAMEM_55S MEM_A_DQ<47..40>
MEM_DATAMEM_55SMEM_A_DM7 MEM_A_DM<7>
MEM_A_DM5 MEM_DATAMEM_55S MEM_A_DM<5>
MEM_CLKMEM_70DMEM_A_CLK MEM_CLK_P<2..0>
MEM_DQSMEM_85D MEM_A_DQS_N<7>
MEM_CLK_P<5..3>MEM_B_CLK MEM_CLKMEM_70D
MEM_85D MEM_DQS MEM_A_DQS_P<7>MEM_A_DQS7
MEM_85D MEM_DQS MEM_A_DQS_N<6>
MEM_B_CMD MEM_B_CAS_LMEM_55S MEM_CMD
MEM_B_CMD MEM_B_RAS_LMEM_55S MEM_CMD
MEM_B_BS<2..0>MEM_B_CMD MEM_55S MEM_CMD
MEM_B_CNTL MEM_ODT<3..2>MEM_45S MEM_CTRL
33
33
33
33
33
33
33
32
33
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31
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17
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17
31
31
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31
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16
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Page 86
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.7 & 10.9
HD Audio Interface Constraints
Disk Interface Constraints
USB 2.0 Interface Constraints
DG says minimum spacing 50 mils to clocks
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
SPACINGPHYSICAL
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 10.13.2
Internal Interface Constraints
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1
SOURCE: Santa Platform DG, Rev 1.0 (#21112), Section 10.17
=STANDARD=STANDARD=55_OHM_SE=55_OHM_SE* =55_OHM_SEHDA_55S =55_OHM_SE
=STANDARD=STANDARD=55_OHM_SE =55_OHM_SE*SMB_55S =55_OHM_SE=55_OHM_SE
* =STANDARD=55_OHM_SE=55_OHM_SE =STANDARD=55_OHM_SESATA_55S =55_OHM_SE
=STANDARD=STANDARD*SPI_55S =55_OHM_SE=55_OHM_SE =55_OHM_SE=55_OHM_SE
=55_OHM_SE =55_OHM_SE =STANDARD =STANDARDIDE_55S * =55_OHM_SE=55_OHM_SE
SYNC_MASTER=T9_NOME SYNC_DATE=01/25/2007
86 92
A.0.0051-7261
SB Constraints (1 of 2)
?* 25 MILUSB_2CLK
?20 MIL*SATA
USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF
* =STANDARD =STANDARD=55_OHM_SE =55_OHM_SE =55_OHM_SEUSB_60S =55_OHM_SE
?*SMB =3:1_SPACING
?=1.8:1_SPACINGSPI *
20 MILUSB ?*
* ?=1.8:1_SPACINGHDA
*IDE ?=1.8:1_SPACING
=100_OHM_DIFFSATA_100D =100_OHM_DIFF =100_OHM_DIFF* =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
USB_90D USB USB_EXTA_MUXED_PUSB_90D USB USB_EXTA_MUXED_N
USB_EXTA USB_EXTA_PUSBUSB_90DUSB_EXTA_NUSBUSB_90D
SPI_CE_L<1>SPISPI_55S
SPI_55S SPISPI_CE_L1 SPI_CE_R_L<1>SPI_CE_L<0>SPISPI_55S
SPI_CE_R_L<0>SPI_CE_L0 SPISPI_55S
SPISPI_55S SPI_B_SO_RSPISPI_55S SPI_B_SO
SPI_55S SPI SPI_A_SO_RSPI_SO SPI_SOSPI_55S SPI
SPI_B_SI_RSPI_55S SPI
SPI_A_SI_RSPISPI_55S
SPI_SISPI_55S SPI
SPI_SI_RSPI_SI SPI_55S SPI
SPI_B_SCLK_RSPISPI_55S
SPI_A_SCLK_RSPI_55S SPI
SPI_SCLKSPISPI_55S
SMB_SB_ME_SDA SMB_ME_DATASMBSMB_55S
SPI_SCLK_RSPISPI_55SSPI_SCLK
SMB_SB_ME_SCL SMB_ME_CLKSMB_55S SMB
SMB_DATASMB_55S SMBSMB_SB_SDA
SMB_CLKSMB_SB_SCL SMBSMB_55S
USB_60S USB_RBIASUSB_RBIAS
USB USB_EXTC_NUSB_90D
USB_90D USBUSB_EXTC USB_EXTC_PUSB_90D USB USB_EXCARD_NUSB_90D USBUSB_EXCARD USB_EXCARD_PUSB_90D USB USB_EXTB_NUSB_90D USBUSB_EXTB USB_EXTB_P
USBUSB_90D USB_IR_NUSBUSB_90DUSB_IR USB_IR_PUSBUSB_90D USB_TPAD_NUSBUSB_90DUSB_TPAD USB_TPAD_PUSBUSB_90D USB_BT_NUSBUSB_90DUSB_BT USB_BT_PUSBUSB_90D USB_CAMERA_NUSBUSB_90DUSB_CAMERA USB_CAMERA_PUSBUSB_90D USB_EXTD_N
USB_EXTD USBUSB_90D USB_EXTD_PUSB_90D USB USB_MINI_N
USBUSB_90DUSB_MINI USB_MINI_P
HDA_RST_LHDAHDA_RST_L HDA_55SHDA_RST_L_RHDAHDA_55SHDA_SDIN0HDA_55S HDAHDA_SDIN0
HDA_55S HDA_SDIN_CODECHDA
SATA_RBIAS SATA_55S SATA_RBIAS
SATA_C_D2R_C_PSATASATA_100D
SATA_C_D2R SATA_100D SATA_C_D2R_PSATA
SATA_100D SATA SATA_C_R2D_C_N
IDE_PDDACK_LIDEIDE_55SIDE_CNTL
IDE_PDIOR_LIDE_PDIOR_L IDEIDE_55S
HDAHDA_55S HDA_BIT_CLK_R
SATASATA_100D SATA_B_R2D_NSATA_B_D2R SATA_100D SATA SATA_B_D2R_P
SATA_100D SATA SATA_A_R2D_C_NSATASATA_100DSATA_A_R2D SATA_A_R2D_C_P
SATA_100D SATA_B_R2D_PSATA
SATA SATA_B_D2R_NSATA_100D
IDEIDE_55S IDE_PDIORDYIDE_PDIORDY
SATA_100D SATA_A_D2R_C_PSATA
SATA_100D SATA_A_D2R_C_NSATA
IDEIDE_55SIDE_RST_L ODD_RST_5VTOL_L
SATA_100D SATA SATA_A_D2R_N
IDE_PDD IDEIDE_55S IDE_PDD<15..0>
SATA_100D SATA SATA_B_R2D_C_N
SATA_100D SATA SATA_A_R2D_NSATASATA_100D SATA_A_R2D_P
IDEIDE_PDA IDE_55S IDE_PDA<2..0>
SATASATA_100D SATA_A_D2R_PSATA_A_D2R
IDEIDE_55SIDE_IRQ14 IDE_IRQ14
IDE_55S IDEIDE_CNTL IDE_PDDREQ
IDE_PDCS IDEIDE_55S IDE_PDCS3_LIDE_PDCS IDEIDE_55S IDE_PDCS1_L
IDE_CNTL IDE_55S IDE IDE_PDIOW_L
SATA_100DSATA_B_R2D SATA_B_R2D_C_PSATA
HDA_SYNC HDAHDA_55S HDA_SYNCHDA_SYNC_RHDAHDA_55S
HDAHDA_55S HDA_SDOUT_RHDA_55S HDA HDA_SDOUTHDA_SDOUT
HDA_BIT_CLKHDAHDA_55SHDA_BIT_CLK
SATA_100D SATA_C_R2D_PSATA
SATA_100D SATASATA_C_R2D SATA_C_R2D_C_PSATA_B_D2R_C_NSATA_100D SATA
SATA SATA_B_D2R_C_PSATA_100D
SATA_C_D2R_C_NSATASATA_100D
SATASATA_100D SATA_C_D2R_N
SATA_100D SATA_C_R2D_NSATA
80
80
43
43
56
56
56
48
56
48
48
48
34
34
34
34
34
34
24
24
80
80
80
80
44
44
44
44
34
34
34
34
42
42
42
42
42
80
80
42
42
42
80
42
42
42
80
42
42
42
42
42
42
34
34
34
42
42
24
24
56
24
56
24
56
24
56
25
24
25
25
25
24
24
24
24
24
24
24
7
7
24
24
24
24
24
24
24
24
24
24
23
23
23
42
23
23
23
23
23
23
23
23
23
23
24
23
23
23
80
80
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
Page 87
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
PCI Bus Constraints
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.18.1 & 10.19
Controller Link (AMT) Constraints
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30
Ethernet (Yukon) Constraints
SOURCE: Based on Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30
PHYSICAL SPACING
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
051-7261 A.0.0
9287
SB Constraints (2 of 2)SYNC_DATE=01/25/2007SYNC_MASTER=T9_NOME
=55_OHM_SE =STANDARD=55_OHM_SE*PCI_55S =STANDARD=55_OHM_SE=55_OHM_SE
=STANDARD =STANDARD* =STANDARD12 MILS 5 MILS 300 MILSCLINK_12MIL
?*ENET_MDI 25 MILS
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFFENET_100D * =100_OHM_DIFF
?CLINK * =1.8:1_SPACING
=STANDARD=55_OHM_SE =55_OHM_SE* =55_OHM_SE =STANDARDCLINK_55S =55_OHM_SE
?*CLINK_VREF 12 MILS
?PCI =2:1_SPACING*
PCIE_FW_D2R_NPCIE_100D PCIE
PCIEPCIE_100D PCIE_MINI_R2D_C_N
PCIE_A_D2R PCIE_100D PCIE PCIE_A_D2R_P
PCIE_A_R2D_C_PPCIE_A_R2D PCIE_100D PCIE
INT_PIRQB_LINT_PIRQB_L PCI_55S PCI
INT_PIRQA_L PCI_55S PCI INT_PIRQA_L
PCI_CNTL PCI_55S PCI PCI_TRDY_L
SB_CLINK_VREF0 CLINK_VREFCLINK_12MIL SB_CLINK_VREF0SB_CLINK_VREF1 CLINK_VREFCLINK_12MIL SB_CLINK_VREF1
PCIE_ENET_R2D PCIE_100D PCIE PCIE_ENET_R2D_C_P
GLAN_COMP GLAN_COMP
CLINK_NB_RESET_L CLINK_55S CLINK CLINK_NB_RESET_LCLINK_WLAN CLINKCLINK_55S CLINK_WLAN_CLK
CLINK_WLAN_DATACLINK_WLAN CLINKCLINK_55S
NB_CLINK_VREF NB_CLINK_VREFCLINK_12MIL CLINK_VREF
CLINK_55S CLINK_WLAN_RESET_LCLINK_WLAN_RESET_L CLINK
CLINK_NB CLINKCLINK_55S CLINK_NB_DATACLINK_NB CLINK CLINK_NB_CLKCLINK_55S
ENET_100D ENET_MDI ENET_MDI_P<3>ENET_MDI
ENET_100D ENET_MDI ENET_MDI_N<3>
ENET_MDIENET_100D ENET_MDI_P<2>ENET_MDI
ENET_MDI ENET_MDI_N<1>ENET_100D
ENET_100D ENET_MDI ENET_MDI_N<2>
ENET_MDI_N<0>ENET_100D ENET_MDI
ENET_100D ENET_MDI_P<1>ENET_MDIENET_MDI
PCIE_ENET_D2R_C_NPCIE_100D PCIE
ENET_MDI_P<0>ENET_MDIENET_100DENET_MDI
PCIE_100D PCIE PCIE_ENET_D2R_C_P
PCIE_100D PCIEPCIE_ENET_D2R PCIE_ENET_D2R_PPCIE_100D PCIE PCIE_ENET_D2R_N
PCIE_100D PCIE PCIE_ENET_R2D_PPCIEPCIE_100D PCIE_ENET_R2D_C_N
PCIE_100D PCIE PCIE_ENET_R2D_N
PCIE_FW_D2R PCIE_FW_D2R_PPCIE_100D PCIE
PCIE_MINI_R2D PCIE_MINI_R2D_C_PPCIEPCIE_100D
PCIE_MINI_D2R PCIE_MINI_D2R_PPCIE_100D PCIEPCIE_MINI_D2R_NPCIE_100D PCIE
PCIE_FW_R2D_C_NPCIEPCIE_100D
PCIE_100D PCIE PCIE_B_D2R_NPCIE_B_D2R PCIE_100D PCIE PCIE_B_D2R_P
PCIE PCIE_B_R2D_C_NPCIE_100D
PCI_REQ2_L PCI_55S PCI PCI_REQ2_LPCI_GNT2_L PCI_55S PCI PCI_GNT2_L
PCI_55S PCI PCI_FW_REQ_LPCI_FW_REQ_L
PCI_CNTL PCIPCI_55S PCI_SERR_L
PCI_CNTL PCI_55S PCI PCI_PERR_LPCI_CNTL PCI_55S PCI PCI_DEVSEL_L
PCI_IRDY_LPCI_CNTL PCI_55S PCI
PCI_LOCK_L PCI_55S PCI PCI_LOCK_L
PCIE_A_R2D_C_NPCIE_100D PCIE
INT_PIRQF_LPCI_55SINT_PIRQF_L PCI
INT_PIRQE_LPCI_55SINT_PIRQE_L PCI
PCI_GNT1_L PCI_55S PCI PCI_GNT1_LPCI_REQ1_L PCI_55S PCI PCI_REQ1_L
PCI_55S PCI PCI_FW_GNT_LPCI_FW_GNT_L
PCI_C_BE_L PCI_55S PCI PCI_C_BE_L<3..0>
PCI_AD PCI_55S PCI PCI_AD<31..21>PCI_AD PCI_55S PCI PCI_PAR
PCI_AD20 PCI_55S PCI PCI_AD<20>PCI_AD19 PCI_55S PCI PCI_AD<19>PCI_AD PCIPCI_55S PCI_AD<18..0>
PCI_CNTL PCI_55S PCI PCI_STOP_L
PCI_CNTL PCI_55S PCI PCI_FRAME_L
PCIE_EXCARD_R2D_C_NPCIE_100D PCIE
PCIE_100D PCIE PCIE_A_D2R_N
PCIE_EXCARD_R2D PCIE_EXCARD_R2D_C_PPCIE_100D PCIE
PCIE PCIE_B_R2D_C_PPCIE_100DPCIE_B_R2D
INT_PIRQD_LINT_PIRQD_L PCI_55S PCI
INT_PIRQC_LINT_PIRQC_L PCI_55S PCI
PCIE_EXCARD_D2R PCIE_EXCARD_D2R_PPCIE_100D PCIE
PCIE_FW_R2D PCIE_FW_R2D_C_PPCIEPCIE_100D
PCIE_EXCARD_D2R_NPCIE_100D PCIE
34
38
35
25
25
25
37
37
37
37
37
37
37
37
35
35
35
34
34
34
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
24
24
24
24
25
25
24
23
16
16
16
16
35
35
35
35
35
35
35
35
35
35
24
24
35
24
35
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
34
34
24
24
34
34
Page 88
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Clock Signal Constraints
(CK505_CPU)(CK505_CPU)
(CK505_NB)(CK505_ITP)
(CK505_PCI2)(CK505_PCI1)
(CK505_DOT96)(CK505_DOT96)
(CPU_BSEL0)(CPU_BSEL2)
(CK505_PCI3)
(CK505_SRC2)
(CK505_SRC6)(CK505_SRC6)
(CK505_LVDS)(CK505_LVDS)
(CPU_BSEL2)
(CK505_SRC1)(CK505_SRC1)
(CK505_ITP)
(CK505_PCIF0)(CK505_PCIF1)
(CK505_NB)
CK505 SRC7 is project-specific
CK505 PCI4 is project-specificCK505 PCI5 is project-specific
PHYSICAL
(CPU_BSEL0)(CPU_BSEL2)
NET_TYPE
SPACING
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 14.1 - 14.6
ELECTRICAL_CONSTRAINT_SET
Clock Net Properties
(CPU_BSEL0)
(CK505_SRC2)(CK505_SRC3)(CK505_SRC3)
(CK505_SRC8)(CK505_SRC8)
(CK505_SRC5)(CK505_SRC4)(CK505_SRC4)
SPACING
SMC SMBus Net PropertiesNET_TYPE
PHYSICALELECTRICAL_CONSTRAINT_SET
(CK505_SRC5)
=100_OHM_DIFFCLK_PCIE_100D =100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF* =100_OHM_DIFF
10 MIL* ?CLK_SLOW
=55_OHM_SECLK_SLOW_55S =55_OHM_SE* =55_OHM_SE =STANDARD =STANDARD=55_OHM_SE
20 MILCLK_PCIE ?*
25 MIL*CLK_FSB ?
=55_OHM_SE =55_OHM_SE =STANDARD=55_OHM_SE=55_OHM_SECLK_MED_55S =STANDARD*
20 MIL*CLK_MED ?
=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF*CLK_FSB_100D
Clock & SMC Constraints
051-7261 A.0.0
9288
SYNC_MASTER=T9_NOME SYNC_DATE=01/25/2007
CLK_PCIE_100DCK505_SRC8 CLK_PCIE CK505_SRC8_PCLK_PCIE CK505_SRC8_NCLK_PCIE_100D
CLK_PCIECK505_SRC6 CLK_PCIE_100D CK505_SRC6_P
CLK_PCIE_100D CLK_PCIE CK505_SRC4_NCK505_SRC4 CLK_PCIE_100D CLK_PCIE CK505_SRC4_P
CLK_PCIE CK505_SRC5_NCLK_PCIE_100D
CLK_PCIECLK_PCIE_100D CK505_SRC6_N
CLK_PCIE_100D CLK_PCIE CK505_SRC7_N
CLK_FSB_100D CLK_FSB FSB_CLK_CPU_NCLK_FSB_100D CLK_FSB FSB_CLK_NB_PCLK_FSB_100D CLK_FSB FSB_CLK_NB_N
XDP_CLK_PCLK_FSBCLK_FSB_100D
CLK_MED_55S CLK_MED PCI_CLK33M_TPM
CLK_MEDCLK_MED_55S CK505_FSC
SB_CLK100M_DMI_NCLK_PCIECLK_PCIE_100D
CLK_PCIE_100D CLK_PCIE NB_CLK96M_DOT_PCLK_PCIE_100D CLK_PCIE NB_CLK96M_DOT_N
CLK_PCIE PEG_CLK100M_PCLK_PCIE_100D
PCIE_CLK100M_EXCARD_PCLK_PCIE_100D CLK_PCIE
CLK_PCIE_100D CLK_PCIE SB_CLK100M_DMI_PCLK_PCIE_100D CLK_PCIE PEG_CLK100M_N
NB_CLK100M_DPLLSS_NCLK_PCIECLK_PCIE_100D
CLK_MED_55S SB_CLK48M_USBCTLRCLK_MED
CLK_MED_55S CLK_MED PCI_CLK33M_SMC
CLK_MED_55S CLK_MED PCI_CLK33M_FW
CLK_MED_55S CLK_MED PCI_CLK33M_LPCPLUSCLK_MED_55S CLK_MED PCI_CLK33M_SB
CLK_PCIE_100D CLK_PCIE CK505_SRC3_N
CLK_PCIECK505_SRC5 CLK_PCIE_100D CK505_SRC5_P
CK505_LVDS CLK_PCIE_100D CLK_PCIE CK505_LVDS_P
CK505_SRC1 CLK_PCIE_100D CLK_PCIE CK505_SRC1_P
CLK_MED_55SCK505_PCIF0 CLK_MED CK505_PCIF0_CLK_ITPEN
CK505_PCI2_CLKCLK_MED_55S CLK_MEDCK505_PCI2CK505_PCI3_CLKCK505_PCI3 CLK_MED_55S CLK_MEDCK505_PCI4_CLKCK505_PCI4 CLK_MED_55S CLK_MED
CLK_MED_55SCK505_PCI5 CLK_MED CK505_PCI5_CLK_FCTSEL
CK505_SRC1_NCLK_PCIE_100D CLK_PCIE
CLK_PCIE_100D CLK_PCIE CK505_LVDS_N
CK505_DOT96_27M_NCLK_PCIECLK_PCIE_100D
CLK_MED_55S CLK_MED CK505_48M_FSA
CK505_NB CLK_FSB CK505_CPU1_NCLK_FSB_100DCK505_CPU2_ITP_SRC10_PCLK_FSBCLK_FSB_100DCK505_ITP
CLK_FSB CK505_CPU2_ITP_SRC10_NCK505_ITP CLK_FSB_100D
CK505_CPU CLK_FSB CK505_CPU0_NCLK_FSB_100D
CLK_FSB CK505_CPU1_PCLK_FSB_100DCK505_NB
CLK_MED_55S CLK_MED CK505_REF0_FSC
CK505_DOT96 CLK_PCIE_100D CLK_PCIE CK505_DOT96_27M_P
CLK_PCIE_100D CLK_PCIE CK505_SRC2_NCK505_SRC2 CLK_PCIE_100D CLK_PCIE CK505_SRC2_P
CLK_PCIE_100D CLK_PCIECK505_SRC3 CK505_SRC3_P
CLK_FSB_100D XDP_CLK_NCLK_FSB
CK505_PCI1_CLKCLK_MED_55S CLK_MEDCK505_PCI1
CK505_PCIF1 CK505_PCIF1_CLKCLK_MED_55S CLK_MED
CK505_CPU CK505_CPU0_PCLK_FSBCLK_FSB_100D
CK505_SRC7 CLK_PCIECLK_PCIE_100D CK505_SRC7_P
CLK_FSB_100D CLK_FSB FSB_CLK_CPU_P
CLK_MEDCLK_MED_55S CK505_FSA
CLK_PCIE_100D CLK_PCIE NB_CLK100M_DPLLSS_P
SB_CLK14P3M_TIMERCLK_MEDCLK_MED_55S
CLK_PCIE_100D PCIE_CLK100M_EXCARD_NCLK_PCIE
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_ENET_NCLK_PCIE_100D CLK_PCIE PCIE_CLK100M_ENET_P
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_P
CLK_PCIE_100D CLK_PCIE NB_CLK100M_PCIE_PCLK_PCIE_100D CLK_PCIE SB_CLK100M_SATA_NCLK_PCIE_100D CLK_PCIE SB_CLK100M_SATA_P
SMBUS_SMC_A_S3_SDASMBUS_SMC_A_S3_SDA SMBSMB_55S
SMBUS_SMC_A_S3_SCLSMBUS_SMC_A_S3_SCL SMBSMB_55S
SMBUS_SMC_B_S0_SCLSMBUS_SMC_B_S0_SCL SMB_55S SMB
SMBUS_SMC_0_S0_SCLSMBUS_SMC_0_S0_SCL SMB_55S SMBSMBUS_SMC_0_S0_SDASMBUS_SMC_0_S0_SDA SMBSMB_55SSMBUS_SMC_BSA_SCLSMBUS_SMC_BSA_SCL SMB_55S SMB
SMBUS_SMC_MGMT_SCLSMBUS_SMC_MGMT_SCL SMBSMB_55S
SMBUS_SMC_B_S0_SDASMBUS_SMC_B_S0_SDA SMBSMB_55S
SMBUS_SMC_BSA_SDASMBUS_SMC_BSA_SDA SMBSMB_55S
SMBUS_SMC_MGMT_SDASMBUS_SMC_MGMT_SDA SMB_55S SMB
PCIE_CLK100M_MINI_NCLK_PCIE_100D CLK_PCIE
CLK_PCIE_100D CLK_PCIE NB_CLK100M_PCIE_N
30
30
30
83
30
47
83
30
30
30
30
30
30
30
30
30
30
30
30
10
14
14
30
30
34
30
22
30
45
38
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
10
22
30
34
35
35
34
16
30
30
34
16
29
29
29
29
29
29
29
29
7
7
7
13
30
24
7
7
9
30
24
9
7
25
30
30
7
24
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
13
29
29
29
29
7
30
7
25
30
30
30
30
7
23
23
48
48
48
48
48
48
48
48
48
48
30
7
Page 89
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
FireWire Interface ConstraintsELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICAL
FireWire Net PropertiesSPACING
Port 2 Not Used
=2:1_SPACINGFW * ?
FW_TP ?=3:1_SPACING*
=110_OHM_DIFF=110_OHM_DIFFFW_110D =110_OHM_DIFF=110_OHM_DIFF=110_OHM_DIFF* =110_OHM_DIFF
*FW_55S =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD=55_OHM_SE=55_OHM_SE
SYNC_DATE=01/25/2007SYNC_MASTER=T9_NOME
89 92
A.0.0051-7261
FireWire Constraints
FW_55S FW FW_LPSFW_LPS
FW_LREQ FW_LREQFWFW_55S
CLK98P304M_FW_XI_RFWPHY_CLK98P304M_XI CLK_MEDCLK_MED_55S
FW_LINK<7..0>FWFW_55SFW_D_CTL
CLKFW_PHY_PCLKCLK_MEDCLK_MED_55S
CLKFW_LINK_PCLKCLK_MED_55S CLK_MEDFW_PCLK
CLKFW_LINK_LCLKCLK_MED_55S CLK_MEDFW_LCLK
FW_D_CTL FW_CTL<1..0>FW_55S FW
FW_LKON FW_LKONFWFW_55S
FW_0_TPA FW_TPFW_110D FW_0_TPA_N
FW_1_TPB_NFW_110D FW_TPFW_1_TPB
FW_1_TPB_PFW_110D FW_TPFW_1_TPB
CLK98P304M_FW_XICLK_MED_55S CLK_MED
FW_TP FW_0_TPB_NFW_110DFW_0_TPB
FW_0_TPA_PFW_0_TPA FW_110D FW_TP
FW_PINT FWFW_55S FW_PINT
FW_LKON_RFWFW_55S
FW_0_TPB_PFW_TPFW_110DFW_0_TPB
CLKFW_PHY_LCLKCLK_MED_55S CLK_MED
FW_1_TPA FW_1_TPA_PFW_110D FW_TP
FW_1_TPA FW_1_TPA_NFW_110D FW_TP
39
39
39
41
41
41
41
41
39
41
39
41
41
38
38
38
39
39
39
39
39
38
39
38
39
39
Page 90
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
SPACINGSPACING
SPACING
Video Signal Constraints
GDDR3 Frame Buffer Signal Constraints
(CK505_DOT96)
PHYSICALELECTRICAL_CONSTRAINT_SET
GDDR3 FB A/B Net Properties GDDR3 FB C/D Net PropertiesPHYSICALELECTRICAL_CONSTRAINT_SET
NET_TYPENET_TYPE
NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL
G84M Net Properties
GDDR3_CLK ?* =2.5:1_SPACING
GDDR3_CMD ?* =2.5:1_SPACING
?*GDDR3_DATA =2.5:1_SPACING
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF* =100_OHM_DIFFTMDS_100D =100_OHM_DIFF=100_OHM_DIFF
=50_OHM_SE =50_OHM_SE* =STANDARD=50_OHM_SEVGA_50S =STANDARD=50_OHM_SE
=55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE =STANDARD*VGA_55S =STANDARD
20 MIL* ?VGA_SYNC
=50_OHM_SEGDDR3_50SE * =50_OHM_SE =STANDARD =STANDARD=50_OHM_SE =50_OHM_SE
?*VGA 20 MIL
20 MIL* ?TMDS
?GDDR3_DQS * =2.5:1_SPACING
=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFFGDDR3_80D * =80_OHM_DIFF
=40_OHM_SEGDDR3_40R50SE * =50_OHM_SE =50_OHM_SE 12.7 MM =STANDARD =STANDARD
051-7261 A.0.0
9290
GPU (G84M) ConstraintsSYNC_MASTER=M75_MLB SYNC_DATE=01/26/2007
TMDS_CLK TMDS_CLK_NTMDSTMDS_100D
TMDS_CLK TMDS_CLK_PTMDSTMDS_100D
LVDS_U_DATA_P<3..0>LVDSLVDS_100D
LVDS_U_CLK_NLVDSLVDS_100D
LVDS LVDS_L_DATA_N<3..0>LVDS_100D
LVDSLVDS_100D LVDS_L_CLK_N
CLK_SLOW_55S CLK_SLOW GPU_CLK27M_SSCK505_CLK27MSS
GDDR3_80DFB_A_CLK_P FB_A_CLK_P<0>GDDR3_CLK
GDDR3_80D FB_A_CLK_N<0>GDDR3_CLK
GDDR3_80D GDDR3_CLK FB_A_CLK_P<1>FB_B_CLK_P
GDDR3_40R50SE FB_A_BA<2..0>GDDR3_CMDFB_AB_CMD
GDDR3_40R50SE FB_A_WE_LFB_AB_CMD GDDR3_CMD
GDDR3_50SEFB_A_CMD GDDR3_CMD FB_A_LMA<5..2>
GDDR3_DATAGDDR3_50SEFB_C_DQ_BYTE3 FB_B_DQ<31..24>GDDR3_DATAGDDR3_50SEFB_C_DQ_BYTE2 FB_B_DQ<23..16>
GDDR3_DATAGDDR3_50SEFB_C_DQ_BYTE0 FB_B_DQ<7..0>
GDDR3_40R50SE GDDR3_CMD FB_A_CS0_LFB_AB_CMD
GDDR3_40R50SE FB_A_CKEFB_AB_CMD_PD GDDR3_CMD
GDDR3_40R50SE FB_A_RAS_LGDDR3_CMDFB_AB_CMD
GDDR3_80D FB_A_CLK_N<1>GDDR3_CLK
GDDR3_DATAGDDR3_50SEFB_D_DQM3 FB_B_DQM_L<7>
GDDR3_DATAGDDR3_50SEFB_D_DQM1 FB_B_DQM_L<5>GDDR3_DATAGDDR3_50SEFB_D_DQM2 FB_B_DQM_L<6>
GDDR3_DATAGDDR3_50SEFB_D_DQM0 FB_B_DQM_L<4>
GDDR3_DATAGDDR3_50SEFB_D_DQ_BYTE3 FB_B_DQ<63..56>GDDR3_DATAGDDR3_50SEFB_D_DQ_BYTE2 FB_B_DQ<55..48>
GDDR3_DATAGDDR3_50SEFB_D_DQ_BYTE0 FB_B_DQ<39..32>GDDR3_DATAGDDR3_50SEFB_D_DQ_BYTE1 FB_B_DQ<47..40>
GDDR3_50SE FB_B_RDQS<6>GDDR3_DQSFB_D_RDQS2
GDDR3_50SE FB_B_RDQS<7>GDDR3_DQSFB_D_RDQS3
GDDR3_50SE GDDR3_DQS FB_B_RDQS<5>FB_D_RDQS1
GDDR3_50SE FB_B_WDQS<6>GDDR3_DQSFB_D_WDQS2
GDDR3_50SE FB_B_WDQS<7>GDDR3_DQSFB_D_WDQS3
GDDR3_50SE FB_B_WDQS<5>GDDR3_DQSFB_D_WDQS1
GDDR3_50SE FB_B_WDQS<4>GDDR3_DQSFB_D_WDQS0
GDDR3_DATAGDDR3_50SEFB_C_DQM3 FB_B_DQM_L<3>
GDDR3_DATAGDDR3_50SE FB_B_DQM_L<0>FB_C_DQM0
GDDR3_50SE FB_B_RDQS<2>GDDR3_DQSFB_C_RDQS2
GDDR3_50SE FB_B_RDQS<3>GDDR3_DQSFB_C_RDQS3
GDDR3_50SE FB_B_RDQS<1>GDDR3_DQSFB_C_RDQS1
GDDR3_50SE FB_B_WDQS<2>GDDR3_DQSFB_C_WDQS2
GDDR3_50SE FB_B_WDQS<3>GDDR3_DQSFB_C_WDQS3
GDDR3_50SE FB_B_WDQS<1>GDDR3_DQSFB_C_WDQS1
GDDR3_50SE FB_B_WDQS<0>GDDR3_DQSFB_C_WDQS0
GDDR3_40R50SE FB_B_DRAM_RSTGDDR3_CMDFB_CD_CMD_PD
GDDR3_40R50SE FB_B_CKEGDDR3_CMDFB_CD_CMD_PD
GDDR3_40R50SEFB_CD_CMD FB_B_CS0_LGDDR3_CMD
GDDR3_40R50SEFB_CD_CMD FB_B_CAS_LGDDR3_CMD
GDDR3_40R50SEFB_CD_CMD FB_B_WE_LGDDR3_CMD
GDDR3_40R50SEFB_CD_CMD FB_B_RAS_LGDDR3_CMD
GDDR3_40R50SEFB_CD_CMD FB_B_MA<11..6>GDDR3_CMD
GDDR3_40R50SEFB_CD_CMD FB_B_BA<2..0>GDDR3_CMD
GDDR3_40R50SEFB_CD_CMD FB_B_MA<1..0>GDDR3_CMD
GDDR3_80D FB_B_CLK_N<1>GDDR3_CLK
GDDR3_80DFB_D_CLK_P FB_B_CLK_P<1>GDDR3_CLK
GDDR3_80DFB_C_CLK_P FB_B_CLK_P<0>GDDR3_CLK
GDDR3_80D FB_B_CLK_N<0>GDDR3_CLK
GDDR3_40R50SE FB_A_MA<11..6>FB_AB_CMD GDDR3_CMD
GDDR3_40R50SEFB_AB_CMD FB_A_CAS_LGDDR3_CMD
GDDR3_50SE FB_A_WDQS<1>GDDR3_DQSFB_A_WDQS1
GDDR3_50SE FB_A_WDQS<3>GDDR3_DQSFB_A_WDQS3
GDDR3_50SE GDDR3_DQSFB_A_WDQS2 FB_A_WDQS<2>
GDDR3_50SE FB_A_RDQS<1>GDDR3_DQSFB_A_RDQS1
GDDR3_50SE GDDR3_DQS FB_A_RDQS<0>FB_A_RDQS0
GDDR3_50SE FB_A_RDQS<2>GDDR3_DQSFB_A_RDQS2
GDDR3_DATAGDDR3_50SE FB_A_DQM_L<0>FB_A_DQM0
GDDR3_DATAGDDR3_50SE FB_A_DQM_L<2>FB_A_DQM2
GDDR3_DATAGDDR3_50SE FB_A_DQM_L<1>FB_A_DQM1
GDDR3_50SE FB_A_WDQS<4>FB_B_WDQS0 GDDR3_DQS
GDDR3_50SE FB_A_WDQS<7>GDDR3_DQSFB_B_WDQS3
GDDR3_50SE FB_A_RDQS<5>GDDR3_DQSFB_B_RDQS1
GDDR3_50SE FB_A_RDQS<4>GDDR3_DQSFB_B_RDQS0
GDDR3_50SE FB_A_RDQS<7>GDDR3_DQSFB_B_RDQS3
GDDR3_50SE FB_A_RDQS<6>GDDR3_DQSFB_B_RDQS2
GDDR3_DATAGDDR3_50SE FB_A_DQ<47..40>FB_B_DQ_BYTE1
GDDR3_DATAGDDR3_50SE FB_A_DQ<39..32>FB_B_DQ_BYTE0
FB_B_DQM2 GDDR3_DATAGDDR3_50SE FB_A_DQM_L<6>
GDDR3_50SE FB_B_RDQS<0>GDDR3_DQSFB_C_RDQS0
GDDR3_50SEFB_D_CMD GDDR3_CMD FB_B_UMA<5..2>GDDR3_50SEFB_C_CMD GDDR3_CMD FB_B_LMA<5..2>
GDDR3_50SE FB_B_RDQS<4>GDDR3_DQSFB_D_RDQS0
GDDR3_DATAGDDR3_50SEFB_C_DQM2 FB_B_DQM_L<2>GDDR3_DATAGDDR3_50SEFB_C_DQM1 FB_B_DQM_L<1>
GDDR3_DATAGDDR3_50SEFB_C_DQ_BYTE1 FB_B_DQ<15..8>
GDDR3_DATAGDDR3_50SEFB_A_DQ_BYTE3 FB_A_DQ<31..24>GDDR3_DATAGDDR3_50SEFB_A_DQ_BYTE2 FB_A_DQ<23..16>GDDR3_DATAGDDR3_50SEFB_A_DQ_BYTE1 FB_A_DQ<15..8>
GDDR3_50SE GDDR3_DQSFB_A_RDQS3 FB_A_RDQS<3>
FB_B_CMD GDDR3_50SE GDDR3_CMD FB_A_UMA<5..2>
GDDR3_50SE FB_A_WDQS<0>GDDR3_DQSFB_A_WDQS0
GDDR3_40R50SE FB_A_MA<1..0>GDDR3_CMDFB_AB_CMD
GDDR3_DATAGDDR3_50SE FB_A_DQM_L<3>FB_A_DQM3
CLK_SLOW GPU_CLK27MCLK_SLOW_55S
GDDR3_DATAGDDR3_50SE FB_A_DQM_L<4>FB_B_DQM0
GDDR3_DATAGDDR3_50SE FB_A_DQ<63..56>FB_B_DQ_BYTE3
GDDR3_50SE FB_A_WDQS<6>GDDR3_DQSFB_B_WDQS2
FB_AB_CMD_PD GDDR3_40R50SE FB_A_DRAM_RSTGDDR3_CMD
GDDR3_DATAGDDR3_50SEFB_A_DQ_BYTE0 FB_A_DQ<7..0>
GDDR3_50SE FB_A_WDQS<5>GDDR3_DQSFB_B_WDQS1
GDDR3_DATAGDDR3_50SE FB_A_DQ<55..48>FB_B_DQ_BYTE2
GDDR3_DATAGDDR3_50SE FB_A_DQM_L<5>FB_B_DQM1
LVDS_U_CLK_PLVDSLVDS_100D
LVDSLVDS_100D LVDS_U_DATA_N<3..0>
VGA_50S VGA GPU_VGA_G
VGA_50SVGA_B_TV_COMP GPU_TV_COMP_VGA_BVGA
TMDS_DATA TMDS TMDS_DATA_N<5..0>TMDS_100D
VGA_R_TV_C VGA_50S GPU_TV_C_VGA_RVGA
LVDSLVDS_100D LVDS_L_DATA_P<3..0>
TMDS_DATA TMDS_DATA_P<5..0>TMDSTMDS_100D
VGA_50SVGA_G_TV_Y GPU_TV_Y_VGA_GVGA
VGA_50S VGA GPU_VGA_R
VGA_50S VGA GPU_VGA_B
VGA GPU_TV_COMPVGA_50S
VGA GPU_TV_YVGA_50S
GPU_TV_CVGA_50S VGA
VGA_SYNC GPU_VGA_VSYNCVGA_55S VGA_SYNC
VGA_SYNC VGA_SYNCVGA_55S GPU_VGA_HSYNC
GDDR3_DATAGDDR3_50SE FB_A_DQM_L<7>FB_B_DQM3
LVDSLVDS_100D LVDS_L_CLK_P
CLK_SLOW_55S CLK_SLOW GPU_CLK27M_SS_GATED
CLK_SLOW_55S CLK_SLOW GPU_CLK27M_GATED
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Page 91
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Allow 0.1 mm necks for >0.1 mm lines between thru-hole SO-DIMM pins.
Graphics Constraint RelaxationsAlternate diffpair width/gap through BGA fanout areas (95-ohm diff)
SIM Card Constraints
Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout.
Memory Constraint Relaxations
(VGA_R_TV_Y)
(VGA_B_TV_COMP)
M76 Specific Net Properties
(VGA_SYNC)
(VGA_SYNC)(VGA_SYNC)
(VGA_G_TV_C)
(USB_EXTA)
(USB_EXTA)
(USB_EXTA)(USB_EXTA)
(USB_EXTD)(USB_EXTD)
(USB_CAMERA)(USB_CAMERA)
(SATA_A_R2D)(SATA_A_R2D)
(SATA_A_D2R)(SATA_A_D2R)
(PCIE_EXCARD)(PCIE_EXCARD)
(PCIE_MINI)(PCIE_MINI)
NET_TYPE
SPACINGPHYSICALELECTRICAL_CONSTRAINT_SET
(VGA_SYNC)
I118
I119
?=STANDARDGND *
PWR_P2MM 1000* 0.20 MM
*GND GND_P2MMMEM_CTRL
GND *MEM_DQS GND_P2MM
GND_P2MMCPU_VCCSENSE GND *
GND_P2MM*FW_POWERCLK_MED
MEM_45S 0.100 MM 2.54 MM*
2.54 MMISL10 0.100 MMMEM_70D
=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SEWWAN_SIM * =50_OHM_SE =50_OHM_SE
?*WWAN_SIM =2:1_SPACING
*TMDS_100D 100_DIFF_BGA
*LVDS_100D 100_DIFF_BGA
*PCIE_100D 100_DIFF_BGA
ISL4,ISL10 0.100 MM 2.54 MMMEM_85D
MEM_70D BOTTOM 6.35 MM0.127 MM
SB_POWER PWR_P2MM*USB
GND_P2MMLVDS GND *
SATA SB_POWER * PWR_P2MM
PWR_P2MMCLK_PCIE SB_POWER *
PWR_P2MM*DMI SB_POWER
GND_P2MM*USB GND
SATA *GND GND_P2MM
GND_P2MM*GNDPCIE
GND_P2MMDMI *GND
GND_P2MM*GNDCLK_PCIE
CLINK_VREF GND * GND_P2MM
GND *CLK_MED GND_P2MM
PWR_P2MM*MEM_DATA PP1V8_MEM
*MEM_DQS PP1V8_MEM PWR_P2MM
PWR_P2MM*PP1V8_MEMMEM_CTRL
PP1V8_MEM PWR_P2MMMEM_CMD *
PWR_P2MMMEM_CLK *PP1V8_MEM
*GNDMEM_DATA GND_P2MM
MEM_CMD GND_P2MMGND *
MEM_CLK *GND GND_P2MM
GND_P2MM 0.20 MM 1000*
PP1V8_MEM =STANDARD* ?
ENET_MDI *ENET_POWER PWR_P2MM
ENET_MDI GND_P2MM*GND
CPU_GTLREF *GND GND_P2MM
CLK_FSB GND * GND_P2MM
THERM ?* =2:1_SPACING
* =2:1_SPACINGSENSE ?
* ?25 MILSENETCONN
FSB_DSTB GND * GND_P2MM
CPU_COMP GND * GND_P2MM
=1:1_DIFFPAIRTHERM_1TO1_55S =1:1_DIFFPAIR=1:1_DIFFPAIR=55_OHM_SE* =55_OHM_SE=55_OHM_SE
SENSE_1TO1_55S =55_OHM_SE* =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR=55_OHM_SE=1:1_DIFFPAIR
051-7261 A.0.0
9291
SYNC_MASTER=M76_MLB SYNC_DATE=02/02/2007
M76 Specific Constraints
FW_POWER
ENET_POWER
WWAN_SIM WWAN_SIM WWAN_SIM_DATA
VGA_HSYNCVGA_55S VGA_SYNC
VGA_50S VGA VGA_R
TMDS_DATA_F_P<5..0>TMDSTMDS_100DTMDS_DATA_F_N<5..0>TMDSTMDS_100D
TMDS_100D TMDS TMDS_CLK_F_NTMDSTMDS_100D TMDS_CLK_F_PTMDSTMDS_100D TMDS_CLK_R_N
TMDS_100D TMDS TMDS_CLK_R_P
LVDSLVDS_100D LVDS_U_DATA_CONN_N<3..0>
LVDS LVDS_U_CLK_CONN_NLVDS_100D
LVDS_100D LVDS_U_DATA_CONN_P<3..0>LVDS
LVDS_U_CLK_CONN_PLVDSLVDS_100D
LVDSLVDS_100D LVDS_L_DATA_CONN_P<3..0>LVDS LVDS_L_DATA_CONN_N<3..0>LVDS_100D
LVDS_L_CLK_CONN_PLVDS_100D LVDSLVDS_L_CLK_CONN_NLVDS_100D LVDS
LVDS_L_CLK_CONN_F_NLVDSLVDS_100D
LVDS_L_CLK_CONN_F_PLVDSLVDS_100D
THERM_1TO1_55S RSFSTHMSNS_D_PTHERM_DIFFPAIR THERM
THERM_1TO1_55S HSTHMSNS_D_PTHERM_DIFFPAIR THERM
THERM_1TO1_55S REMTHMSNS_DX_PTHERMTHERM_DIFFPAIR
THERM_1TO1_55S GPUTHMSNS_D_PTHERM_DIFFPAIR THERM
THERM_1TO1_55S GPU_TDIODE_PTHERM_DIFFPAIR THERM
THERM_1TO1_55S CPU_THERMD_PTHERM_DIFFPAIR THERM
THERM_1TO1_55S CPUTHMSNS_D2_PTHERMTHERM_DIFFPAIR
SENSE_1TO1_55S P1V25ISNS_PSENSESENSE_DIFFPAIR
SENSE_1TO1_55S P1V8ISNS_PSENSE_DIFFPAIR SENSE
SENSE_1TO1_55S NBCOREISNS_PSENSESENSE_DIFFPAIR
USB_CAMERA_F_NUSBUSB_90D
SENSE_1TO1_55S GFXIMVP6_VSEN_PSENSE_DIFFPAIR SENSE
USBUSB_90D USB_CAMERA_F_PUSB_90D USB USB_WWAN_F_NUSB_90D USB USB_WWAN_F_P
USBUSB_90D USB2_RT_NUSBUSB_90D USB2_RT_PUSBUSB_90D USB2_EXTA_MUXED_N
USB_90D USB USB2_EXTA_MUXED_P
SATASATA_100D SATA_A_D2R_UF_NSATASATA_100D SATA_A_D2R_UF_P
SATASATA_100D SATA_A_R2D_UF_NSATASATA_100D SATA_A_R2D_UF_P
FW_110D FW_TP FW_PORT0_TPB_FL_NFW_110D FW_TP FW_PORT0_TPB_FL_PFW_110D FW_TP FW_PORT0_TPA_FL_N
ENET_100D ENETCONN ENETCONN_N<3..0>
FW_110D FW_PORT0_TPA_FL_PFW_TP
ENET_MDIENET_100D ENET_MDI_R_N<3..0>ENETCONNENET_100D ENETCONN_P<3..0>
ENET_MDIENET_100D ENET_MDI_R_P<3..0>
PCIE_100D PCIE_MINI_R2D_PPCIE
PCIEPCIE_100D PCIE_MINI_R2D_N
PCIE_100D PCIE PCIE_EXCARD_R2D_NPCIE PCIE_EXCARD_R2D_PPCIE_100D
WWAN_SIM WWAN_SIM WWAN_SIM_CLOCK
SB_POWER PP3V3_S0SB_POWER PP3V3_S5
=PP1V8_S3M_MEM_BPP1V8_MEM
=PP1V8_S3M_MEM_APP1V8_MEM
VGA_VSYNCVGA_55S VGA_SYNC
VGA_55S VGA_VSYNC_RVGA_SYNC
VGA_55S VGA_HSYNC_RVGA_SYNC
VGA_50S VGA VGA_BVGA_50S VGA VGA_G
PP1V5_S0SB_POWER
GND GND
79
79
79
79
79
79
79
79
51
51
74
51
51
44
44
44
44
66
32
31
44
78
78
78
78
78
78
78
78
77
77
77
77
77
77
77
77
77
77
7
7
51
51
10
7
50
50
50
7
60
7
7
7
43
43
43
43
80
80
80
80
41
41
41
37
41
37
34
34
34
34
44
8
8
8
8
78
78
78
78
78
8
Page 92
TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_BOARD_INFO
VERSIONALLEGRO
(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
Default width/spacing is 100-ohm differential, but pairs can neck to 95-ohms without DRC.NOTE: 100_DIFF_BGA is for select 100-ohm differential pairs with routing difficulties through BGAs.
M75/M76 Board-Specific Spacing & Physical Constraints
=STANDARD* =STANDARD100_OHM_DIFF =STANDARD =STANDARD=STANDARDN * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF100_DIFF_BGA
ISL3,ISL4 Y 0.075 MM 0.125 MM100_DIFF_BGA
ISL9,ISL10 Y 0.075 MM 0.125 MM100_DIFF_BGA
0.140 MM0.085 MMISL2,ISL11 Y100_DIFF_BGA
TOP,BOTTOM Y 0.085 MM 0.140 MM100_DIFF_BGA
M75/M76 Rule DefinitionsSYNC_DATE=02/02/2007SYNC_MASTER=M76_MLB
051-7261 A.0.0
9292
*CLK_MED BGA_P2MMBGA
CLK_FSB * BGA_P2MMBGA
MEM_CLK BGA_P2MM* BGA
** BGA_P1MMBGA
BGA_P2MM*CLK_PCIE BGA
0.3 MM3:1_SPACING * ?
0.25 MM* ?2.5:1_SPACING
1.5:1_SPACING 0.15 MM* ?
1.8:1_SPACING * ?0.18 MM
FSB_DSTB BGA_P3MMFSB_DSTB BGA
CLK_SLOW * BGA_P2MMBGA
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM 15.5.1
?=DEFAULT*STANDARD
*BGA_P1MM ?=DEFAULT
BGA_P3MM ?=DEFAULT*
* ?BGA_P2MM =DEFAULT
?DEFAULT * 0.1 MM
N =STANDARD =STANDARD110_OHM_DIFF * =STANDARD=STANDARD =STANDARD
ISL3,ISL4 Y 0.077 MM 0.077 MM 0.330 MM 0.330 MM110_OHM_DIFF
90_OHM_DIFF ISL2,ISL11 Y 0.130 MM 0.130 MM 0.220 MM 0.220 MM
0.140 MM 0.140 MM 0.125 MM 0.125 MM80_OHM_DIFF ISL2,ISL11 Y
=STANDARD=STANDARD80_OHM_DIFF N =STANDARD* =STANDARD =STANDARD
TOP,BOTTOM 0.125 MMY70_OHM_DIFF 0.185 MM 0.185 MM 0.125 MM
=STANDARD*70_OHM_DIFF =STANDARD =STANDARD=STANDARDN =STANDARD
* Y =STANDARD27P4_OHM_SE =STANDARD =STANDARD0.240 MM 0.240 MM
0.185 MM0.185 MM40_OHM_SE TOP,BOTTOM Y
TOP,BOTTOM Y27P4_OHM_SE 0.335 MM 0.335 MM
TOP,BOTTOM Y50_OHM_SE 0.125 MM 0.125 MM
=STANDARD0.076 MM =STANDARD0.076 MM* =STANDARDY55_OHM_SE
=55_OHM_SEDEFAULT =55_OHM_SE 0 MM0 MM* 30 MMY
=DEFAULT=DEFAULT12.7 MM=DEFAULT=DEFAULTY*STANDARD
0.076 MM55_OHM_SE 0.250 MMISL2,ISL11 Y
TOP,BOTTOM55_OHM_SE Y 0.100 MM 0.100 MM
YTOP,BOTTOM45_OHM_SE 0.150 MM 0.150 MM
=STANDARD* Y =STANDARD =STANDARD0.090 MM 0.090 MM50_OHM_SE
4:1_SPACING 0.4 MM* ?
0.131 MM0.131 MM40_OHM_SE =STANDARD =STANDARD=STANDARDY*
=STANDARDY*1:1_DIFFPAIR =STANDARD =STANDARD 0.1 MM 0.1 MM
Y70_OHM_DIFF ISL3,ISL4 0.149 MM 0.149 MM 0.125 MM 0.125 MM
0.115 MM0.115 MM 0.125 MM 0.125 MM80_OHM_DIFF YISL3,ISL4
0.115 MM 0.115 MM 0.125 MM0.125 MM80_OHM_DIFF YISL9,ISL10
0.200 MM0.200 MM0.099 MM0.099 MMTOP,BOTTOM100_OHM_DIFF Y
90_OHM_DIFF TOP,BOTTOM 0.220 MM0.220 MM0.130 MM0.130 MMY
* 0.2 MM ?2:1_SPACING
0.330 MM0.089 MM0.089 MMISL2,ISL11110_OHM_DIFF 0.330 MMY
0.330 MM0.089 MM0.089 MM 0.330 MMY110_OHM_DIFF TOP,BOTTOM
ISL9,ISL10 0.220 MM0.220 MM0.102 MM0.102 MM90_OHM_DIFF Y
ISL2,ISL11100_OHM_DIFF 0.099 MMY 0.200 MM 0.200 MM0.099 MM
Y70_OHM_DIFF 0.185 MM 0.185 MM 0.125 MM 0.125 MMISL2,ISL11
0.125 MMY70_OHM_DIFF 0.149 MM 0.125 MMISL9,ISL10 0.149 MM
45_OHM_SE * Y =STANDARD =STANDARD=STANDARD0.105 MM 0.105 MM
0.101 MM 0.125 MMY85_OHM_DIFF 0.101 MM 0.125 MMISL9,ISL10
0.125 MM0.125 MMTOP,BOTTOM85_OHM_DIFF Y 0.125 MM 0.125 MM
=STANDARD =STANDARD85_OHM_DIFF * =STANDARD =STANDARD =STANDARDN
0.140 MM 0.140 MM 0.125 MM 0.125 MM80_OHM_DIFF TOP,BOTTOM Y
0.125 MMY85_OHM_DIFF ISL3,ISL4 0.101 MM 0.101 MM 0.125 MM
0.125 MMISL2,ISL1185_OHM_DIFF Y 0.125 MM 0.125 MM 0.125 MM
N =STANDARD =STANDARD=STANDARD* =STANDARD=STANDARD90_OHM_DIFF
0.220 MMISL3,ISL4 0.220 MM0.102 MM0.102 MM90_OHM_DIFF Y
0.330 MM0.330 MMISL9,ISL10 Y 0.077 MM 0.077 MM110_OHM_DIFF
0.080 MMY100_OHM_DIFF 0.080 MM 0.200 MM 0.200 MMISL9,ISL10
0.200 MM0.080 MM0.080 MMISL3,ISL4100_OHM_DIFF 0.200 MMY