1 1 Elec 326 Registers & Counters Registers & Counters Objectives This section deals with some simple and useful sequential circuits. Its objectives are to: Introduce registers as multi-bit storage devices. Introduce counters by adding logic to registers implementing the functional capability to increment and/or decrement their contents. Define shift registers and show how they can be used to implement counters that use the one-hot code. Reading Assignment Sections 4.4 and 5.4 2 Elec 326 Registers & Counters 1. Registers A register is a memory device that can be used to store more than one bit of information. A register is usually realized as several flip-flops with common control signals that control the movement of data to and from the register. Common refers to the property that the control signals apply to all flip-flops in the same way A register is a generalization of a flip-flop. Where a flip- flop stores one bit, a register stores several bits The main operations on a register are the same as for any storage devices, namely Load or Store: Put new data into the register Read: Retrieve the data stored in the register (usually without changing the stored data
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1Elec 326 Registers & Counters
Registers & Counters ObjectivesThis section deals with some simple and useful sequential circuits. Its objectives are to:
Introduce registers as multi-bit storage devices.Introduce counters by adding logic to registers implementing the functional capability to increment and/or decrement their contents.Define shift registers and show how they can be used to implement counters that use the one-hot code.
Reading AssignmentSections 4.4 and 5.4
2Elec 326 Registers & Counters
1. Registers
A register is a memory device that can be used to store more than one bit of information. A register is usually realized as several flip-flops with common control signals that control the movement of data to and from the register.
Common refers to the property that the control signals apply to all flip-flops in the same way A register is a generalization of a flip-flop. Where a flip-flop stores one bit, a register stores several bits The main operations on a register are the same as for any storage devices, namely
Load or Store: Put new data into the registerRead: Retrieve the data stored in the register (usually without changing the stored data
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3Elec 326 Registers & Counters
Control SignalsWhen they are asserted, they initiate an action in the registerAsynchronous Control Signals cause the action to take place immediately Synchronous Control Signals must be asserted during a clock assertion to have an effect
ExamplesOn the following three registers, which control signals are asynchronous and which are synchronous? How are the control signals asserted?
always @(posedge CLK)if (CLR) IQ <= 0;else if (LD) IQ <= D;
always @(OE)if (OE) Q = IQ;else Q = 'bz;
endmodule
8Elec 326 Registers & Counters
2. CountersA counter is a register capable of incrementing and/or decrementing its contents
Q ← Q plus nQ ← Q minus n
The definition of "plus" and "minus" depend on the way the register contents encode the integersBinary Counters: Encode the integers with the binary number code
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9Elec 326 Registers & Counters
Example: 3-bit binary counter:
What does the counter count?The output signals are just the state variables
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 0
minus
plus
•••
Count Sequence
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 0
Transistion Table
01234567
12345670
State Table
10Elec 326 Registers & Counters
Example: 3-bit binary up/down counter
Example: Binary mod 6 counter
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
1 1 10 0 00 0 10 1 00 1 11 0 01 0 11 1 0
TransistionTable
0 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 0
0 1
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0 0 10 1 00 1 11 0 01 0 10 0 0x x xx x x
Transistion Table
0 1 2
345
State Diagram
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11Elec 326 Registers & Counters
Design of a Binary Up Counter
Qi toggles on every clock cycle where Qj = 1, for i > j ≥ 0
12Elec 326 Registers & Counters
Binary Up Counter
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J Q
QK
CK
J Q
QK
J Q
QK
J Q
QK
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Design of a Binary Down Counter
Qi toggles on every clock cycle where Qj = 0, for i > j ≥ 0
14Elec 326 Registers & Counters
Binary Down Counter
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Synchronous, Series-Carry Binary Counter
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CK
Q0 Q1 Q2 Q3J Q
QK
J Q
QK
J Q
QK
J Q
QK
TW ≥ tPFF + (n-2)tPG + tsu (for n≥2)
tsu
CKTW
Q3
Q2
Q1
Q0 = JK1
Q=14 Q=15 Q=0
JK2
JK3
tPFF
tPG
tPG
16Elec 326 Registers & Counters
Synchronous, Parallel-Carry Binary Counter
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CK
Q0 Q1 Q2 Q3J Q
QK
J Q
QK
J Q
QK
J Q
QK
TW ≥ tPFF + tPG + tsu (for n≥3)
CKTW
Q3Q2
Q1Q0 = JK1
Q=14 Q=15 Q=0
JK2
JK3
tPFF
tPG
tPG
tsu
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17Elec 326 Registers & Counters
Asynchronous Counters
Typical MSI counter chip
LD and CLR are synchronousLD asserted during the rising edge of the clock loads the register from ABCD.CLR asserted during the rising edge of the clock clears the counterCLR overrides LDLD overrides ENRCO = QD•QC • QB • QA • ENT, used for cascading chips
The decoding spikes are hazzards that can not be designed outThe following circuit will mask the decoding spikes, at the cost of delaying the outputs one clock cycle.
QAQBQC
ABC
Y0Y1Y2Y3Y4Y5Y6Y7
/S0/S1/S2/S3/S4/S5/S6/S7
CK
Q0
Q1
Q2
/S0
/S1
/S2
CLK
REGQAQBQC
ABC
Y0Y1Y2Y3Y4Y5Y6Y7
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3. Shift Registers
How would you add a control signal to control when the shift register shifted?How would you add parallel input capability and why would you want to?
What kind of control signals are needed?Is the shift register drawn above a left shifter or a right shifter?How would you make a shift register that could shift either left or right and what control signals would you need?
24Elec 326 Registers & Counters
Example: 74LS194
Shift left is from A to DShift right is from D to ACLR is asynchronous
CLR
S0S1
RIN
LINDBCA
QDQCQBQA
S1 S0 QA* QB* QC* QD*0011
0101
holdshift rightshift leftload
QA RINQBA
QBQA QCB
QCQB QDC
QDQC LIND
Action
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25Elec 326 Registers & Counters
Verilog Description Of A Shift Registermodule shift4 (D, LD, LI, Ck, Q);