Reflector Design for Orthogonal Frequency (OFC) Coded Devices D.C. Malocha, D. Puccio, and N. Lobo School of Electrical Engineering & Computer Science University of Central Florida Orlando, Fl 32816-2450 Acknowledgements: Funding is provided through the NASA STTR grants with industry partners of MSA and ASRD, and through the NASA Graduate Student Research Program.
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Reflector Design for Orthogonal Frequency (OFC) Coded Devices
Reflector Design for Orthogonal Frequency (OFC) Coded Devices. D.C. Malocha, D. Puccio, and N. Lobo School of Electrical Engineering & Computer Science University of Central Florida Orlando, Fl 32816-2450. - PowerPoint PPT Presentation
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Reflector Design for Orthogonal Frequency (OFC) Coded Devices
D.C. Malocha, D. Puccio, and N. LoboSchool of Electrical Engineering & Computer Science
University of Central Florida
Orlando, Fl 32816-2450
Acknowledgements: Funding is provided through the NASA STTR grants with industry partners of MSA and ASRD, and through the NASA Graduate Student Research Program.
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.80
0.2
0.4
0.6
0.8
Normalized Frequency
Mag
nit
ude (
Lin
ear)
Schematic of OFC SAW ID TagBackground: OFC Bit – 7chips/bit
Piezoelectric Substrate
f1 f4 f6 f0f2 f5 f3
0 1 2 3 4 5 6 71
0.5
0
0.5
1
Normalized Time (Chip Lengths)
Chip length
Bit Length
Approach
• Study a methodology to optimize reflective structures for OFC devices– Minimize device insertion loss– Find optimum values for bit length, chip
length, and strip reflectivity as a function of device fractional bandwidth
– Maintain processing gain– Minimize ISI effects
Boundary Conditions for Analysis
• Assume only a single in-line grating analysis.
• Assumes no weighting within each reflective region which composes a chip.
• First order assumptions are made to understand the phenomenon and then verified by COM models and simulation.
• Multiple parallel tracks can be approached in a similar manner.
SAW OFC Reflector Coding
• Ideal OFC code using a SAW reflective structure assumes that the ideal chip can be accurately reproduced by a reflector– Chip frequency response: Sin(x)/x – Chip time response: – Uniform amplitude of chips for maximum coding,
processing gain (PG) and correlation output
)Rect(t/ chip
Intra-chip & Inter-chip Reflector Considerations
• Chip reflector uniformity
• Processing gain
• Coding diversity
• Orthogonality of chips
• Frequency & time domain distortion
• Intersymbol interference (ISI)
OFC Reflector Bank Uniformity
cNc* cf
0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2-35
-30
-25
-20
-15
-10
-5
0OFC Reflector Responses
Normalized Frequency
Re
fle
ctio
n M
ag
nitu
de
(d
B)
f1 f4 f6 f0f2 f5 f3
constantc fc=chip frequency determined by orthogonality
As fc increases, Nc increases and chip reflectivity increases
Response of Reflector Test Structure
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-80
-70
-60
-50
-40
-30
-20
-10
Time (s)
dB
(s 21
)
Direct SAW response
Reflector response
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-80
-70
-60
-50
-40
-30
-20
-10
Time (s)
dB
(s 21
)
Direct SAW response
Reflector response
64 65 66 67 68 690
0.1
0.2
0.3
0.4
0.5
Frequency ( MHz )
| R |
Measured responsePredicted-fit
Under proper conditions, a SAW reflector looks similar to a Sampling function in frequency and a Rect function in time. Reflectivity is a function of the substrate and reflector material, reflector film thickness, substrate coupling coefficient and line-to-width ratio. The reflector width is approximately the chip length. How approximate is it???
Simulation of a reflector grating frequency response for 1% reflectivity per strip, and 4 different grating lengths. Ng equals the number of reflective strips in each grating.
Frequency Transmission vs Reflectivity as a Function of Frequency Offset
0 2 4 60
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
rNg
Tra
nsm
issio
n c
oe
ffic
ien
t, T
ad
j
Low center frequencies
fref = f0 - 1-1
fref = f0 - 2-1
fref = f0 - 3-1
0 2 4 60
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
rNg
Tra
nsm
issio
n c
oe
ffic
ien
t, T
ad
j
High center frequencies
fref = f0 + 1-1
fref = f0 + 2-1
fref = f0 + 3-1
• COM simulations used to determine non-synchronous reflector transmission coefficient
• Analysis performed for reflector center frequencies 1,2,3 orthogonal frequencies higher and lower than incident wave
fSAW is the synchronous reflector of interest
is a prior asynchronous reflector in bank
nf
For 90% transmission, r*Ng<2
Adjacent Frequency Reflector Transmission Example
f3 f6 f4 f7 f1 f5 f2
SAW Substrate
Reflectors
f3f6 f4f7 f1f5 f2
1 02 23 04 15 26 07 1
Sum 6
Interrogation Frequency
Adjacent Frequency Interactions
Independent of the OFC frequency code sequence, the sum of the adjacent frequency interactions is always equal to Nf-1, but the interactions for a given frequency is code dependent.
Total Reflected OFC Power- Simple Model
– Ptot= total output power
– Tadj=adjacent center frequency transmission
– Ro=chip reflectivity– r= electrode
reflectivity– Ng= # of reflector
chip electrodes– Nf= # of frequencies
2 2 4 4 20 0
1
1 1 1B
b btot adj f adj
b
P R R T N T
2
1.40 2
1.437 tanh 0.3771 2
tanh 0.3771 2
g g
g g
r N r NR
r N r N
%f
g
NN
BW
2
6.231gr N
adjT e
Equations defined to relate several OFC reflector bank parameters, (approximate and empirically derived)
Chip Correlation with Synchronous Interrogator Pulse
1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 150
40
30
20
10
0Correlation for Ng*r=.25Ideal Correlation
Relative Time (Normalized to Ng*r)
Mag
nitu
de (
dB)
3 2 1 0 1 2 350
40
30
20
10
0Correlation for Ng*r=1.0Ideal Correlation
Relative Time (Normalized to Ng*r)
Mag
nitu
de (
dB)
Correlation is greater than ideal, IR length is near ideal and sidelobes are low.
Correlation is greater but sidelobes apparent due to intra-chip-reflections
1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 150
40
30
20
10
0Correlation for Ng*r=.25Ideal Correlation
Relative Time (Normalized to Ng*r)
Mag
nitu
de (
dB)
3 2 1 0 1 2 350
40
30
20
10
0Correlation for Ng*r=1.0Ideal Correlation
Relative Time (Normalized to Ng*r)
Mag
nitu
de (
dB)
Chip Correlation with Adjacent Frequency Asynchronous Interrogator Pulse
Near ideal response.
Cross correlation shows null at chip center, as expected due to OFC properties.
Cross correlation shows reduced null at chip center, and trailing correlation sidelobe distortion.
Measured Device Example
• fo= 250 MHz
• %BW=28%; BW=69 MHz
• YZ LiNbO3, k2=.046, r~3.4%
• (# frequencies) = (# chips) =7
• # of reflectors at fo = 24
• Ng*r ~ .72
• Chip reflector loss~4dB
nsec 98~c
COM Simulation versus Experimental Results – Time Domain Reflections
COM Predictions
Experimental Measurement
Piezoelectric Substrate
f1 f4 f6 f0f2 f5 f3f1f4f6f0 f2f5f3
Dual delay OFC device having two reflector banks and 7 chips/bank
For Ng*r ~ .72, chips are clearly defined, ISI is minimal, predictions and measurements agree well
COM Simulation versus Experimental Results - Correlation
4 6 8 10 12 14 16 18-50
-40
-30
-20
Time Normalized to a Chip Length
Mag
nitu
de (
dB) Ideal Compressed Pulses
4 6 8 10 12 14 16 18-50
-40
-30
-20
Time Normalized to a Chip Length
Mag
nitu
de (
dB) Simulated Compressed Pulses
4 6 8 10 12 14 16 18-50
-40
-30
-20
Time Normalized to a Chip Length
Mag
nitu
de (
dB) Experimental Compressed Pulses
Dual delay OFC device having two reflector banks and 7 chips/bank
Piezoelectric Substrate
f1 f4 f6 f0f2 f5 f3f1f4f6f0 f2f5f3
For Ng*r ~ .72, ideal, COM predictions, and experimentally measured autocorrelation results agree well
General Results and Conclusions
• Various OFC chip criteria were investigated to provide guidance in choosing optimal design criteria.
• The ISI and pulse correlation distortion appear to be a limiting or controlling factor for maximizing the chip reflectivity and suggests Ng*r<1.
• For Ng*r=1, chip reflector loss is approximately 2.5 dB.
• Based on reflective power predictions and simulations, the largest number of chip frequencies should be between 10 and 15, with the precise number of frequencies dependent on the bit fractional bandwidth and strip reflectivity.