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Simple and Accurate Circuit Models for High-Impedance Surfaces Embedded in Printed Circuit Boards

*Shohrooz Shahpnmlo'. ' and Dmor M. Romahi'.'.' 'Electrical ond Compurer Engineering Deporhenl. 'Mechanical Engineering Depnrmonl. ond

'CALCE Electronic Pmducls ondSvrrems Cenler, A. James Clark School ofEnglneering. Universlly ofMqsland, College Park, MO 20742, USA

hrto://llr.renme.I,,ndedu/EMCPL

Abstract In recent sNdies, High-Impedance Surfaees (HIS) also known as Elecuomagnctic Bandgap Smclwes (EBG) have been successfully employed to suppress Simultaneous Switching Noisc (SSN) generated between power busses of pnnted circuit boards (F'CB). HIS swclwes, when embedded in a PCB, can suppress elsctromagnetic wave propagation within a prsdictable range of frequencies. In this papa, B highly-accurate model for HIS smclwes embedded in PCBs is presented. This circuit i s then added to a physics-based model for power busses of PCB's, ereating a compact 3 0 madel to represent the power bus together with Embedded HIS (EHW smCNres. The circuit models presented allow for accurate prediction of the center frequency and bandgap of the EHlS without a priori full-wave modeling a f a singe or multiple cells.

I. INTRODUCrION With the increase in operating frequency af devices and switching speed of digital devices

within sub-nanoseconds, cleceomagnetic interference and radiation have become a major concern, affecting the integrity of electronic system. This electromagnetic interference, also know as switching noise, is due to high-speed time-varying currenls needed by high-performance digital circuits. The tlow of high-speed time varying mmen13, thmugh vias between layers of a multilayer pnnted circuit board (PCB), causes radiation. Electromagnetic waves generated by these SWICCS of noise use the parallel-plates to pmpagate and lherefore induce noise on other power-consuming devices connected IO the pawer bus s well as other signals passing thmugh the pawer bus.

Figure 1 (a) shows a general schematic for the generation of switching noise within a power bus of a PCB. A high-speed or high-power (or bath) logic gate that consume$ power from hvo parallel power planes generates switching noise that affects other devices that rely on these planes far their power as well as signals that pass through the power planes without being connected lo any ofthem.

Switching noise mitigation in PCB's ConsistS ofproviding a low-impedance path betwen the planes of the power bus for high frequency signals. Previous methods include, using decoupling capacitors connected between the power bus condunon and employing embedded capacitance, by reducing the distance between the conductors of such power planes and employing dielectric materials with high permittivity between these planes. fwfher improvement has been achieved by changing the usual dielectric material with one thd h s higher pehttiviw, cansing higher capacitance.

In re~enl soudies, High-Impedance Surfaces (HIS) h u e been successfully employed to suppress switching noise in PCB's [I]-[3]. Their SUCC~ES is due to the fact that their effectiveness is not limited to low frequencies as in decoupling capacilors. funhemore, embedded HIS stmclwes (EHIS) in PCB's are not as expensive as embedded capacitance since they relies on c h a p circuit printing technologies. In addition, EHlS ~1tllcNres provide a high degree of attennation over a wide range of hrquencies in which SSN has most of its energy [I]-[3].

These previous works, in their design stages, relied mainly on full-wave simulation or on circuit models onginally developed assuming open stmclwe~ (HIS over B conductive plane) and normal incident waves. Since the available circuit models are not applicable to the case of EHlS StTUCNm and full wave simulations are slow and cam01 he easily integrated in iterative design processes a new effective and accurate model needs to be defined. In this sNdy, we inmduce a quanutative relatiomhip between geomefical parameters of a power bus with EHlS smcNres and

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an equivalent lumped elements circuit. This equivalent circuit facilitates power bus design with EHlS smcmes. In fact, the circuit model presented here can also be used ih simulating power bus smcms together with other circuitry in eonvcntional circuit simulators during CAD layout to speed up the design process.

11. PCBs WITH EMESEDDEDHIS STRUCTURES Figure I (b) shows a lateral view of B rypisal HIS ~mcws, the simplest ofthcm, which is

charactenzed by periodic vias (with radius rv) connected together though a conductive (metallic) surface, and metallic squared patches on the top ofthese vias. A second metallic plate an the top ofthis smcme represen& the second power plpne. The size of these patches is SP x Se and they us separated by gaps of size S, fram each other and by a via of length h. from the plane that they arc connected to. The smcwe is periodic with period (Sp + S,) and it is located between two parallel metallic plate^. These plates are 2h, distant from each other. The whale smcme, ace as a band-stop filter by suppressing all propagating waves within a predictable range of frequencies. This frequency range is a function ofthe geometrical feawes ofthe s m c k (sufh as periodicity, patch size, gap size, via diameter, via length and also board thickness) as well as the dielectric material used in PCB as substrate.

III.HISELPMENT MODELING FOR ACCURATE B ~ O C A P PREDICTION A . Modeling the HIS nil cell

In this section we introduce a compact circuit model for each HIS unit cell. The main advantags of this modular appmacb is that it cm be extended to any new HIS unit cell design. A unit sell in PCB-embedded-HIS s h c N r e s is composed of a metallic patch and a via at the center of the patch. Figvrs 1 @) shows an equivalent cirmit for this cell when located between two metallic parallel plates (the pawer bus).

In this model, capacitor CI denotes the capacitance between the metallic patch and the top plate, inductor LI i s the inductance ofthe via and capacitor C2 is the capacitance between the patch and the boltam plate. The series-resonance frequency ofthis circuit is

1

fe = 2xJ-

In m n t applications that employ EHlS srmcwes the patch is usually laeated a1 an equal distance from both power bus planer and many approximate equations are available for the indwtance of the via (LI). The moat widely used one is given in [4]. Therefore,

with the c~nstant a equal to -0.15. This equation is valid only for large values of h., h, >z r, and much lower frequencies at which the skin effect can be neglected. The constmt a cannot be uniquely defined Since it depends an the length ofthe via. For a via with length of 1.54 mm, radius of0.4 mm by using a separate HFSS Simulation we denved o to be -0.1. This modification takes also in account the frequency-dependent resistance of the via, due to skin effects. The resulting resonance frequency represents the center frequency of the stopband region of an HIS srmchxe employing this type of unit cell. In fact, each unit cell provides high-frequency low-path impedance between the parallel-plater at this resonance frequency. Unit cells when combined together to form a full HIS s m c w e affect each other by shifting their resonance frequency, therefore creating a stop-band region. B. Comporiron between modelandsimulariom

In order to validate the model, its predicted re~onan~e frequency was compared to full-wave simulations using HFSS (a commercial CAD tool by AnroR Co.). In Fig. 2 (a) the results are comoared in HIS smchres with variable oatch sizes (C, chaneesl. In Fie. 2 (bl the results are . ~~~ ~ ~ . . . , ~ E ~ , ~ I compared while the radius ofthe via changer (L, changes). All the ather design parameters fixed throughout the simulations.

were

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Fig. 2. changes. (bj Comparison of resonance frequency of the model and simulation^ while the via radiuschanges. (h .=1 .54~S,=10mm,~=4.1 ,a=-0 .1)

(a) Comparison ofresonance frequency of the model and simulations while the patch size

IV. LUMPEPELEMENTlD MODELFORPCB'SWITN EMBEDDED-HIS A . Incorporatinp the HIS unit cell in parollel-plate models

The model developed for HIS unit cells c m be incorporated into a physics-based model for power planes in printed circuit boards. In Fig. 3 (aj, a three dimensional view of a HIS unit cell is shown. The top and honam planes represent the power bus and the plane in the middle i s the HIS patch, connected to the bottom plane through a via. Cl, C2 and LI represent the model introduced in the previous Section. Each of the capacitors C3-C6 i s Wice the capacitance between adjacent patches, so that when the unit cell is connected to a neighboring cell the equivaIcn1 capacitance would be the capacitance between the two patches. This capacitance can be calculated using m approximate equation given in [ 5 ] assuming that the effective length of the patch is equal to the gap Size. This is due to the presence ofthe top plate. Inductors L3-L6 are sheet inductances ofhalf ofthe ponion of the top plate located on the top of the patch. Therefore

2s E E C -&cosh-'(3j,and L,, =$S,. (3)

x 1-1 -

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B. Comparison between model. simulalions and erperimenlr

In order to validate this model, several cells of the compact 3D model are cascaded in a ZD fashion to build a model for the full power plane. Component values are dnivrd by analytical and approximate equations. The result of simulating this circuit is then compared to full-wave simulations done using HFSS and measurement on a fabricated PCB with EHIS smcNn. Figure 3 (b) illusuates this comparison for a smcNre with Sp = IO m.

(a) (b)

Fig. 3. (a) HIS unit cell model merged with a power bus circuit model. A 2D array of Ulese cells repre~ent~ the whole power bus. @) Comparison the model, simulations using HFSS and expc~mentalmeasuremenur.(h,=1.54Mn,S,=10mm,+=4.1,~=-0.1,r,=0.4m)

A good apemen1 between simulation, experiments and the result from the model show the high degree of reliability of the model to predict the gap of the smcture.

I t should be noted that, since the model used for the power bus is inherently B low-pass model, the resulting 3D compact model inherits this limitation and it is valid only in the range from DC to 4 GHz. Furthermore, The model for the unit cell presented in the previous Section is not limited U) this frequency range and as shown in Fig. 2, it is able to have good predictions at far higher frequencies.

v. CORCL"Sl0N In this shldy, we introduce a quantitative relationship between geameuical p m e t e n of a

power bus with embedded HIS and equivalent simple circuits based on lumped elements. Simulation and experiment results r e ~ e a l the high accuracy of the models. These simple models c m be used to design embedded HIS structures by predicting their resonance frequency. They can also be used in simulating power bus smchres together with other circuim in conventional circuit simulators during the design to speed up the process therefore facilitating power bus design with embedded HIS.

[I]. T. Kamgaing, 0. M. Ramahi, "A novel power plane with integrated simultaneous switching noise mitigation capability using high-impedance surfaces; IEEE Microwove and Wireless Componenls Lelters. Vol. 13. No./. pp. 21-23, Jan. 2003. [Z] R. Abha", G.V.Eleflheriades, "Suppression of parallel-plate noise in high-speed circuits using a metallic eleceomagnetic bandgap ~mcture." Proc. o/IEEE MTT-S lnfemationol Microwme Symposium, Philodelphio, PA, USA, IO-IZJune2003. Vol. 1. pp. 587-590. [3] S . Shahpamia, 0. M. Ramahi, "Simultaneous switching noise mitigation in high-speed printed circuit boards using cascaded high-impedance surfaces:' 4 8 IEEE Midwe11 Symposium on Circuill andSyslem, Cairo. Egypt. 28-30 Dec. 2003. [4] F.W. Grover, Induclonce Calculalionr: Working/ormular and rabler. New York, Dover 1962. [SI D. F. Sievenpiper, High-impedance eleclromagnelic sur/aees. Ph.D. Thesis, Depamnent of Electneal Engineering, UCLA, Los Angeles, CA, 1999.

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