[Electronics Lab : 15 EEL 38] 2017-18 Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 1 Experiment No. : 1 Date: ___/____/_______ Rectifiers and Filters Aim : To design and testing of Full wave – centre tapped transformer type and Bridge type rectifier circuits with and without Capacitor filter. Determination of ripple factor, regulation and efficiency Apparatus Required : Sl. No. Particulars Range Quantity 1. Transformer As per design 01 2. Diode (BY 127) - 04 3. Resistors & Capacitors As per design - 4. Multimeter - 01 5. CRO Probes - 2 Set 6. Spring board and connecting wires - - Theory: Rectifier is a circuit which converts AC to pulsating DC. Rectifiers are used in construction of DC power supplies. There are three types of rectifiers namely Half wave rectifier, Center tap full wave rectifier and bridge rectifier. In half wave rectification, either the positive or negative half of the AC wave is passed, while the other half is blocked. Because only one half of the input waveform reaches the output, it is very inefficient if used for power transfer. A full-wave rectifier converts the whole of the input waveform to one of constant polarity (positive or negative) at its output. Full-wave rectification converts both polarities of the input waveform to DC (direct current), and is more efficient. Fullwave rectification can be obtained either by using center tap transformer or by using bridge rectifier. The output of a rectifier is not a smooth DC it consists of ac ripples therefore to convert this pulsating DC in to smooth DC we use a circuit called filter. There are many types of filters like C filter, L filter, LC filter, multiple LC filter, filter etc.. of all these C filter is the most fundamental filter.
86
Embed
Rectifiers and Filters - Welcome To Channabasaveshwara … · · 2017-09-21Rectifiers and Filters Aim : To design and testing of Full wave –centre tapped transformer type and
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 1
Experiment No. : 1 Date: ___/____/_______
Rectifiers and Filters
Aim : To design and testing of Full wave – centre tapped transformer type and Bridge type rectifier circuits
with and without Capacitor filter. Determination of ripple factor, regulation and efficiency
Apparatus Required :
Sl.
No. Particulars Range Quantity
1. Transformer As per design 01
2. Diode (BY 127) - 04
3. Resistors & Capacitors As per design -
4. Multimeter - 01
5. CRO Probes - 2 Set
6. Spring board and connecting wires - -
Theory:
Rectifier is a circuit which converts AC to pulsating DC. Rectifiers are used in construction of
DC power supplies. There are three types of rectifiers namely Half wave rectifier, Center tap full
wave rectifier and bridge rectifier.
In half wave rectification, either the positive or negative half of the AC wave is passed, while
the other half is blocked. Because only one half of the input waveform reaches the output, it is very
inefficient if used for power transfer.
A full-wave rectifier converts the whole of the input waveform to one of constant polarity
(positive or negative) at its output. Full-wave rectification converts both polarities of the input
waveform to DC (direct current), and is more efficient. Fullwave rectification can be obtained either
by using center tap transformer or by using bridge rectifier.
The output of a rectifier is not a smooth DC it consists of ac ripples therefore to convert this
pulsating DC in to smooth DC we use a circuit called filter. There are many types of filters like C
filter, L filter, LC filter, multiple LC filter, filter etc.. of all these C filter is the most fundamental
filter.
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 2
VDC
Circuit Diagram:
Full wave rectifier
a) Center tap FWR without filter b) Center tap FWR with „C‟ filter
a) Bridge Rectifier without filter b) Bridge Rectifier with „C‟ filter
Vi
Vm
2 t
Vo without filter
Vm
2 t Vo with „C‟ filter
Vrpp
VDC
2 t
D2
Vm
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 3
Design :
a) Center Tap Full Wave Rectifier / Bridge Rectifier Without filter
VDC = 2Vm / for FWR ( both center tap and bridge rectifier )
For the given VDC calculate Vm and Vrms = Vm / 2
Procedure :
1. Components / Equipment are tested for their good working condition
2. Connections are made as shown in the circuit diagram
3. Observe different waveforms on CRO
4. Measure VDC using multimeter in dc mode and Vm on CRO
5. Calculate Vrms from Vm using formula Vrms = Vm / 2 for Half wave rectifier Vrms = Vm /
2 for full wave rectifier
6. Calculate the efficiency, ripple factor and regulation. Compare the results with the theoretic
Choose the transformer of rating Vrms – 0 – Vrms / ≥ IDC for Center tap full wave rectifier and 0 –
Vrms / ≥ IDC for Bridge rectifier
The value of load resistance, RL = VDC / IDC, PRL = VDC2 / RL
b) Full Wave Rectifier with „C‟ filter
VDC = Vm – ( IDC / 4fC )
= 1 / ( 4 3 fCRL ) ( f = 50 Hz )
For the given value of VDC and IDC Calculate RL = VDC / IDC, PRL = VDC2 / RL
For the given Calculate the value of capacitor „C‟
For the given value of VDC and IDC Calculate Vm and Vrms = Vm / 2
Choose the transformer of rating,
Vrms – 0 – Vrms / ≥ IDC for Center tap full wave rectifier and 0 – Vrms / ≥ IDC for Bridge rectifier
Choose the capacitor of value C / ≥ Vm
Example - 1: Design an FWR for an output DC voltage of 10 V and load current of
10 mA. (Bridge and Center tap rectifier)
VDC = 10 V
Vm = (VDC X ) / 2 = 15.7 V
Vrms = Vm / 2 = 11.1 V 12 V
Choose a transformer of rating 12V – 0 – 12V / ≥ 10 mA for Center tap full wave rectifier
Choose a transformer of rating 0 – 12V / ≥ 10 mA for Bridge rectifier
RL = VDC / IDC = 1 K
PRL = VDC2 / RL = 0.1 W
Choose RL = 1 K / 0.1 W
Example – 2 : Design a full wave rectifier for VDC = 16 V, IDC = 16mA, = 0.006 (Bridge and
center tap rectifier)
RL = VDC / IDC = 1 K, PRL = VDC2 / RL = 0256 W
From = 1 / ( 4 3 fCRL ), C = 481 f, ( 470f ) ( f = 50 Hz )
From VDC = Vm – ( IDC / 4fC ), Vm = 16.17 V, Vrms = 11.43 V, ( 12 V )
Choose transformer of rating 12V - 0 – 12V / ≥ 16mA for center tap full wave rectifier
and 0 – 12V / ≥ 16mA for bridge rectifier
Choose RL = 1 K / 0.256 W, C = 470 f / ≥ 16.17V
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 5
Tabular Column :
Without filter
Circuit VDC Vm Vrms =VDC2
/ Vrms2
= (Vrms2
/ VDC2)-1
Center tap full
wave rectifier
Bridge
Rectifier
Note : Vrms = Vm / 2 for Half wave rectifier Vrms = Vm / 2 for full wave rectifier
With filter :
Circuit VDC
full load Vrpp Vrrms
VDC
no load
%
Regulation = Vrrms / VDC
Center tap full
wave rectifier
Bridge
rectifier
Note : Vrrms = Vrpp / 23
% Regulation = ( VDC no load – VDC full load ) / VDC full load
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 6
Experiment No. : 2 Date: ___/____/_______
Simplification and Realization of Boolean Expression using logic gates/Universal
gates
Aim: Simplify and realize the given Boolean expressions using Logic Gates/Universal Gates
Apparatus:
Sl No Particulars Quantity
1 IC 7408,IC 7432 2 each
2 IC 7400,IC 7402 2 each
3 IC 7410 1
Theory:
Canonical Forms (Normal Forms): Any Boolean function can be written in disjunctive
normal form (sum of min-terms) or conjunctive normal form (product of max-terms).A Boolean
function can be represented by a Karnaugh map in which each cell corresponds two minterm. Sum of minterms : Sum Of Product (SOP) Product of maxterms : Product Of Sum (POS)
Procedure: 1. Verify that the gates are working.
2. Construct a truth table for the given problem.
3. Draw a Karnaugh Map corresponding to the given truth table.
4. Simplify the given Boolean expression manually using the Karnaugh Map.
A. Implementation Using Logic Gates 1. Realize the simplified expression using logic gates.
2. Make connections as per the logic gate diagram.
3. Apply the different combinations of input according to the truth tables.
4. Verify that the results are correct.
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 7
1) Y1=(A+BC)(B+A C ) using Basic Gates
Simplification:
Y1=(A+BC)(B+A C ) ( Given Expression)
= AB+ A C +BC (Using basic gates)
= BC+ CA +AB
=
Y1= ( A+BC)(B+ A C )
= (A+B)(A+C)(B+A)(B+ C )
= ))()(( CBBACA
=
A B C
Y1
AB . BC . CA (Using NAND Gates)
)( CA + )( BA + ( )CB (Using only NOR gates)
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 8
B. Implementation Using Universal Gates
1. Convert the AND-OR logic into NAND-NAND and NOR-NOR logic.
2. Implement the simplified Boolean expressions using only NAND gates, and then using only
NOR gates.
3. Connect the circuits according to the circuit diagrams, apply inputs according to the
truth table and verify the results.
Using Only NAND gates
Using only NOR gates Truth Table
A B C Y1
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
A B C
Y
1
1
A B C
Y1
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 9
2) Z= A B C +ABC + A B C+ABC
= A B (C+C )+AB(C+C )
= A B +AB (using Basic Gates)
Z=
Z=
Using NAND Gates Only
Using NOR Gates only
A B + AB ( Using only NAND Gates)
(A+ B )+( A +B) ( Using only NOR Gates)
A
B
Z
Z
A B
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 10
Circuit Diagram :
A. Series Clippers :
1. To pass positive peak above V level
Vi
V Vm
2 t
Vo
2 t
2. To pass positive peak above some reference level ( VR +V )
Vi
VR+V
Vm
2 t
Vo
2 t
Vi
Vo
V
Vi
Vo
VR +V
10 V p-p
500 Hz
10 V p-p
500 Hz
A K
A K
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 11
Experiment No. : 3 Date: ___/____/_______
Testing of diode clipping and Clamping circuits
Aim : To design and study the series and shunt clipping circuits using diodes.
Apparatus Required :
Sl.
No. Particulars Range Quantity
1. Diode ( 1N4007 / BY 127 ) - 02
2. Resistor As per design -
3. Multimeter - 01
4. CRO Probes - 3 set
5. Spring Board and Connecting wires - -
Theory:
A clipper is a circuit that removes either positive or negative portion of a waveform. This kind
of processing is useful for signal shaping, circuit protection and communications. The clippers are
usually constructed by using diodes and resistors and some times to adjust the clipping level DC
power supplies are also used. There are two types of clippers namely series clippers and shunt
clippers. If the clipping element (diode) is in series with the source then we call it as series clippers
and if the clipping device is in parallel with the source then we call such circuit as shunt clippers.
Further based on the portion of a waveform clipped the clippers can be classified as positive clippers,
negative clippers and two level clippers (combination clippers).
Procedure:
1. Components / Equipment are tested for their good working condition.
2. Connections are made as shown in the circuit diagram
3. Apply a sine wave of amplitude greater than the designed clipping level with frequency 500
Hz.
4. Observe the output wave form on the CRO
5. Observe the transfer characteristic curve on CRO by applying input waveform to channel – X
and output waveform to channel – Y.
6. Measure the clipped voltage and compare with the designed value.
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 12
3. To pass negative peak above -V level
Vi
Vm
-V 2 t
Vo
2 t
4. To pass negative peak above some reference level (-VR - V )
Vi
Vm
Vo 2 t
-VR-V
2 t
Vi
Vo
- V
Vi
Vo
- VR - V
10 V p-p
500 Hz
10 V p-p
500 Hz
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 13
5. To pass positive peak above some reference level (VR1+V) and negative peak above some
Example: 7+2=11 (1001) • 7 is realized at A3 A2 A1 A0 = 0111 • 2 is realized at B3 B2 B1 B0 = 0010
Sum = 1001 Procedure:
1. Check all the components for their working. 2. Insert the appropriate IC into the IC base. 3. Make connections as shown in the circuit diagram. 4. Apply augend and addend bits on A and B and cin=0. 5. Verify the results and observe the output of ADDER CIRCUIT
Circuit :
2. 4-Bit Binary Subtractor.
(i) 4 bit subtraction operation using 7483 for A>B and Cin=1
Example: 8 – 3 = 5 (0101)
• 8 is realized at A3 A2 A1 A0 = 1000
• 3 is realized at B3 B2 B1 B0 through X-OR gates = 0011
• Output of X-OR gate is 1’s complement = 1100
• 2’s Complement can be obtained by adding Cin = 1
Therefore Cin =1
A3 A2 A1 A0 = 1 0 0 0
B3 B2 B1 B0 = 1 1 0 0
S3 S2 S1 S0 = 0 1 0 1 Cout = 1 (Ignored)
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 37
Experiment No. : 6 Date: ___/____/_______
Realization of parallel adder/Subtractors using 7483 chip- BCD to Excess-3
code conversion & Vice –Versa, Binary to Gray code conversion and vice-
versa
6 a) parallel adder/Subtractors using 7483
Aim: To design and set up the following circuit using IC 7483.
i) A 4-bit binary parallel adder.
ii) A 4-bit binary parallel subtractor. Components Required: IC 7483, IC 7486, Trainer kit, etc
Theory:
The Full adder can add single-digit binary numbers and carries. The largest
sum that can be obtained using a full adder is 112. Parallel adders can add
multiple-digit numbers. If full adders are placed in parallel, we can add two- or
four-digit numbers or any other size desired. Figure below uses STANDARD
SYMBOLS to show a parallel adder capable of adding two, two-digit binary
numbers The addend would be on A inputs, and the augend on the B inputs.
To add four bits need four full adders arranged in parallel. IC 7483 is a 4- bit
parallel adder is used.
MSB LSB
INPUTS Cin
A3 A2 A1 A0
B3 B2 B1 B0
OUTPUT Cout S3 S2 S1 S0
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 38
ii) 4 bit subtraction operation using 7483 for A<B and Cin=1
Example: 14 – 15 = -1 (1111)
• 14 is realized at A3 A2 A1 A0 = 1110
• 15 is realized at B3 B2 B1 B0 through X-OR gates = 1111
• Output of X-OR gate is 1’s complement of 15 = 0000
• 2’s Complement can be obtained by adding Cin = 1
Therefore Cin = 1
A3 A2 A1 A0 = 1 1 1 0
B3 B2 B1 B0 = 0 0 0 0
S3 S2 S1 S0 = 1 1 1 1 since the most significant bit of the result is 1, this is a negative number, so form
the two's complement of (1111)=0001(-1)
Procedure:
1. Check all the components for their working. 2. Insert the appropriate IC into the IC base. 3. Make connections as shown in the circuit diagram. 4. Apply Minuend and subtrahend bits on A and B and cin=1. 5. Verify the results and observe the outputs.
Circuit:
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 39
Experiment 6(b): CODE CONVERTERS. Aim: To design and realize the following using IC 7483.
(i) Excess-3 to BCD Code conversion and vice-versa (ii) Realization of Binary to Gray code conversion and vice versa
Components Required: IC 7483, IC 7486, Patch Cords & IC Trainer Kit.
Theory:
Code converter is a combinational circuit that translates the input code
word into a new corresponding word. The excess-3 code digit is obtained by
adding three to the corresponding BCD digit. To Construct a BCD-to-excess-3-
code converter with a 4-bit adder feed BCD code to the 4-bit adder as the first
operand and then feed constant 3 as the second operand. The output is the
corresponding excess-3 code. To make it work as a excess-3 to BCD converter, we feed excess-3 code as the
first operand and then feed 2's complement of 3 as the second operand. The
output is the BCD code.
Excess-3-code to BCD: Truth Table:
Excess-3 inputs BCD outputs
E3 E2 E1 E0 S3 S2 S1 S0
0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 40
Procedure: 1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Apply Excess-3-code code as first operand (A) and binary 3 as second
operand(B) and Cin=1 for realizing Excess-3-code to BCD.
Circuit:
BCD to Excess-3-code: Truth Table:
BCD inputs Excess-3 outputs
A3 A2 A1 A0 S3 S2 S1 S0
0 0 0 0 0 0 0 0
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 41
Procedure: 1. Check all the components for their working. 2. Insert the appropriate IC into the IC base. 3. Make connections as shown in the circuit diagram. 4 Apply BCD code as first operand(A) and binary 3 as second operand(B) and cin=0 for
Realizing BCD-to-Excess-3-code:
Circuit :
RESULT:
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 42
Binary to Gray code Realization using Nand Gates
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 43
(ii)Binary to Gray code conversion and vice versa Components Required: IC 7486, IC 7400and IC 7408. Theory:
Binary to gray code conversion is a very simple process. There are several
steps to do this types of conversions. Steps given below elaborate on the idea on
this type of conversion. (1) The M.S.B. of the gray code will be exactly equal to the first bit of the given
binary number. (2) Now the second bit of the code will be exclusive-or of the first and second bit of
the given binary number, i.e if both the bits are same the result will be 0 and if
they are different the result will be 1. (3)The third bit of gray code will be equal to the exclusive -or of the second and
third bit of the given binary number. Thus the Binary to gray code conversion
goes on. One example given below can make your idea clear on this type of
conversion.
Gray code to binary conversion is again very simple and easy process. Following steps can make your idea clear on this type of conversions. (1) The M.S.B of the binary number will be equal to the M.S.B of the given gray
code. (2) Now if the second gray bit is 0 the second binary bit will be same as the
previous or the first bit. If the gray bit is 1 the second binary bit will alter. If it was
1 it will be 0 and if it was 0 it will be 1. (3) This step is continued for all the bits to do Gray code to binary conversion.
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 44
Karaungh maps: (i)Realization using Basic Gates:
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 45
Procedure:
1. Verify that the gates are working.
2. Write the proper truth table for the given Binary to Gray /Gray to binary
converter
3. Draw Karnaugh maps for each bit of output. Simplify the Karnaugh maps to get simplified
Boolean Expressions.
4. Make connections on the trainer kit as shown in the circuit diagram for the Binary to Gray /Gray
to Binary converter.
5. Check the outputs for the corresponding inputs.
BINARY TO GRAY CONVERSION: Truth Table:
Binary inputs Gray outputs
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 46
GRAY TO BINARY CONVERSION : Truth Table:
Gray
inputs Binary outputs
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
Karnaugh maps:
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 47
(i)Realization using Basic Gates:
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 48
d) Realization using Nand Gates:
RESULT:
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 49
Experiment No. : 7 Date: ___/____/_______
RC Phase Shift Oscillator
Aim: To design and test an RC phase shift oscillator for the given frequency of oscillations.
Apparatus Required:
Sl.
No. Particulars Range Quantity
1. Transistor SL 100 - 01
2. Resistors & Capacitors As per design -
3. CRO Probes - 3 Set
4. Multi meter - 01
5. DRB - 01
6. Spring board and connecting wires - -
Theory:
An oscillator is an electronic circuit that produces a repetitive electronic signal, often a sine
wave or a square wave. RC-phase shift oscillator is used generally at low frequencies (Audio
frequency). It consists of a CE amplifier as basic amplifier circuit and three identical RC networks for
feed back, each section of RC network introduces a phase shift of 60 and the total phase shift by
feedback network is 180. The CE amplifier introduces 180 phase shift hence the overall phase shift
is 360. The feed back factor for an RC phase shift oscillator is 1/29, hence the gain of amplifier (A)
should be 29 to satisfy Barkhausen criteria.
The Barkhausen criteria states that in a positive feedback amplifier to obtain sustained
oscillations, the overall loop gain must be unity ( 1 ) and the overall phase shift must be 0 or 360.
When the power supply is switched on, due to random motion of electrons in passive
components like resistor, capacitor a noise voltage of different frequencies will be developed at the
collector terminal of transistor, out of these the designed frequency signal is fed back to the amplifier
by the feed back network and the process repeats to give suitable oscillation at output terminal
No. RL in Ic in mA Vo in Volt Pdc = VCC. IC Pac=Vo
2 / 8RL % =Pac / PDC
B E
C
C
2N3055 / OC26
0.1 F 1000 F
TR1
TR2
OC26
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 64
Experiment No. : 12 Date: ___/____/_______
Realization of 3 bit counters as a sequential circuit and MOD – N counter design
using 7476,7490, 74192, 74193.
Experiment 12(a): ASYNCHRONOUS COUNTERS
Aim: To design and test 3-bit binary asynchronous up/down counter using flip-fop IC 7476 for the given sequence. Components required: IC 7476,patch cards,trainer kit etc. Theory:
An asynchronous (ripple) counter is a single JK-type flip-flop, with its J (data) input fed from its own inverted output. This circuit can store one bit, and hence can count from zero to one before it overflows (starts over from 0). Notice that this creates a new clock with a 50% duty cycle at exactly half the frequency of the input clock. If this output is then used as the clock signal for a similarly arranged D flip-flop (remembering to invert the output to the input), one will get another 1 bit counter that counts half as fast. Putting them together yields a two-bit counter: We can continue to add additional flip-flops, always inverting the output to its own input, and using the output from the previous flip-flop as the clock signal. The result is called a ripple counter,
which can count to 2n − 1 where n is the number of bits (flip-flop stages) in the counter
PROCEDURE: 1. Check all the components for their working. 2. Make connections as shown in the circuit diagram. 3. Clock pulses are applied one by one at the clock input and output is observed at QA,QB and QC. 4. Verify the Truth Table and observe the outputs.
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 65
1. 3 Bit Asynchronous Up Counter
Truth Table: Circuit:
Clock
QC
QB
QA
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
0
0
0
9
0
0
1
Wave Forms:
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 66
2. 3 Bit Asynchronous Down Counter
Truth Table: Circuit:
Wave Forms:
Clock
QC
QB
QA
0
1
1
1
1
1
1
0
2
1
0
1
3
1
0
0
4
0
1
1
5
0
1
0
6
0
0
1
7
0
0
0
8
1
1
1
9
1
1
0
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 67
3. Mod 5 Up Counter:
Truth Table Waveforms:
Clock
QC
QB
QA
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
0
0
0
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 68
4. Mod 4 Down Counter:
Truth Table: Wave forms
Clock
QC
QB
QA
0
1
1
1
1
1
1
0
2
1
0
1
3
1
0
0
4
1
1
1
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 69
Circuit:
Waveforms:
[Electronics Lab : 15 EEL 38] 2017-18
Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 70
Experiment 12(b): SYNCHRONOUS COUNTERS Aim: To design and test a 3 bit synchronous counter using 7476