Reconfigurable Cell Array for DSP Applications Chenxin Zhang Department of Electrical and Information Technology Lund University, Sweden ETI180 DSP-design Dec. 06 th , 2011 Department of Electrical and Information Technology, Lund University Outline • Reconfigurable computing • Coarse-grained reconfigurable cell array – Processing cell – Memory cell – Network router cell – System reconfiguration – Reconfigurable FIR – Reconfigurable FFT processor – Multi-standard OFDM coarse time synchronization Department of Electrical and Information Technology, Lund University Reconfigurable computing • Updates on the data path in addition to the control flow. • Combined flexibility with high performance at a feasible hardware cost. • Software-centric programming approach. • Coarse-grained granularity – trade-off between efficiency, flexibility, and programmability. • Dynamic reconfigurability. Department of Electrical and Information Technology, Lund University High performance real-time DSP computing
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Reconfigurable Cell Arrayfor DSP Applications
Chenxin Zhang
Department of Electrical and Information TechnologyLund University, Sweden
ETI180 DSP-design Dec. 06th, 2011
Department of Electrical and Information Technology, Lund University
Outline
• Reconfigurable computing
• Coarse-grained reconfigurable cell array
– Processing cell
– Memory cell
– Network router cell
– System reconfiguration
� ����������– Reconfigurable FIR
– Reconfigurable FFT processor
– Multi-standard OFDM coarse time synchronization
Department of Electrical and Information Technology, Lund University
Reconfigurable computing
• Updates on the data path in addition to the control flow.
• Combined flexibility with high performance at a feasible
hardware cost.
• Software-centric programming approach.
• Coarse-grained granularity – trade-off between efficiency,
flexibility, and programmability.
• Dynamic reconfigurability.
Department of Electrical and Information Technology, Lund University
High performance real-time DSP computing
Department of Electrical and Information Technology, Lund University
Media.Processor
Apps.Processor
GPS
Multiple standards
CellularApps.Processor
BT
WLAN
DVB-H
Wimax
LTE-A
WCDMA
Media.Processor
…
5G?
Apps.Processor
Department of Electrical and Information Technology, Lund University
Software-defined hardware
• Hardware sharing
– Accelerators: poor hardware reusability
– Reconfigurable architecture
+ Multi-task
+ Multi-standard
+ Multi-algorithm
− Control overhead, e.g. area, power.
A B C D
Processing chain
Department of Electrical and Information Technology, Lund University
Performance vs. Flexibility
• Specialized hardware (ASIC)
+ High performance, small size, low power
- Less flexible, manufacturing defects
- High NRE cost
• Standard processor (GPP, DSP…)
+ Flexible, Short design time
- Lack of computation capacity
• Fine-grained reconfigurable architecture (FPGA)
+ High calculation capacity, flexible
- Routing overhead, high power consumption
- Hardware oriented design approach
Department of Electrical and Information Technology, Lund University
Application specific DSP:Tensilica ConnX Baseband Engine
Department of Electrical and Information Technology, Lund University
Tabula Spacetime
• Ultra-rapid reconfiguration:
multi-GHz rates
• 2.5x logic density
• 3.7x DSP performance
Department of Electrical and Information Technology, Lund University
Coarse-grainedreconfigurable architecture
• High calculation capacity & flexible
• Software oriented: relevantly fast
development
• tolerance to manufacturing defects
• Sacrificed area & energy efficiency
compared to ASICs
• Sacrificed mapping flexibility compared
to FPGAs
CGRA
Department of Electrical and Information Technology, Lund University
Related work
• ALU clusters: MathStar FPOA, RICA…
– Instruction level, data level parallelism
– SIMD or VLIW
• Processor array: RAW, WPPA, REMARC…
– Instruction level, data level, and task level parallelism
– MIMD
• Hybrid structure: ADRES, PACT XPP…
– Instruction level, data level, and task level parallelism