School of Engineering 1 ENG2410 Digital Design “Arithmetic Circuits” Fall 2017 S. Areibi School of Engineering University of Guelph 2 Topics Binary Adders Binary Ripple Carry Adder 1’s and 2’s Complement Binary Subtraction Binary Adder-Subtractors Binary Multipliers BCD Arithmetic 3 Resources Chapter #5, Mano Sections 5.2 Binary Adders 5.3 Binary Subtraction 5.4 Binary Adders-Subtractors 5.5 Binary Multiplications 5.7 HDL Representations -- VHDL 4 Recall: Arithmetic -- addition Binary addition is similar to decimal arithmetic + 1 0 0 0 1 0 0 1 1 0 1 1 1 0 1 No carries 1 0 1 1 0 0 1 0 1 1 0 + 1 0 1 1 1 1 0 1 1 0 1 Carries Remember: 1+1 is 2 (or (10) 2 ), which results in a carry 1+1+1 is 3 (or (11) 2 ) which also results in a carry 5 Half Adder (One bit adder) o S = XY’ + X’Y = X ⊕ Y o C = X.Y 6 Full Adder o Three inputs: X Y Third is C in Z o Two outputs: Sum C out S Full Adder x y Z C out Implementation?
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School of Engineering 1
ENG2410Digital Design
“Arithmetic Circuits”
Fall 2017S. Areibi
School of EngineeringUniversity of Guelph
2
Topics
� Binary Adders
� Binary Ripple Carry Adder
� 1’s and 2’s Complement
� Binary Subtraction
� Binary Adder-Subtractors
� Binary Multipliers
� BCD Arithmetic
3
Resources
� Chapter #5, Mano Sections� 5.2 Binary Adders
� 5.3 Binary Subtraction
� 5.4 Binary Adders-Subtractors
� 5.5 Binary Multiplications
� 5.7 HDL Representations -- VHDL
4
Recall: Arithmetic -- addition
Binary addition is similar to decimal arithmetic
+ 10001
00110
1 1 1 0 1
No carries 1 0 1 1 0 0
1 0 1 1 0
+ 1 0 1 1 1
1 0 1 1 0 1
Carries
Remember: 1+1 is 2 (or (10)2), which results in a carry1+1+1 is 3 (or (11)2) which also results in a carry
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Half Adder (One bit adder)
o S = XY’ + X’Y
= X ⊕ Y
o C = X.Y
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Full Adder
o Three inputs: � X� Y� Third is C in � Z
o Two outputs: � Sum� Cout
S
Full Adder
x y
ZCout
Implementation?
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Straight Forward Implementation:
� What is this?
Z
S
K Map for S
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YZXZXYC ++=
Y
X
Z
Y
Z
X
C
Straight Forward Implementation:
K Map for C
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Implementation Issues
o If we try to implement the Optimized Boolean functions directly we will need how many gates?� Seven AND gates and two OR Gates !!
o Can we do better?o YES!!
� Share Logic � Hierarchical Design.
YZXZXYC ++=
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Any Alternatives?
o Try to make use of hierarchy to design a 1-bit full adder from two half adders.
o Also, try to share logic between the Sum output and Carry output.
� Half Adder
S = X ⊕ Y
C = XY
� Full Adder
S = X ⊕ Y ⊕ Z
C = XY + XZ + YZ
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A Different Way to Represent C
1
1 1 1
X
YZ
0
1
00 01 11 10
XY
XYZ
XYZ
C = XY + XYZ + XYZ
C = XY + Z (XY + XY)
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Two Half Adders (and an OR)
How many Gates do we need?
Full Adder
x y
ZC
S
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Binary Ripple-Carry Adder
� A Parallel binary adder is a digital circuit that produces the arithmetic sum of two binary numbers using only combinational logic.
� The parallel adder uses “n” full adders in parallel, with all input bits applied simultaneously to produce the sum.
� The full adders are connected in cascade, with the carry output from one full adder connected to the carry input of the next full adder.
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Binary Ripple-Carry Adder
� Straightforward – connect full adders
� Carry-out to carry-in chain
� C0 in case this is part of larger chain, maybe just set to zero
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Hierarchical 4-Bit Adder
We can easily use hierarchy here1. Design half adder2. Use TWO half adders to create full adder3. Use FOUR full adders to create 4-bit adder
VHDL CODE?
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VHDL Half Adder (DATA FLOW)
entity half_adder is
port (x_ha,y_ha: in std_logic;
s_ha,c_ha: out std_logic);
end half_adder;
architecture dataflow of half_adder is
begin
s_ha <= x_ha xor y_ha;
c_ha <= x_ha and y_ha;
end dataflow
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VHDL Full Adder (Structural)
entity full_adder is
port (x_fa, y_fa, z_fa: in std_logic;
s_fa, c_fa: out std_logic);
end full_adder;
architecture struc_dataflow of full_adder ishs
hc
tc
component half_adder
port (x_ha, y_ha : in std_logic;
s_ha, c_ha : out std_logic);
end component;
signal hs, hc, tc: std_logic;
begin
HA1: half_adder
port map (x_fa, y_fa, hs, hc);
HA2: half_adder
port map (hs, z_fa, s_fa, tc);
c_fa <= tc or hc;
end struc_dataflow
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Any Problems with this Design?
� Delay� Approx how much?
� Imagine a 64-bit adder� Look at carry chain
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Carry Propagation & Delay
� One problem with the addition of binary numbers is the length of time to propagate the ripple carry from the least significant bit to the most significant bit.
� The gate-level propagation path for a 4-bit ripple carry adder of the last example:
� Note: The "long path" is from A0 or B0 through the circuit to S3.
Range 0 ≤ N ≤ 15 -7 ≤ N ≤ +7 -7 ≤ N ≤ +7 -8 ≤ N ≤ +7
PositiveBinary Binary Binary Binary
Negative XBinary 1’s Comp. 2’s Comp.
0 0 0
1 1 1
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Example in 8-bit byte
� Represent +9 in different ways
Signed magnitude 00001001
1’s Complement 00001001
2’s Complement 00001001
� Represent -9 in different ways
Signed magnitude 10001001
1’s Complement 11110110
2’s Complement 11110111
The
Same!
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Observations
� All positive numbers are the same
� 1’s Comp and Signed Mag have two zeros
� 2’s Comp has more negative than positive
� All negative numbers have 1 in high-order bit
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Advantages/Disadvantages
Signed magnitude has problem that we need to correct after subtraction
One’s complement has a positive and negative zero
☺ Two’s complement is most popular
� i.e arithmetic operations are easy
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Signed Magnitude Representation
�Magnitude is magnitude, does not change with sign
(+3)10 � ( 0 0 1 1 )2
(−3)10 � ( 1 0 1 1 )2
�Can’t include the sign bit in ‘Addition’0 0 1 1 � (+3)10
+ 1 0 1 1 � (−3)10
1 1 1 0 � (−6)10
Sign Magnitude
S Magnitude (Binary)
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Signed Magnitude Representation
� The signed-magnitude system is used in ordinary arithmetic, but is awkward when employed in computer arithmetic (Why?)
1. We have to separately handle the sign
2. Perform the correction if necessary!!
� Therefore the signed complement (1’s complement and 2’s complement number representations) is normally used.
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Signed Magnitude Arithmetic
� Complex Rules!!
� The addition of two numbers M+N in the sign magnitude system follows the rules of ordinary arithmetic:
� If the signs are the same, we add the two magnitudes and give the sum the sign of M.
� If the signs are different, we subtract the magnitude of N from the magnitude of M.
� The absence or presence of an end borrow then determines:
� The sign of the result.
� Whether or not a correction is performed.
� Example: (0 0011001) + (1 0100101)
� 0011001 – 0100101 = 1110100
� End borrow of 1 occurs, � M < N!!
� Sign of result should be that of N,
� Also correct result by taking the 2’s complement of result
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Binary Subtraction Using 1’s Comp. Addition
�Change “Subtraction” to “ Addition”
� If “ Carry” = 1then add it to theLSB, and the resultis positive(in Binary)
� If “ Carry” = 0then the resultis negative(in 1’s Comp.)
0 1 0 1
+ 1 1 1 0
(5)10 – (1)10
(+5)10 + (-1)10
0 0 1 1+
0 1 0 0
0 1 0 1
+ 1 0 0 1
(5)10 – (6)10
(+5)10 + (-6)10
0 1 1 1 0
1 1 1 0
+ 4 − 1
1
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Two’s Complement
� To Add:� Easy on any combination of positive
and negative numbers
� To subtract:� Also easy!
� Take 2’s complement of subtrahend
� Add
� This performs A + ( -B), same as A – B
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Binary Subtraction Using 2’s Comp. Addition
�Change “Subtraction” to “ Addition”
� If “ Carry” = 1ignore it, and the result is positive(in Binary)
� If “ Carry” = 0then the resultis negative(in 2’s Comp.)
0 1 0 1
+ 1 1 1 1
(5)10 – (1)10
(+5)10 + (-1)10
1 01 0 0
0 1 0 1
+ 1 0 1 0
(5)10 – (6)10
(+5)10 + (-6)10
0 1 1 1 1
+ 4 − 1
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Examples from Book
� Addition
� (+6) + 13
� (-6) + 13
� (+6) + (- 13)
� (-6) + (-13)
� Subtraction
� (-6) - (-13)
� (+6) - (-13)
The numbers below should be in 2’s comp representation
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Addition of Two Positive Numbers
� Addition
� (+6) + 13 = +19
00000110 � +6
+00001101 � +13
--------------
00010011 � +19
� If a carry out appears it should be discarded.
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Addition of :a Positive and Negative Numbers
� Addition
� (-6) + 13 = +7
11111010 (this is 2’s comp of +6)
+00001101
--------------
1 00000111
� The carry out was discarded
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Subtraction of Two Numbers
� The subtraction of two signed binary numbers (when negative numbers are in 2’s complement form) can be accomplished as follows:1. Take the 2’s complement of the subtrahend
(including the sign bit)
2. Add it to the minuend.
3. A Carry out of the sign bit position is discarded.
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Subtraction of Two Numbers
� Subtraction� (+6) – (+13) = -7
00000110 00000110
- 00001101 � + 11110011 (2’s comp)
-------------- -----------
11111001
� What is 11111001?
Take its 2’s complement=> 00000111
The magnitude is 7
So it must be -7
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Circuit for 2’s complement Numbers
� No Correction is needed if the signed numbers are in 2’s complement representation
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Sign Extension
� Sign extension is the operation, in computer arithmetic, of increasing the number of bits of a binary number while preserving the number’s sign (positive/negative) and value.
� This is done by appending digits to the most significant side of the number
� In order to obtain a correct answer when adding and subtracting, we must ensurethat the result has a sufficient number of bits to accommodate the sum.
� If we start with two n-bit numbers and we end up with a number that is n+1 bits, we say an overflow has occurred.
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Overflow
� Two cases of overflow for addition of signed numbers
� Two large positive numbers overflow into
sign bit
� Not enough room for result
� Two large negative numbers added
� Same – not enough bits
� Carry out can be OK
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Examples
� Two signed numbers +70 and +80 are stored in 8-bit registers.
� The range of binary numbers, expressed in decimal, that each register can accommodate is
from +127 to -128.
� Since the sum of the two stored numbers is 150, it exceeds the capacity of an 8-bit register.