Rec101 unit ii (part 3) field effect transistor

Field Effect Transistor

Unit II

Bipolar Junction Transistor: Transistor Construction, Operation, Amplification action.Common Base, Common Emitter, Common Collector Configuration DC Biasing BJTs: OperatingPoint, Fixed-Bias, Emitter Bias, Voltage-Divider Bias Configuration. Collector Feedback,Emitter-Follower Configuration. Bias Stabilization. CE, CB, CC amplifiers and AC analysis ofsingle stage CE amplifier (re Model ). Field Effect Transistor: Construction and Characteristicof JFETs. AC analysis of CS amplifier, MOSFET (Depletion and Enhancement)Type, TransferCharacteristic

11/6/2017 1REC 101 Unit II by Dr Naim R Kidwai, Professor & Dean, JIT Jahangirabad

Field Effect Transistor (FET)


BJTBase B

Collector C

Emitter E

Control Current IB

IC

FETGate G

Drain D

Source S

Control Voltage VGS

ID

Current Controlled device BJT Voltage Controlled device FET

• BJT is current-controlled, whereas FET is voltage-controlled device • BJT is bipolar device (electrons and holes contribute in currents)

whereas FET is a unipolar device; current conducts either due to electron (n-channel) or hole (p-channel).

Field Effect Transistor (FET)

• In FET an electric field, due to biasing voltage, controls the current conduction path of device, hence the name Field effect transistor

• FET have high input impedance than BJT

• FET are more temperature stable than BJT

• FETs are of two types:

– junction field-effect transistor (JFET), and

– metal–oxide–semiconductor field-effect transistor (MOSFET),

MOSFET are of two types;

• depletion and

• enhancement


Junction Field Effect Transistor (JFET): Construction


• With no bias, the JFET has two p–n junctionsresulting in depletion region at each junction

n-channel JFET construction

npp

Source S

Drain D

Gate G

Ohmic contacts

Depletion region

SG +

-

ID

D +

VDS

-VGS SG +

-

ID

D +

VDS

-VGS

n-channel JFET symbol p-channel JFET symbol

• n-type material connected to drain (D) and source (S), forms thechannel between the p-material layers.

• The two p materials are connected to gate (G) terminal

Junction Field Effect Transistor (JFET): Working


VGS=0 and VDS>0

• When VGS=0 & VDS is +ve, a decreasing reverse biaspotential is applied across p-n junction from drainto source, resulting in wide depletion at drain endwhich goes on reducing towards source

• Due to VDS, current flows. Drain and sourcecurrents are equal (ID=IS).

• charge flow is uninhibited and is limited byresistance of n-channel between drain and source.

• Due to reverse bias p-n junction, gate current IG 0,which is an important characteristic of the JFET

Varying reverse bias potential at p-n junction

S

D

G

2 V

0 V

1.5 V

1.0 V

0.5 V

n

p p

n-channel JFET at VGS=0

S

D

G

Depletion region +

VDS

-

+

VGS=0

-

n

p p

Junction Field Effect Transistor (JFET): Working


VGS=0 and pinch off voltage• With Initial increase of VDS from 0, ID increase

linearly (constant channel resistance)• Further increase of VDS results in channel width

reduction due to depletion widening, causingslowdown in increase of ID.

• As VDS=VP (pinch off voltage), it appears thattwo depletion regions ‘touch’ each other and ID

is saturated to IDSS (a very small channel exist and a

very high density current flows)• When VDS>VP, the region of ‘touching’ depletion

increases in length & ID remains saturated. JFETbehaves as constant current source

n-channel JFET at VGS=0 & VDS=VP

S

D

G

Depletion region +

-

+

VGS=0

-

n

p pVDS =VP

Output characteristicsof JFET at VGS=0

VDS

ID

IDSS

VP

VGS =0

Increasing resistance dueto narrowing channel

JFET Characteristics


VGS<0 and VDS>0• -ve VGS results in similar curve with

reduced VP & saturation current.• pinch-off voltage drop in parabolic

manner as VGS goes more negative.• At VGS= -VP , JFET will be ‘off’ (ID=0)• For VDS> VDS max , breakdown occurs

• VP is +ve for for p-channel JFET. VP is also referred as VGS(off)

• Saturation is also called constant current / linear amplification region• JFET behaves as variable resistor in ohmic region (controlled by VGS)

Output characteristics of n-channel JFET

VDS

ID

IDSSVGS =0

VGS =-1 V

VGS =-2 V

VGS =-3 VVGS =-4 V= -VP

Locus of pinch off valuesSaturation regionO

hm

icre

gio

n

VP for VGS=0

876543210 5 10 15 20 25

Breakdownregion

VDS max

JFET Characteristics Transfer curve


Output characteristics of n-channel JFET

VDS

ID(mA)

IDSS VGS =0

VGS =-1 V

VGS =-2 V

VGS =-3 VVGS =-4 V= VP

VP for VGS=0

876543210

5 10 15 20 25

Breakdownregion

VDS max

-4 -3 -2 -1

876543210

VGS

ID(mA)

Transfer characteristics of n-channel JFET

Transfer characteristics of JFET is given by Shockley’s equation

2

1

P

GSDSSD

V

VII

Depletion MOSFET, Transfer Characteristic

• MOSFET is Metal Oxide Semiconductor Field Effect Transistor and areof two types; depletion and enhancement type

• It does not have p-n junction structure as in JFET

• SiO2 layer (dielectric insulator) isolates gate and channel.• SiO2 layer results in very high input impedance


n-channel D-MOSFET symbol p-channel D-MOSFET symbol

S

G+

-

ID

D +

VDS

-VGS S

G+

-

ID

D +

VDS

-VGS

n-channel D-MOSFET construction

P substrate

Gate G

SiO2 layer

n

nSource S

Drain D

n-channel

D-MOSFET, Operation & Transfer Characteristic


For n channel D-MOSFET, with VDS>0• At VGS=0, current ID flows through the channel.

The current is labelled as IDSS

• With VGS<0, channel depletes & current ID

reduces with increasing -ve bias.• at VGS=VP (pinch off voltage; a –ve voltage),

channel fully depletes & current ID=0• With +ve VGS, channel enhances & ID increases

S

G+

-

IDD

+VDS

-VGSVGG

VDD

n-channel D-MOSFET

• Shockley’s equation of JFET is applicable for the D-MOSFETon the drain or transfer characteristics• region of +ve gate voltage is referred as enhancement region• region with VP< VGS<0 is referred as depletion region• region with VGS< VP is referred as cut off region

D-MOSFET, Operation & Transfer Characteristic


Transfer characteristics of n-channel D-MOSFET Output (Drain) characteristics of n-channel D-MOSFET

VDS

ID(mA)

IDSS

VGS =0

VGS =-1 V

VGS =-2 V

VGS =-3 VVGS =-4 V= VP

VP for VGS=0

876543210 5 10 15 20 25-4 -3 -2 -1

876543210VGS

ID(mA) VGS =1 V

-VP

Depletion mode Enhancement mode

Transfer characteristics of D-MOSFET is given by Shockley’s equation2

1

P

GSDSSD

V

VII

Enhancement MOSFET, Transfer Characteristic

• E-MOSFET has no structured channel• Gate voltage induces a channel by by creating a thin layer of charge

carriers in the substrate near the gate.• +ve VGS, results in n-channel by while -ve VGS, results in p channel• conductivity of channel is enhanced by increasing the VGS

• SiO2 layer accounts for the very high input impedance.


n-channel D-MOSFET symbol p-channel D-MOSFET symbol

S

G+

-

ID

D +

VDS

-VGSS

G+

-

ID

D +

VDS

-VGS

P substrate

n-channel D-MOSFET construction

GateG

SiO2 layer

n

nSource S

Drain D

E-MOSFET, Operation & Transfer Characteristic


For n channel E-MOSFET, with VDS>0• when 0<VGS<VT (threshold voltage) current

ID is zero due to absence of channel• With VGSVT, electrons of p-substrate

induces a channel for drain current flow.• with VGSVT with increase in VDS, ID

saturates due to pinching-off (narrowerchannel at drain end of induced channel )

S

G+

-

IDD

+VDS

-VGSVGG

VDD

n-channel E-MOSFET

on the drain or transfer characteristics• region of +ve gate voltage is referred as

enhancement region• region with VGS< VT is referred as cut off region

P substrate

Pinching off in n-channel E-MOSFET with VGS>VT & VDS>0

GateG

SiO2 layer

n

nSource S

Drain D

E-MOSFET, Transfer Characteristic


Transfer characteristics of n-channel E-MOSFET Output (Drain) characteristics of n-channel E-MOSFET

VDS

ID(mA)

IDSS VGS =0

VGS =-1 V

VGS =-2 V

VGS =-3 V VGS= VT= 2 V

10

9

8

7

6

5

4

3

2

1

0 5 10 15 20 252 3 4 5 6 7 VGS

ID(mA) VGS =1 V

VT

10

9

8

7

6

5

4

3

2

1

0

For VGS>VT

device ofon constructi offunction is andconstant is

2

k

VVkI TGSD

FET: DC Biasing Operating Point

•ac power increase (amplification) is due to energy transfer by dc bias

•both dc & ac response is required for analysis/design of FET amplifier

•To find Q point (operating point), output voltage & output current dueto dc biasing has to be known. (for CS configuration, ID , VDS and VGS )


and 0 SDG III

•Each configuration is analysed by recurring use of following equations

2

1 MOSFET-D & JFETfor

P

GSDSSD

V

VII 21 MOSFET-Efor TD VkI

•ac power increase (amplification) is due to energy transfer by dc bias

•both dc & ac response is required for analysis/design of FET amplifier

•To find Q point (operating point), output voltage & output current dueto dc biasing has to be known. (for CS configuration, ID , VDS and VGS )

FET: Voltage-Divider Bias


calculated is and equation, two theSolving

1

and

,0 as

2

21

2

21

2

GSD

P

GSDSSD

SDDD

GS

SDGGSDD

G

SDG

VI

V

VII

RIRR

VRV

RIVVRR

VRV

III

Voltage divider bias

VDD

IDRDR1

+-

Input ac signal

Output ac signal

C1

C2VDS

ISRS

R2

I1

I1

SG

D

VGS

SDDDDDS RRIVV

FET: Voltage-Divider Bias Example


mA 66.6I and V 71.1 so

holdnot does which VV & 0I ,V if as

V 71.1 V, 7.4get wesolving

003.841.6or

69971.0409.0or

3004.061037.2 ngsubstitution

3004.03

V1120.0I & 61037.2

V 37.22093

11 , ,0 as

D

GSGDP

2

2

2

2

2

GSD

21

2

GS

GS

GS

GSGS

GSGSGS

GSGS

GSDGS

DDGSDG

V

V

V

VV

VVV

VxV

VIV

xRR

VRVIII

V 62.261.266.620 xVDS

R2=11 M

RD=2 K

RS=610

Voltage divider bias

VDD=20 V

ID

R1=82 M

+-C1

C2

IS

I1

I1

SG

D

VGS

IDSS =12 mAVP = -3 Vrd =100 K

AC analysis of CS amplifier


• FET amplifiers give excellent voltage gain with high inputimpedance, low power consumption, and high frequency range

• Transconductance gm of FET is given as

P

DSSD

P

GS

P

DSS

GS

Dm

V

II

V

V

V

I

V

Ig

21

2

GSVD

DSd

I

Vr

constant

FET, of impedenceoutput

To make ac equivalent model• replace dc supplies by zero (short circuit)• replace coupling /bypass capacitor by short

circuit• Remove elements bypassed by short circuit• define the parameters Zi, ZO, Av, and VO

+

-

G

S

D

S

VGS rd

JFET ac equivalent circuit

gmVGS

FET: ac analysis of CS amplifier


i

Oi

Ddm

i

OV

DdO

i

I

IA

RrgV

VA

RrZ

RRZ

gain Current

gain Voltage

21

+

-VGS rd

ac equivalent circuit

gmVGS

VDD

Voltage divider bias CS amplifier

IDRDR1

C1 C2

RSR2

SG

D

+Vi

-

+

VO

-

ac equivalent

IDRDR1

+-

R2

SG

D

VGS

+Vi

-

+

VO

-R2

R1 RD

CS

+

-

Vi

+

-

VO

Rec101 unit ii (part 3) field effect transistor

Engineering