Real Time Correlator in FPGA Xu ZhiJun, Zhang XiuZhong Shanghai Astronomical Observatory China 4 th IVS General Meeting January 9, 2006.

Real Time Correlator in FPGA

Xu ZhiJun, Zhang XiuZhongShanghai Astronomical Observatory China

4th IVS General MeetingJanuary 9, 2006

OUTLINE

Main Characteristics Architecture of the Correlator FFT & MAC Board Some results Future Plan

1. 3 Stations FX Correlator ( 5 stations, 8 IFs )

2. date rate ： 0 - 32M samples/s, 1 or 2 bits/sample

3. Integration Time ： 32.768 millisecond – 1 hour (typical 5s)

4. Input data format: MKIV, MKV or others( VSI, VLBI)

5. data source ： Disk Array, Network

6. Output: via net and disk files ( in FITS format)

7. Fringe searcher, Phase Cal ( in Hardware)

Main Characteristics

Architecture of Correlator

PBD

PBD

PBD

PBI

PBI

PBIFFT &

MAC

LTA(PC)

MCCSystem Clock, Start/Stop control Fringe

search

PCAL

RS232

RS2327300A

7300A

7300A

7300A/RS232

3 Station8Ch

7300A

BENEFITS:

Fringe Finder

Phase Calibration

10Mbps data streamfrom network

256Mbps data stream from Disk Array

Hard Disk Array Storage

2Bit,8Ch

RS232

Station 1MKV

net

Station 2MKV

net

Station 3MKV

net

CCC (PC) 32 users RS232

Delay Model

FPGA

Delay Model

1G DDR ram

LTA Monitor (real time fringe display)

PBD

CCC

LTA

MOXA Card

PBI

(xc2v3000)

FFT & MAC

(xc4vsx35)

DataOutput

MAC

FFT16bitsScaled

Fixed Point

FRINGE

DELAY

16bits

LTA

7300A

PBI_1

Model Input

FSTC

MCC

DATA

CLKPBI_1

PBI_2

PBI_3

32M 32M 160M

8M

4M

DATA

CLKPBI_2

DATA

CLKPBI_3

FFT & MAC Board Diagram

192x3 bits 192x3 bits 192x3 bits

160x1024 bits （ linear model period ）

CLK_4M

RESET

READY_PARA

CLK_PARA

PARASTR

Model Input - Time DiagramPeriod of 6 coefficient polynomial = 1min

C1

C2

C3

CLKPBI_1

CLKPBI_2

CLKPBI_3

CLKFRINGE

C1=6 C2=4 C3= -3

Integer Bit Delay

i= 1, 2 …, linear Model period (160x1024 bits)

Sine-Cosine Look-Up Table

Sine

Cosine

16bits

PBI-1

14bits Unsigned

PBI-2 PBI-3

16bits

1(b) 2(b) 3(b)

1(a)

RAM16x2x1024

2(a)

RAM16x2x1024

3(a)

RAM16x2

x1024

PING-PANG RAM Xilinx IP Core

3x2x16 bits

‘1’ = x“4000” ‘0’ = x”C000”

Fringe Stopping 1 ibai

Complex Multiply

1(b) 2(b) 3(b)

1(a)

RAM16x2

x1024

2(a)

RAM16x2x1024

3(a)

RAM16x2

x1024

PING-PANG RAM

FFT

16 bits1024 Fixed Point

Xilinx IP Core

DATA_R DATA_I (16 bits)

1

2

3

Address

10 bits

Index

9 bits

FFT_R

16 bits

Done

FSTC

FFT_I

FFT (Fast Fourier Transform)

τ = d + e(f-1) f= 1, 2 …,FFT num per linear Model period (160)FSTC = i* τ/ N i=1, 2 … , N/2 N is FFT point

Sine-Cosine Look-Up Table

Sine

Cosine

16bits Sign

FFT_R

14bits Unsigned

FFT_I

16 bits

1(b) 2(b) 5(b)

1(a)

RAM

16x2x512

2(a)

RAM16x2x512

5(a)

RAM16x2x512

PING-PANG RAM

Xilinx IP Core

1

DATA_R DATA_I (16 bits)2 3

DATA_R = FFT_R * Cosine - FFT_ I * SineDATA_ I = FFT_ I * Cosine + FFT_R * Sine

FSTC (Fractional Sample Time Correction)

X_R

16 bits

X_I

Y_R Y_I

16 bits

Dout_R Dout_I

R

RAM42x512

I

RAM42x512

R

RAM42x512

I

RAM42x512

1~1023 次

1024 次

Output RAM

Acc RAM

42x2 bits

42x2 bits

42x2 bits

DOUT_R = X_R * Y_R + X_I * Y_I

DOUT_ I = X_I * Y_R - X_R * Y_I

MAC (multiple and accumulate)

ML402 Evaluation Platform (V4-SX35)

FFT & MAC Board

xc2v3000Number of MULT18X18s 37 out of 96 38% Number of RAMB16s 86 out of 96 89% Number of SLICEs 7301 out of 14336 50%

xc4vsx35Number of DSP48s 43 out of 192 22% Number of RAMB16s 76 out of 192 39% Number of Slices 6056 out of 15360 39%

FPGA Chip Usage

Results – Simulation data

Station 1 - Station 2 Station 1 - Station 3 Station 2 - Station 3

Results – TC-1 Satellite

The Fringe of the

SH-UR Baseline

TC-1 observation

with Integration

time of 62.5 ms

Results – TC-1 Satellite (cont.)

The Fringe of the

SH-UR Baseline

TC-1 observation

with Integration time

of 4 seconds

Future Plan

5 stations, 8 IFs Network creation System auto-operation software developm

ent Hardware Fringe searcher, Phase Cal

Thank you