1 RCU to FECs CONNECTORS BUS TRANSCEIVERS FPGA XILINX Virtex-II Pro FINAL RCU (FECs side) FPGA MAIN FUNCTION • Power-on Procedure • FEE Initialization • Dataflow Control • FEE Safety Control Reconfiguration Auxiliary Devices - FLASH Memory - FLASH FPGA (ProASIC+) Readout Control Unit 1/3 FPGA for final RCU • Real-time readback of configuration data for verification • Partial reconfiguration while running