HLR Core allocation and relocation Core allocation and relocation management for self dynamically management for self dynamically reconfigurable architectures reconfigurable architectures Massimo Morandi: [email protected]Marco Novati: [email protected]Reconfigurable Computing Italian Meeting Reconfigurable Computing Italian Meeting 19 December 2008 Room S01, Politecnico di Milano - Milan (Italy)
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HLR
Core allocation and relocation Core allocation and relocation
management for self dynamically management for self dynamically
CoreCore: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG)
IPIP--CoreCore: a core described using a HD Language combined with its communication infrastructure (i.e. the bus interface)
Reconfigurable Functional UnitReconfigurable Functional Unit: an IP-Core that can be plugged and/or unplugged at runtime in an already working architecture
Reconfigurable RegionReconfigurable Region: a portion of the device area used to implement a reconfigurable core
6
Relocation: The ProblemRelocation: The Problem
Set of Available
Functionalities
FiArea/Time
Legenda:
A2/1
B 1/2
C2/2
D 1/1 E 1/1
F 2/2
RR3RR2RR1
A
RR3RR2RR1
F
RR3RR2RR1
D
RR3RR2RR1
B
RR3RR2RR1
C
E
RR3RR2RR1
RFU
Implementations
7
Relocation: MotivationRelocation: Motivation
A
E
DC
B
F
2/1
2/2
1/2
1/1
1/1
2/2
Demanded Tasks
TiArea/Time
Request
Sequnce
Legenda: D
R2D
R2F
F
Area
Time
Area
AB
AB
Rec. C
C
Rec. F
F
Rec. E
E
Rec. C
C
Rec. D
D
8
Relocation: RationaleRelocation: Rationale
Bitstreams relocation technique to:
speedup the overall system execution
reduce the amount of memory used to store partial bitstreams