RATIONALE · 2016. 1. 22. · RATIONALE 10 years ago => 1 h battery life. 5 years => medium-length flight. today => Rome-New York flight with almost no problem. Your MP3 player can

OUTLINE • Introduction

– Motivation

– The Dark Silicon Problem

– Approaches

• Low-level methodologies for power management

– Clock related

– Power related

• Architectural methodologies by examples

– Mapping

– IP specific techniques: ASIPs and IP management

– DSE

– Dataflow-based approaches

• Final Remarks

RATIONALE

RATIONALE

10 years ago => 1 h battery life. 5 years => medium-length flight. today => Rome-New York flight with almost no problem.

Your MP3 player can hold more songs than those that can be played without

running out of power.

RATIONALE

• MORE FEATURES in their mobile devices:

– MP3, Camera, Video, GPS...

• LONG BATTERY LIFE

– Convenient form factor, affordable price

• Battery technology is NOT EVOLVING FAST ENOUGH!

– Need to manage power consumption

RATIONALE

form factor small volume low weight.

2013 White Paper by Juniper Research

RATIONALE

Energy standards may limit the usable power and/or the devices that can be plugged in a network.

Server people spend more money on the cooling

system than in the computing system itself.

RATIONALE

2013 Survey by SONICS (leader in NoC design, http://sonicsinc.com/) over 318 customers.

RATIONALE

RATIONALE

POWER CONSUMPTION

• Static: due to the leakage current, present when the circuit is not switching.

– As transistors get smaller, their channel lengths become shorter and leakage currents increase.

– Do not depend on switching and operating frequency.

• Short-circuit: in CMOS technology when the output line of a transistor is switching, there is a period of time when both the PMOS and the NMOS transistors are on.

• Dynamic: it is due to the charging and discharging of the load capacitance at the gate output in transistor, determined by the formula C·V2·f. It decrements quadratically with voltage, but voltage levels seem to be stabilizing in the 1.0-1.2 V.

THE 90nm INFLECTION POINT

Leakage goes up dramatically,

moving from 130 nm to 90 nm technology

“DARK SILICON”

H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, D. Burger, “Dark silicon and the end of multicore scaling”, IEEE Micro, May/June 2012

DARK SILICON: gap between projected speed-up and the expected one with each

technology generation.

WHAT TO DO?

0%

20%

40%

60%

80%

100%

Power Optimization Potential

Architectural

Synthesis

Gate

Layout

TEXTBOOK TECHNIQUES

• Design related techniques: Multi Vt, Clock gating, Power gating, Multi Vdd, DVFS.

• Architecture related techniques: power-constrained DSE, hw customization and IP specific techniques, parallelism, mapping.

• Process related techniques: Multi Vt, PD SOI, FD SOI, FinFet, Body

Bias, Multi oxide devices, Minimize capacitance by custom design.

Dynamic Power Clock gating

Variable frequency Voltage islands

Variable power supply Multi power supply

DVFS

Leakage Power Multi-threshold dev.

Power gating Back (substrate) bias Multi-oxide devices

SOI CMOS


– Motivation


– Approaches


– Clock related

– Power related


– Mapping


– DSE


• Final Remarks

REDUCE CLOCK RELATED POWER

Reduce frequency whenever you can. Stop the clock when the component is not active.

Fine-Grained Coarse-Grained

• Power consumed by flip-flops.

• Power consumed by combinatorial logic driven by registers.

• Power consumed by the clock buffer tree.

V4 V4

REDUCE VOLTAGE RELATED POWER

• Power-aware partitioning (either logical or physical).

• Switching-off power island brings local leakage to zero.

• Modes of operation -> power down all the idle chip regions.

Reduce the voltage level of a power island whenever you can. Switch it off when it is not active.

V1 V3 V2

V1

V3

V2 V4

V1 OFF V2

V1

OFF

V2 V4

V4

V1 OFF OFF

OFF

V3

OFF OFF

SVS Static Voltage Scaling

POWER GATING TECHNIQUE • Sleep transistor

– software managed: a driver schedules power down operations.

– hardware managed: dedicated power management controllers.

SLEEP TRANSISTOR

Fine-Grained Coarse-Grained

POWER GATING TECHNIQUE

POWER-DOWN BLOCK

P_UP

ALWAYS-ON BLOCK

MAIN REGISTER

SHADOW REGISTER

SAVE RESTORE

POWER DOMAIN 1

0.8 V

POWER DOMAIN 2

1.2 V

POWER-DOWN BLOCK

Vdd

Level shifters

Power Switch-Off Cell

Isolation Cell

Retention Register

THE COMMON POWER FORMAT: MSV



# define the library sets

define_library_set -name set1_bc -libraries {lib1_bc lib2_bc}

define_library_set -name set1_wc -libraries {lib1_wc lib2_wc}

define_library_set -name set2_bc -libraries lib3_bc

define_library_set -name set2_wc -libraries lib3_wc

define_library_set -name set3_bc -libraries lib4_bc

define_library_set -name set3_wc -libraries lib4_wc

worst case

best case


# define the level shifters define_level_shifter_cell -cells LVLLHEHX* \ -input_voltage_range 0.8 \ -output_voltage_range 1.0 \ -output_power_pin VDD \ -ground VSS \ -direction up \ -valid_location from define_level_shifter_cell -cells LVLLHX* \ -input_voltage_range 0.8 \ -output_voltage_range 1.2 \ …

0.8 V to 1.0 V


set_design top

# create power domains

create_power_domain -name PD1 -default

create_power_domain -name PD2 -instances instance_B

create_power_domain -name PD3 -instances instance_C

# create nominal conditions

create_nominal_condition -name low -voltage 0.8

create_nominal_condition -name medium -voltage 1.0

create_nominal_condition -name high -voltage 1.2

# create power mode

create_power_mode -name PM -domain_conditions {PD1@low PD2@medium PD3@high} \

-default

target design


set_design top

# create power domains

create_power_domain -name PD1 -default

create_power_domain -name PD2 -instances instance_B

create_power_domain -name PD3 -instances instance_C

# create nominal conditions

create_nominal_condition -name low -voltage 0.8

create_nominal_condition -name medium -voltage 1.0

create_nominal_condition -name high -voltage 1.2

# create power mode

create_power_mode -name PM -domain_conditions {PD1@low PD2@medium PD3@high} \

-default

target design

power domains

nominal conditions

power mode

COMMON POWER FORMAT: MSV

# associate library sets with nominal conditions update_nominal_condition -name low -library_set set1_wc update_nominal_condition -name medium -library_set set2_wc update_nominal_condition -name high -library_set set3_wc # create rules for level shifter insertion create_level_shifter_rule -name lsr1 -from PD1 -to PD2 create_level_shifter_rule -name lsr2 -from PD2 -to PD3 create_level_shifter_rule -name lsr3 -from PD1 -to PD3

library vs nominal conditions

COMMON POWER FORMAT: MSV

# associate library sets with nominal conditions update_nominal_condition -name low -library_set set1_wc update_nominal_condition -name medium -library_set set2_wc update_nominal_condition -name high -library_set set3_wc # create rules for level shifter insertion create_level_shifter_rule -name lsr1 -from PD1 -to PD2 create_level_shifter_rule -name lsr2 -from PD2 -to PD3 create_level_shifter_rule -name lsr3 -from PD1 -to PD3

library vs nominal conditions

level shifter rules

COMMON POWER FORMAT: PSO

POWER DOMAIN 1

0.8 V

POWER DOMAIN 2

1.2 V

COMMON POWER FORMAT: PSO

POWER-DOWN BLOCK P_UP

ALWAYS-ON BLOCK

MAIN REGISTER

SHADOW REGISTER

SAVE RESTORE

POWER-DOWN BLOCK

Vdd

# define the isolation cells define_isolation_cell -cells ISOLN* -enable EN -valid_location on # define the state retention cell define_state_retention_cell -cells *DRFF* -restore_function RETN # define the power switch cells define_power_switch_cell -cells "hd8DM hd16DM hd32DM hd64DM" \ -stage_1_enable SLEEP -type header define_power_switch_cell -cells "hd8M hd16M hd32M hd64M" \ -stage_1_enable !SLEEP -type header …..

ADVANCED POWER REDUCTION

• Sw power manager are slower than the hw ones, but they do not suffer the power management deadlock phenomenon.

Under(Over)volting whenever you can to minimize(maximize) power(performance). Frequency tuning at the island level.

Voltage Regulator

Mode Control

A B

C

PROGRAMMABLE

DVFS Dynamic Voltage Frequency Scaling

Voltage Regulator

Mode Control

A B

C

AVS Adaptive Voltage Scaling

MONITOR

MON.


– Motivation


– Approaches


– Clock related

– Power related


– Mapping


– DSE


• Final Remarks

MAPPING: SONICS Comm. Layer

I I I I I

T T T T T

Always-On Domain


Mapping and connectivity are of paramount importance to reduce power dissipation at

the communication layer level.

I I I I I

T T T T T

Always-On Domain

I I I I I

T T T T T




I I I I I

T T T T T

Always-On Domain

I I I I I

T T T T T




I I I I I

T T T T T

Always-On Domain

I I I I I

T T T T T I I I I I

T T T T T




I I I I I

T T T T T

Always-On Domain

I I I I I

T T T T T I I I I I

T T T T T

• To avoid any issue related to the the power management deadlock phenomenon any initiator needs to


I I I I I

T T T T T

POWER MANAGER


1. hold its traffic and


I I I I I

T T T T T

POWER MANAGER

1


1. hold its traffic and 2. send a request to the

power manager


I I I I I

T T T T T

POWER MANAGER

1

2



power manager 3. Wait for the answer of

the power manager that is positive as soon as the requested unit is back on


I I I I I

T T T T T

POWER MANAGER

1

2






I I I I I

T T T T T

POWER MANAGER

1

2

3





4. transmits its data.


I I I I I

T T T T T

POWER MANAGER

1

2

3

4

IP-SPECIFIC: ASIP • Heterogeneous and customizable processing element: the

Silicon Hive’s (Intel’s) Processor Architectural Template

Function units

Memories

Data Routing Network

Register files

Issue slots

Configurable parameters • Number of VLIW ways (issue slots), • Number and size of register files • Number and size of processor internal memories

• Set of function units inside every issue slot • Data Routing Network topology • Customized instructions

IP-SPECIFIC: The ARM big.LITTLE

• Saves 40% SoC power cons. in common workload (e.g. web browsing )

• Increases performance by 40% in highly threaded workloads vs ARM Cortex-A15

http

://ww

w.th

inkb

iglittle.co

m/


– Motivation


– Approaches


– Clock related

– Power related


– Mapping

– IP specific techniques: ASIPs and IP managment

– DSE


• Final Remarks

FINAL REMARKS

• All the different SoC designers need to take into consideration the power issue problem.

• Both design methodologies and architectural approaches should be taken into consideration and combined to tackle power management issues: – Manage power in all modes in which a design operates

• Dynamic power during device operation including active leakage

• Static power dissipation during standby

– Maintain device performance while minimizing power consumption

• Aggressive power optimization when running at reduced performance levels

• Combine low power techniques

RATIONALE · 2016. 1. 22. · RATIONALE 10 years ago => 1 h battery life. 5 years => medium-length flight. today => Rome-New York flight with almost no problem. Your MP3 player can

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