RapidIO Technology RapidIO Technology Applied in Applied in Multifunction Phased Array Radar (MPAR) Multifunction Phased Array Radar (MPAR) (Introduction and literature Review) Yu Sun Department of Electrical and Computer Engineering Radar Innovations Laboratory University of Oklahoma University of Oklahoma Final Presentation of ECE5990 031 Final Presentation of ECE5990 031 Special Study Special Study Advisor: Dr. Yan Zhang Advisor: Dr. Yan Zhang
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RapidIO Technology Applied in Multifunction Phased Array Radar (MPAR) RapidIO Technology Applied in Multifunction Phased Array Radar (MPAR) (Introduction.
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RapidIO Technology RapidIO Technology Applied in Applied in
Multifunction Phased Array Radar (MPAR)Multifunction Phased Array Radar (MPAR)(Introduction and literature Review)
Yu SunDepartment of Electrical and Computer Engineering
Radar Innovations Laboratory
University of OklahomaUniversity of Oklahoma
Final Presentation of ECE5990 031 Final Presentation of ECE5990 031 Special StudySpecial StudyAdvisor: Dr. Yan ZhangAdvisor: Dr. Yan Zhang
Why RapidIO is preferred in Multifunction Phase Array Radar?Why RapidIO is preferred in Multifunction Phase Array Radar?
Future MPAR architectureFuture MPAR architecture
Transmit-Receive Elements (TR) Transmit-Receive Elements (TR) --- partitioned into “sub-arrays” --- partitioned into “sub-arrays” Overlapped Sub-Array BeamformerOverlapped Sub-Array Beamformer --- controlled by analog circuitry --- controlled by analog circuitry Digital Transceiver Digital Transceiver --- A/D conversion --- A/D conversion Digital Beamforming (DBF)Digital Beamforming (DBF) --- all beams are computed concurrently --- all beams are computed concurrently ~1 Tera (10~1 Tera (101212) operations per second ) operations per second Radar Signal processorRadar Signal processor --- Data analysis, processing --- Data analysis, processing
Estimated transportationEstimated transportation throughput of the parallel DBF scheme:throughput of the parallel DBF scheme: 1 Tera (101 Tera (101212) operations per second.) operations per second. (level of 1 Giga-byte/s I/O bandwidth)(level of 1 Giga-byte/s I/O bandwidth) significant challenge by using general-purpose programmable processors (e.g., DSPs)significant challenge by using general-purpose programmable processors (e.g., DSPs) but tractable using field programmable gate arrays (FPGAs)but tractable using field programmable gate arrays (FPGAs)
Diagrams of fully parallel DBF design in MPARDiagrams of fully parallel DBF design in MPAR
Characters of MPAR data communication: Characters of MPAR data communication: complex network switches, high-speed transactions (Interconnection) complex network switches, high-speed transactions (Interconnection)
Multifunction Phased Array Radar (MPAR)’s needs on Multifunction Phased Array Radar (MPAR)’s needs on high-speed data transportationhigh-speed data transportation
Example RapidIO Architecture:Example RapidIO Architecture: interconnection between systems & devicesinterconnection between systems & devices
Our Current Plan:
Applying High-Speed Serial I/O to Phased Array Radar
Multifunction Phase Array Radar signal processing diagramMultifunction Phase Array Radar signal processing diagram
a. Acquire digital data from ADC ( in Phase Array Radar)a. Acquire digital data from ADC ( in Phase Array Radar)b. Implement RapidIO on FPGAb. Implement RapidIO on FPGAc.c. Use RapidIO to transfer data within & between FPGA boardsUse RapidIO to transfer data within & between FPGA boardsd.d. Build RapidIO physical channel on PCBBuild RapidIO physical channel on PCB
Overall design stepsOverall design steps
FPGA computer-aided system designFPGA computer-aided system design design tools: Xilinx ISE 8.2 design tools: Xilinx ISE 8.2 ModelsimModelsim
challenges:challenges: understand, simulate and synthesize high-speed serial understand, simulate and synthesize high-speed serial protocolsprotocols
RapidIO FPGA hardware realizationRapidIO FPGA hardware realization FPGA board: Xilinx Virtex II – Pro FPGA board: Xilinx Virtex II – Pro with RocketIO transceiverswith RocketIO transceivers challenges:challenges: Place & Route, hardware debugging Place & Route, hardware debugging
RapidIO signal integrity designRapidIO signal integrity design & Test& Test Design tools: HFSS 10.1 Design tools: HFSS 10.1 Ansoft Designer 3.5Ansoft Designer 3.5 multi-layer PCB multi-layer PCB
(OrCAD)(OrCAD) challenges:challenges: design layout of differential pairs on design layout of differential pairs on
PCB, PCB, minimize noise & minimize noise &
crosstalks,crosstalks, optimize signal qualityoptimize signal quality
1.1.
2.2.
3.3.
FPGA board: Xilinx Virtex II Pro
Virtex-II Pro Generic Architecture OverviewVirtex-II Pro Generic Architecture Overview
RocketIO blocks --- the basis of Xilinx's RapidIO technology & protocol RocketIO blocks --- the basis of Xilinx's RapidIO technology & protocol --- 3.125 Gb/s maximum serial communication speed--- 3.125 Gb/s maximum serial communication speed
Xilinx Virtex-II Pro XC2VP20 FF1152 KitXilinx Virtex-II Pro XC2VP20 FF1152 Kit P160 Prototype Module with I/O HeaderP160 Prototype Module with I/O Header
P160 Communications Module 2P160 Communications Module 2 P160 Analog ModuleP160 Analog Module
Our FPGA development kitsOur FPGA development kits
Digital Clock Management (DCM)Digital Clock Management (DCM)
RapidIO signal integrity challenge:--- Gigabit transactions cause jitters, phase shift, cross-talk on wires
--- difficult to layout communication wires on PCB
a. Jittera. Jitter: Short-term variation of signal transaction from their ideal position.: Short-term variation of signal transaction from their ideal position.
Advantage: less susceptible to noise, jitters, and cross-talksAdvantage: less susceptible to noise, jitters, and cross-talks Better Signal IntegrityBetter Signal Integrity EMI generation is greatly reduced.EMI generation is greatly reduced.This becomes more important as edge rates increase and higherThis becomes more important as edge rates increase and higherfrequencies appear in I/O system.frequencies appear in I/O system.
Transmit (TX) & Receive (RX) Transmit (TX) & Receive (RX) differential pairdifferential pair N & P nodes of differential pairN & P nodes of differential pair
Differential pair’s effect on noiseDifferential pair’s effect on noise
If two pair routed very closely together: If two pair routed very closely together: noise will affect both wires identicallynoise will affect both wires identically
Receiving gate:Receiving gate:Only interested in difference between Only interested in difference between two signalstwo signals---- less susceptible to noise ---- less susceptible to noise
Better eye diagram of Better eye diagram of Vertex II test platform Vertex II test platform differential channel differential channel with 2 feet of co-ax with 2 feet of co-ax (Data Rate (Data Rate = 3.125 Gbps)= 3.125 Gbps)
Scope eye diagram of Scope eye diagram of normal test stimulus normal test stimulus by 10 by 10 inch using inch using conventional twisted conventional twisted lineline
Twisted differential line on multi-layer PCB Twisted differential line on multi-layer PCB
Measured Measured radiated emissionradiated emission spectrum spectrum from the differential lines on a PCB.from the differential lines on a PCB. (a) Radiation from the conventional (a) Radiation from the conventional
differential line differential line (b) radiation from the proposed Twisted (b) radiation from the proposed Twisted
Differential Line.Differential Line.
Comparison of the measured Comparison of the measured crosstalkcrosstalk
voltagevoltage waveforms of the two differential waveforms of the two differential
Differential output with different output capacitances
Differential Pair Differential Pair ModelsModels
&&Simulation resultsSimulation results
Tools:Tools:Avnet Designer 3.5Avnet Designer 3.5
HFSS 9.1HFSS 9.1
ConclusionConclusion
High-speed serial links are preferable in Phased Array High-speed serial links are preferable in Phased Array RadarRadar Large data flow rate in MPARLarge data flow rate in MPAR High-speed serial transceiverHigh-speed serial transceiver Save FPGA pin countsSave FPGA pin counts
How to implement RapidIOHow to implement RapidIO FPGAFPGA Physical layer PCBPhysical layer PCB
Challenges in RapidIO designChallenges in RapidIO design How to keep good signal integrity?How to keep good signal integrity? Minimize noise, crosstalks, jitters……Minimize noise, crosstalks, jitters……
Serial link technologies for RapidIOSerial link technologies for RapidIO Clock Correction, 8B/10B converter, Channel Clock Correction, 8B/10B converter, Channel Bonding……Bonding……