Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip Ran Manevich, Leon Polishuk, Israel Cidon, and Avinoam Kolodny. M odule M odule M odule M odule M odule M odule M odule M odule M odule M odule M odule M odule Group Research Electrical Engineering Department Technion – Israel Institute of Technology Haifa, Israel 1 QNoC
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Ran Manevich, Leon Polishuk, Israel Cidon, and Avinoam Kolodny.
Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip. Ran Manevich, Leon Polishuk, Israel Cidon, and Avinoam Kolodny. . Electrical Engineering Department Technion – Israel Institute of Technology Haifa, Israel. QNoC. Research. Group. Hierarchical NoCs . PyraMesh - PowerPoint PPT Presentation
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Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-
Chip
Ran Manevich, Leon Polishuk, Israel Cidon, and Avinoam Kolodny.
Module
Modu le Module
Modu le Modu le
Modu le Modu le
Modu le
Module
Modu le
Modu le
Modu leGroup
Research
Electrical Engineering DepartmentTechnion – Israel Institute of Technology
Haifa, Israel
1
QNoC
Hierarchical NoCs
Hybrid Ring/Mesh S. Bourduas and, Z. Zilic, “Latency reduction of global traffic in wormhole-routed meshes using hierarchical rings for global routing.” ASAP 2007.
PyraMesh R. Manevich, I Cidon and, A. Kolodny. “Handling global
traffic in future CMP NoCs” SLIP 2012.
2
Hierarchical NoCs lower hop distances
2D Mesh 14
Hops
PyraMesh 10
Hops
3
Max. Hop distance vs. Number of Modules
# of Modules
# of Modl sog ule
Go Go
Hierarchical
NoCs!!!
LONG LINKSWho is right?
4
Parallel link delay model
Elmore’s delay:20.5wired RCl
[ / mm] [F/ mm], [ ],R C l mm
Repeated wire [Bakoglu - 1990]:
0, 0 00.7 0.4 0.7wire repeated R R
R
R C R Cd l hS C hS C
hS
R
0 0
[repeaters / mm], h Bakoglu 's optimal repeater sizeS repeater size normalized to hR ,C input C and output R of min size inverter
20.5 wired RCl
5
Links delay in 16x16 hierarchical NoC
300 mm2 die
Short1 mm
Medium1.9 mm
Long3.4 mm
16x16 Mesh. 8x8, 4x4 Upper Levels
Elmore’s Delay – Unrepeated, min. size global links (ITRS):
29 nm Technology
Short: 0.11nsMedium: 0.41nsLong: 1.31ns
12X
~17mm
LONG LINKS
6
Adjusting delay of parallel links
Wire sizing: Lower RC delay by changing wire pitch (S and W).
Repeaters insertion: Lower wire delay by inserting repeaters.
7
Wire design parameters
ΛW – Scaling of W vs. min. size global wire [ITRS].