Ramon Chips Ramon Chips Rad-Tolerant design of all-digital DLL Tuvia Liran [[email protected] ] Ran Ginosar [[email protected] ] Dov Alon [[email protected] ] Ramon-Chips Ltd., Israel Ramon Chips is named in memory of Col. Ilan Ramon, Israeli astronaut who died on board the Columbia space shuttle, 1/2/2003 Ramon Chips
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Ramon Chips is named in memory of Col. Ilan Ramon, Israeli astronaut who died on board the Columbia space shuttle, 1/2/2003
Ramon Chips
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Outline• Issues with analog DLL/PLL• All-digital DLL (ADDLL) architecture• Radiation hardening of ADDLL• Applications of ADDLL• Integration of ADDLL in SOC• Future developments
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Issues with analog PLL
PFD+
CPVCO
/N
clk_refclk_out
Ionizing particle
Issues:- Sensitive to TID of analog- Might un-lock due to SET- Accumulate phase error due to SET- Might miss cycle due to SET- Sensitive to process, voltage, temperature
control voltage
time
time
time
frequency
control voltage
frequency
phase
Discharge by ionizing particle
Missing clock cycle
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All-digital DLL concept• Standard cell based logic
Operates at wide range of process, voltage & temperature
• Timing is controlled by logic• Fast locking / immediate re-locking• Low jitter – typically <1% of CLKREF period
PHD CTRL
DCDL
up
dn
ctrl[m-1:0]
MUL
clkfb
REFCLK
CLK1XCLK2XCLK4X
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DCDL operation
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EN0
IN
OUT
EN1 EN2
Gross tuning of delay
Fine tuning of delay
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DCDL response to control code
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DCDL4 Delay vs code
0.00E+00
2.00E-09
4.00E-09
6.00E-09
8.00E-09
1.00E-08
1.20E-08
1.40E-08
0 50 100 150 200 250 300 350 400 450
Code
Del
ay
slow typ fast up_slow up_fast dn_slow dn_fast
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Radiation hardening of ADDLL
• Key radiation hazards:• TID• SEL• Phase error due to SE• Clock spike due to SET• Reset/re-configure due to SEU/SET
• RH mitigation techniques• The use of RadSafeTM std. cells – immunity to TID &
SEL• Use of SEP flip-flops mitigates SEU – immunity to
change in control• Glitch filtering at each DCDL stage – mitigates SET
spikes• Requirements for double sampling of reset –
mitigates SET in reset/load7
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Advantages of ADDLL• Voltage range – as logic core• Temperature range – as logic core• Lock time – limited # of cycles• Re-locking time – immediate• Standby power – zero• Dynamic power – very low• Bursts of clocks - enabled• Control of slave delay lines - enabled• Area – very small• Floor planning – anywhere in the chip / I/O
strip• Immunity to Soft-Errors - Optional
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ADDLL in RadSafeTM library
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DLCTRDelay controller
PHDPhase
detector
CLKOUT
FBCLK
PHDREF
CTRL_IN ]11:0[
LDEN
REFCLK DCDLDigitally Controlled Delay
Line
DCDLEN
PH ]8:1[
CLK1X
CLK4X
LDB
FCLKEN
BCNT ]11:0[CTRLEN
CLK2X
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All-digital DLL cores• Three DLL cores for 3 frequency