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Questa® ADMS™ for A/MS Design Verification
Student Workbook
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Table of Contents
Questa ADMS for A/MS Design Verification
I
Module 1: Introduction to Questa ADMS ........................................................ 15
Objectives ........................................................................................................................................... 16
Questa ADMS Unified Platform for all Design Methodologies ........................................................ 17
Flexible — Scalable Architecture ..................................................................................................... 18
In Either Major Integration................................................................................................................. 19
Artist Link for Cadence ADE ............................................................................................................. 20
Or Questa ADMS Standalone ............................................................................................................ 21
A/MS Simulation Required Tasks ...................................................................................................... 22
Questa ADMS Flow on an Example .................................................................................................. 23
Load Design Window ......................................................................................................................... 24
Questa ADMS Main Window ............................................................................................................ 25
Selecting Signals/Nets for Viewing ................................................................................................... 26
Selecting Signals/Nets for Viewing Other Methods .......................................................................... 27
Running a Simulation ......................................................................................................................... 28
Viewing Results With EZwave: A True Mixed-Signal Waveform Viewer ....................................... 29
EZwave: Elements of the Interface .................................................................................................... 30
EZwave: Additional Tools ................................................................................................................. 31
EZwave Help ...................................................................................................................................... 32
Other Useful Information ................................................................................................................... 33
Lab Exercise – Lab 1 .......................................................................................................................... 34
Module 2: Library Management ....................................................................... 35
Objectives ........................................................................................................................................... 36
What Is a Questa ADMS Library? ..................................................................................................... 37
Logical Library Names ....................................................................................................................... 38
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Sample Initialization Files .................................................................................................................. 39
Objectives ........................................................................................................................................... 40
ADMS Library Management Commands: Library Creation ............................................................. 41
ADMS Library Management Commands: Change WORK ............................................................... 42
ADMS Library Management Commands: Library Mapping ............................................................. 43
ADMS Library Management Commands: WORK Contents ............................................................. 44
Library Management Example ........................................................................................................... 45
Commonly Used Library Management Commands ........................................................................... 47
Viewing Library Content in the GUI ................................................................................................. 48
Objectives ........................................................................................................................................... 49
Populating Libraries: Compiling Models ........................................................................................... 50
Compilation Commands ..................................................................................................................... 51
Library Compatibility Management ................................................................................................... 52
VAMAKE .......................................................................................................................................... 53
Lab Exercise – Lab 2 .......................................................................................................................... 54
Module 3: Basic Mixed-Signal Simulation ........................................................ 55
Objectives ........................................................................................................................................... 56
Questa ADMS Data Flow .................................................................................................................. 57
Steps for Running Simulations ........................................................................................................... 58
Graphical User Interface .................................................................................................................... 59
Questa ADMS GUI Settings .............................................................................................................. 60
Structure Window: Unified Design View .......................................................................................... 61
Invoking the Questa ADMS Simulator .............................................................................................. 62
Command Line vasim ........................................................................................................................ 63
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Command File .................................................................................................................................... 64
Additional vasim Examples ............................................................................................................... 65
vasim: Other Commonly— Used Options ......................................................................................... 66
vasim –cmd ….. –g/-G To Override Value of Digital or Analog Parameters .................................... 67
vasim G/-g .......................................................................................................................................... 68
Objectives ........................................................................................................................................... 69
Dofile .................................................................................................................................................. 70
Plotting Nodes .................................................................................................................................... 71
Plots in Questa ADMS GUI ............................................................................................................... 72
Save/Reuse EZwave Configuration.................................................................................................... 73
Display Simulation Output Information ............................................................................................. 74
In Case of Waveform Database Failure ............................................................................................. 75
Lab Exercise – Lab 3 .......................................................................................................................... 76
Module 4: Simulating Analog Centric Designs ................................................. 77
Objectives ........................................................................................................................................... 78
Analog — Centric Methodology ........................................................................................................ 79
Procedure for SPICE Instantiating HDL ............................................................................................ 80
.model and Y— instance Syntax ....................................................................................................... 81
Generics in Y— instance .................................................................................................................... 82
Replacing SPICE With HDL – Netlist Level ..................................................................................... 83
Example: SPICE Instantiating HDL .................................................................................................. 84
.MODEL Extension ............................................................................................................................ 85
Usage Example ................................................................................................................................... 86
SPICE Compatibility Options for Other SPICE "Flavors" ................................................................ 87
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Objectives ........................................................................................................................................... 88
Reconfigure SPICE Design ................................................................................................................ 89
.BIND Syntax ..................................................................................................................................... 90
Wildcard in .BIND ............................................................................................................................. 91
.BIND Example .................................................................................................................................. 92
.BIND: Other Arguments ................................................................................................................... 93
.BIND: Resolving Port Mismatch ...................................................................................................... 94
vamatch .............................................................................................................................................. 95
vamatch Example ............................................................................................................................... 96
vamatch: Other Arguments ................................................................................................................ 98
Lab Exercise – Lab 4 .......................................................................................................................... 99
Module 5: Simulating Digital Centric Designs ............................................... 101
Objectives ......................................................................................................................................... 102
HDL Instantiating SPICE — Typical Situation ............................................................................... 103
Starting From a Questa Digital Simulation ...................................................................................... 104
Simulating the Digital Design With Questa ADMS ........................................................................ 105
Replacing Digital With Spice ........................................................................................................... 106
Simulating the MS Design With Questa ADMS .............................................................................. 107
Access to Both Viewers in Questa ADMS ....................................................................................... 108
Objectives ......................................................................................................................................... 109
How Can QuestaSim Instantiate SPICE? ......................................................................................... 110
vaspi Command Does the Job .......................................................................................................... 111
vaspi Mechanism .............................................................................................................................. 112
vaspi Example .................................................................................................................................. 114
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Verilog Testbench ............................................................................................................................ 115
VHDL Testbench ............................................................................................................................. 116
Objectives ......................................................................................................................................... 117
Port Mismatch Between QuestaSim and SPICE .............................................................................. 118
vaspi Port — Mapping Options ........................................................................................................ 119
Objectives ......................................................................................................................................... 120
vaspi -interactive .............................................................................................................................. 121
Port Mapping Options ...................................................................................................................... 122
Moving Pins/Ports ............................................................................................................................ 123
vaspi: Map by Name ........................................................................................................................ 124
vaspi: Map by Name Result ............................................................................................................. 125
vaspi: Unconnected Pins .................................................................................................................. 126
vaspi: Save Port Mapping ................................................................................................................ 128
Port Association File ........................................................................................................................ 129
Objectives ......................................................................................................................................... 130
Running vaspi Within a Digital Library ........................................................................................... 131
Vaspi - The Design Unit is VHDL ................................................................................................... 132
Vaspi - The Design Unit is Verilog .................................................................................................. 133
Vaspi Extensions .............................................................................................................................. 134
Vaspi -noarch ................................................................................................................................... 135
Vaspi -noarch -cktname.................................................................................................................... 136
Vaspi -noarch -digname ................................................................................................................... 137
Objectives ......................................................................................................................................... 138
Compilation Commands ................................................................................................................... 139
Instance Compilation ........................................................................................................................ 140
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More About VHDL Compilation ..................................................................................................... 141
Verilog-AMS Instantiating SPICE ................................................................................................... 142
VHDL-AMS Specific Rules ............................................................................................................. 143
Lab Exercise – Lab 5 ........................................................................................................................ 144
Module 6: Boundary Elements ........................................................................ 145
Objectives ......................................................................................................................................... 146
Intelligent Converter Insertion ......................................................................................................... 147
Mixed Connections Need Boundary Elements ................................................................................ 148
Bi-Directional Boundary Insertion ................................................................................................... 149
Boundary Insertion for Inout ............................................................................................................ 150
Tunneling ......................................................................................................................................... 151
Objectives ......................................................................................................................................... 152
Built — In Converter Insertion Procedure ....................................................................................... 153
Built-In Converters ........................................................................................................................... 154
std_logic D2A — Equivalent Circuit .............................................................................................. 155
std_logic D2A — Impedance .......................................................................................................... 156
std_logic D2A — Other Parameters ................................................................................................ 157
std_vsrc (fast_std_logic) and std_supply ......................................................................................... 158
std_logic A2D .................................................................................................................................. 159
Supply Dependent Converters .......................................................................................................... 160
VHDL-AMS Custom Boundary Model ........................................................................................... 162
User Defined VHDL-AMS D2A Converter ..................................................................................... 163
VerilogAMS Connect Rules ............................................................................................................. 164
Connectrules Syntax ......................................................................................................................... 165
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Connectrules Syntax Extension ........................................................................................................ 166
D2D Converters ................................................................................................................................ 167
Objectives ......................................................................................................................................... 168
Global Assignment ........................................................................................................................... 169
.defhook Specification ...................................................................................................................... 170
A Fragment of .conv File for a Uni-Directional Net ........................................................................ 172
A Fragment of .conv File for a Bi-Directional Net .......................................................................... 173
Required Three Steps ....................................................................................................................... 174
Lab Exercise – Lab 6 ........................................................................................................................ 175
Module 7: Advanced Simulation Techniques ................................................. 177
Objectives ......................................................................................................................................... 178
Hierarchical Design Objects References .......................................................................................... 179
Hierarchy Path Separator.................................................................................................................. 180
Spice .plot Command ....................................................................................................................... 181
DO-File Commands - Hierarchical Definitions ............................................................................... 182
Objectives ......................................................................................................................................... 183
Questa ADMS Offers "Net Spy" to Extend Hierarchical References to VHDL/VHDL-AMS ....... 184
Net Spy for Analog and Digital Objects .......................................................................................... 185
Net Spy for Analog and Digital Objects .......................................................................................... 186
Net Spy for Analog Objects ............................................................................................................. 187
Objectives ......................................................................................................................................... 189
Incremental Runs .............................................................................................................................. 190
Saving Simulation State During DC or Transient ............................................................................ 191
Restoring a Saved Simulation State ................................................................................................. 192
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Typical Analog Verification Flow Requirements Integrated Seamlessly Within Questa ADMS ... 193
Extends SPICE Diagnostic Analyses to Mixed-Signal .................................................................... 194
Multiple Runs ................................................................................................................................... 195
Dedicated Commands for Multiple-Run Simulations ...................................................................... 196
Dedicated Commands for Multiple-Run Simulations Examples ..................................................... 197
Objectives ......................................................................................................................................... 198
Eldo Premier ..................................................................................................................................... 199
Premier Use Model Allows Quick Adoption ................................................................................... 200
Eldo Continuous Performance Improvement ................................................................................... 201
Speedup Multithreading Scalabity Improvement ............................................................................. 202
Speedup Even Better With Large Designs ....................................................................................... 203
Performance Improvements ............................................................................................................. 204
PREMIER_MODE and Other Accuracy Options ............................................................................ 205
Multi-Threading ............................................................................................................................... 206
Multi-Threading on a Loaded Machine............................................................................................ 207
Objectives ......................................................................................................................................... 208
Interrogating Nets in Contributor Window ...................................................................................... 209
Interrogating Mixed-Signal Nets ...................................................................................................... 210
Viewing Current Contributions on an Analog Net ........................................................................... 211
Current Flow Window ...................................................................................................................... 212
Other TCL Commands for Debugging ............................................................................................. 213
Analog Sequential Debugging for Verilog-AMS ............................................................................. 214
Analog Sequential Debugging for Verilog-AMS ............................................................................. 215
Dynamic Control of Analog Precision ............................................................................................. 216
Dynamic Control of Analog Precision at HDL/Tcl Level ............................................................... 217
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Objectives ......................................................................................................................................... 218
Analyzing Design or Simulation Issues Using the Statistics File .................................................... 219
Stat File Content — Three Main Sections ...................................................................................... 220
Using Stat File to Find Source of Slow Down ................................................................................. 221
Does Slow Down Come From Analog or Mixed Signal Interactions? ............................................ 222
When Coming From Mixed Signal — How to Analyze? ................................................................ 223
When Coming From Analog — How to Analyze? ......................................................................... 224
Stat File Visualization ...................................................................................................................... 225
Stat File Visualization — General View ......................................................................................... 226
Window Stat Summary .................................................................................................................... 227
Window Stat Mixed — Signal Activity ........................................................................................... 228
Window Stat Analog Kernel ............................................................................................................ 230
Generating Stat File During Simulation Run ................................................................................... 232
Diagnosis Mode ................................................................................................................................ 233
Diagmode – Design Checks ............................................................................................................. 234
Diagmode – Design Checks Report ................................................................................................. 235
Diagmode – Performance Bottleneck Checks .................................................................................. 236
Error Code 2 Causes ......................................................................................................................... 237
Error Code 6 Causes ......................................................................................................................... 238
Lab Exercise – Lab 7 ........................................................................................................................ 239
Module 8: Unified Coverage DataBase ........................................................... 241
Objectives ......................................................................................................................................... 242
UCDB Overview .............................................................................................................................. 243
UCDB Example: Verification Setup ................................................................................................ 244
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UCDB Example: Assertion & Coverage .......................................................................................... 245
UCDB Usage – Capturing Coverage Data ....................................................................................... 246
Example of Assertion Results .......................................................................................................... 247
Example of Report on Assertions ..................................................................................................... 248
Example of Assertion Results .......................................................................................................... 249
Example of Report on Coverage ...................................................................................................... 250
Example of Report on Instance Coverage ........................................................................................ 251
Example of UCDB File .................................................................................................................... 252
Verification Management Windows ................................................................................................ 253
Case of Multiple Run Simulations ................................................................................................... 254
Lab 8 ................................................................................................................................................. 255
Appendix A: Solving an ADMS Problem ....................................................... 257
Objectives ......................................................................................................................................... 258
What Is the MGC Doc System? ....................................................................................................... 259
How to Access the MGC Doc System ............................................................................................. 260
Objectives ......................................................................................................................................... 261
MGC Doc System — InfoHub ......................................................................................................... 262
From the InfoHub, You Can・ ........................................................................................................ 263
From the InfoHub, You Can Also・ ................................................................................................ 264
InfoHub — Support & Training Tab ............................................................................................... 265
InfoHub — System Admin Tab ....................................................................................................... 266
InfoHub — Search Scope ................................................................................................................. 267
HTML— Based Documentation ...................................................................................................... 268
HTML — Search Scoping ................................................................................................................ 271
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HTML — Search Results List .......................................................................................................... 272
HTML — Global Index .................................................................................................................... 273
HTML — My Topics ....................................................................................................................... 274
Objectives ......................................................................................................................................... 275
Mentor Graphics Support ................................................................................................................. 276
Your First Visit: Login or Signup ................................................................................................... 277
Your First Visit: Choose Your Product ........................................................................................... 278
Overview: All About Your Product ................................................................................................. 279
Troubleshoot ..................................................................................................................................... 280
Open a Service Request: Step 1 ....................................................................................................... 281
Open a Service Request: Step 2 ....................................................................................................... 282
Search ............................................................................................................................................... 283
Advanced Search .............................................................................................................................. 284
Appendix B: EZwave Major Features ............................................................ 285
Objectives ......................................................................................................................................... 286
Basic EZwave Features .................................................................................................................... 287
Advanced EZwave Capabilities ....................................................................................................... 288
EZwave — Elements of the Interface .............................................................................................. 289
Joint Waveform Database (JWDB) .................................................................................................. 290
.wdb and .swd Files .......................................................................................................................... 291
Invoking EZwave ............................................................................................................................. 292
EZwave Integration in Artist Link ................................................................................................... 293
How to Start EZwave in Artist Link ................................................................................................ 294
Memory & Disk Space Shortage Detection ..................................................................................... 295
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Out of Memory ................................................................................................................................. 296
Allocate Less Memory ..................................................................................................................... 297
Module Objectives ........................................................................................................................... 298
Toolbar ............................................................................................................................................. 299
Mouse Strokes .................................................................................................................................. 300
The Find Capability for Plotted Waveforms .................................................................................... 301
Find Button ....................................................................................................................................... 302
Waveform List .................................................................................................................................. 303
EZwave — Additional Tools ........................................................................................................... 304
Module Objectives ........................................................................................................................... 305
Pick-Point Tool – New in AMS13.2 Release ................................................................................... 306
Pick-Point Mode ............................................................................................................................... 307
Pick Points Capabilities .................................................................................................................... 308
Pick Points Default Settings ............................................................................................................. 310
Pick Points Specific Behavior .......................................................................................................... 311
Module Objectives ........................................................................................................................... 312
Measurement Tool ............................................................................................................................ 313
Module Objectives ........................................................................................................................... 315
Waveform Calculator ....................................................................................................................... 316
Using the Waveform Calculator ....................................................................................................... 317
Module Objectives ........................................................................................................................... 320
Waveform Compare Tool ................................................................................................................. 321
Waveform Compare Wizard ............................................................................................................ 322
Comparison Method Selection ......................................................................................................... 323
Viewing Waveform Comparison Results ......................................................................................... 324
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Algorithm ......................................................................................................................................... 325
X_min, x_max, y_min, y_max ......................................................................................................... 326
Tolerance Area ................................................................................................................................. 327
Tolerance Tube ................................................................................................................................. 328
Module Objectives ........................................................................................................................... 329
Performing Power Analysis in EZwave ........................................................................................... 330
Power Analysis Window .................................................................................................................. 331
Running the Analysis ....................................................................................................................... 332
Power Table ...................................................................................................................................... 333
Module Objectives ........................................................................................................................... 334
File > Save Menu ............................................................................................................................. 335
Tcl File Example .............................................................................................................................. 336
Getting Help ..................................................................................................................................... 337