Quantum Dot Cellular Automata (QCA) based 4-Bit Shift Register using e cient JK Flip Flop · 2018-03-15 · Quantum Dot Cellular Automata (QCA) based 4-Bit Shift Register using e

Quantum Dot Cellular Automata (QCA)based 4-Bit Shift Register using efficient

JK Flip Flop

Birinderjit Singh Kalyan 1 and Balwinder Singh2

1I K Gujral Punjab Technical University,Jalandhar, Panjab, India.

[email protected] for Development of Advanced Computing

(C-DAC), Mohali, [email protected]

January 25, 2018

Abstract

Abstract: The Quantum-dot Cellular Automata (QCA)is a replacement of the conventional CMOS technology fornano computing devices. This technology aids to achieve ex-tra low power, lower complexity sequential structures withvery high speed. In this paper JK flip flop is redesignedand compared with previous structures. The JK flip flopbased QCA structure which has 78% lesser complexity andcovered 66.6 % less area with half latency than previous de-signs. Further the novel 4 bit shift register was designed aswell as simulated in QCA designer tool using proposed JKflip flop. The total area covered by shift register is 0.20 µm2

with single clock cycle delay. The power estimation is donein QCAPro tool.

Key Words : Quantum Cellular Automata (QCA);Majority gate Logic; Flip Flop (FF); Sequential Logic; clock(Clk) ; QCA Designer.

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International Journal of Pure and Applied MathematicsVolume 118 No. 19 2018, 143-157ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version)url: http://www.ijpam.euSpecial Issue ijpam.eu

143

1 INTRODUCTION

The nano-computing [2] is becoming more popular by nature dueto its high speed and lower complexity for implementation. Thistechnology leads to more complex structures which were first of allproposed by Lent et al [1]. The QCA cell is the building architec-ture of any circuit from which the basic gates and logic devices aredesigned. The research involves first at the physical level and thento the simulation tool which is QCA Designer tool introduced andvarious test were reported [3-5]. The QCA technology has manyadvantages as its high operational speed, low-power consumptionand lower complexity [6- 9]. In this paper the JK flip flop usingQCA cells are redesigned and effectively used to realize more com-plex sequential circuits like shift register. In the basic of QCA, theschematic figure 1(a) shows the QCA nanostructure with four quan-tum dots which have placed at the square boundary corners. Thisquantum cell comprises of twin electrons those can tunnel throughthese four quantum interstitial positions at the corner of the squarecell. Tunneling doesn’t happen between the two adjoining corners.The Quantum dots (denoted as i ) in the cell where i=1, i=2, i=3and i= 4 represent the different interstitial positions of dots. Thepolarization P in a cell can be explained by equation 1, where ρ isthe polarization positions in QCA cell.

P = (ρ1+ρ3)−(ρ2+ρ4)(ρ1+ρ2+ρ3+ρ4)

(1)

The polarization comprises the different charge configurationthat will define the various logics which is distributed among fourdots. Likewise, the polarization is -1 when i=4 and i=2 are at higherstate and polarization become +1 when i=3 and i=1 at higher state.Binary information is also represented in QCA by figure 1(a) in theforms of logics.

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International Journal of Pure and Applied Mathematics Special Issue

144

(a) (b)

Figure 1: Figure 1 (a) QCA cells (b) QCA wire

Due to coulombic repulsion [1], the cell occupies the antipo-dal sites under the control clock scheme in which they can tunnelthrough to form the logic. The two polarizations of -1 and +1 rep-resent the binary ”0” and ”1” respectively. The polarized chargecan be transferred by the Coulombic repulsion within the squarecells along with the one-dimensional cell array. There is nonlin-ear cell-to-cell interaction which means even when a input cell isslightly polarized, it can induced its polarization to the output cellto its extent which happens only when these cells are placed nearone other and this was presented by P. Douglas Tougaw et. al [10].The QCA wire [34-37] is a group of cells placed together to form achain, as shown in figure 1(b). Neighboring cells along with otherstransmit binary information.

2 QCA MAJORITY IMPLEMENTA-

TION

Binary basic elements also evolve with the development of logicaldevices such as parametrons and esaki diodes in 1960, as describedby Yuhui Lu and Craig S. Lent [12]. The distributive law andalgebraic manipulations in digital circuits with the use of majoritylogics[11-16]. The NOT gate is represented by rearranging the QCAcells as shown in figure 2(a). Inverter input is having ”logic 0” andat the output we get ”logic 1” or vice-versa. The majority gateshown in Figure 2 (b) has three inputs. A, B, and C act as inputfor three majority gate inputs, and the output is given by M (A,

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B, C) = AB + BC + AC, expressing various logic gates by simplysetting the inputs to zero or one.

(a)

(b)

Figure 2 (a) Inverter (b) Three input Majority gate

In figure 2(b) there is three input majority gate in which C hasset at logic 0 and input A & B have set at logic 1, as a result ANDgate is implemented by using majority gate functions, it will act asM(A, B, 0) = AB. On the other hand when we keep C input atlogic 1, the majority gate functions become M(A,B,1) = (A+ B)which act as an OR gate. The complex QCA circuit is designedusing the five input majority gate which was described by KeivanNavia et. al [17] as shown in figure 3.

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(a) (b)

Figure 3 Majority Gate having 5 Inputs

The majority structure uses the 10 QCA cells for the imple-mentation where X1, X2, X3, X4, X5 are the input logics of the five-input majority gate structure. The logic expression is representedby equation 2.

M(X1, X2, X3, X4, X5) = X1X2X3 + X1X2X4 + X1X2X5 +X1X3X4 + X1X3X5 + X1X4X5 + X2X3X4 + X2X3X5 +X2X4X5 + X3X4X5 (2)

The clock signals in various digital circuits are main elementswhich synchronized the digital circuits and control the data flow. Inthe synchronization sequence, there are four different consecutivephases which are divided into four clock zones and the 90 degreeout of phase, and four synchronization phases: ”Switch”, ”Hold”,”Release” and ”Relax” [7-10]. As described in [4], the noise ismuch more concern in three input majority gate structure, therebydifferent clock zone are positioned at the input cells, middle QCAcells and output of the majority gate.

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Figure 4 Clocking Mechanism in QCA

3 QCA BASED FLIP FLOP DESIGN

The flip flop circuit is the major component for the design of anymemory device. The total number of QCA cells can be minimizedby using majority logic in various designs of flip flops[19]. These flipflops are designed with optimum area in QCA designer and clockscycles are utilized hence quantum area of these designs are studied.Here JK flip flop is discussed and simulated in QCA designer tooland power dissipation is estimated in QCA Pro tool.

3.1 QCA BASED JK FLIP FLOP DESIGN

The behavior of the JK flip flop is described in the characteristicstable 1. The schematic of clocked JK flip-flop is shown in figure 5.The majority gate based flip flop is designed by using 2 invertersand four majority gates as shown in figure 6.

Figure 5 Logic Design of JK Flip flop

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TABLE 1: CHARACTERISTIC TABLE OF JK FLIP FLOP

Q(output) = JQ′ +K ′Q (3)

The majority gate M1 is fed with complement of input K andQ which is fedback from output of the circuit. The Majority gateM2 act as OR gate to produced the output JQ’+ K’Q. The outputof M1 and M3 are combined with the clock input by majority gateM2. The desired characteristics are produced in equation (3).

Figure 6 Majority gate based JKFlip Flop

Figure 7 QCA Cell Layout of JKFlip flop

The layout of JK Flip flop is implemented in QCA Designershown in figure 7. The QCA implementation requires 39 cells todesign, with an area of 0.04 µm2 having 2 clock zones. The latencyof the circuit is 0.5. The JK design utilizes 78% less area then

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previous design [34].

3.2 SIMULATION RESULT

The simulation result of JK flip flop as shown in figure 8, the outputreferred as Q having latency 0.5. The output is depicting the outputas per the characteristic table 1. There is 900 phase delay betweenthe clocking zones. The JK flip flop having two clock zones so itsvulnerability to noise is lesser then single QCA cell clock cycle.

Figure 8 Simulation result of QCA based JK Flip Flop

4 PERFORMANCE EVALUATION

The performance analyses of novel designed circuits are comparedon the basis of their complexity, area, latency, and latency cost aregiven table 2. The quantum cost has been calculated on the basisof latency and area. It has been found that JK flip flop havingcomplexity 39 cells and area utilization is 0.04 µm2 than previousstructure. The sequential circuits are designed using novel JK flipflop having 78% lesser complexity then previous structure. Further,in this paper 4 bit shift register is designed using QCA designer.

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TABLE 2 PERFORMANCE ANALYSES OF FLIP FLOPS

5 QCA SHIFT REGISTER USING JK-

FF

The layout of JK flip flop based shift register is shown in figure 9.The shift resister is designed using proposed JK flip flop which washaving 39 cells and the total area of 0.04 µm2. The shift registerserial in serial out is having the 4 JK flip flops, total QCA cellutilized are 238 cells with the area spacing of 0.20 µm2. The inputis feed through input D and clock is provided as shown in table 3as the design vectors of shift-register and the simulation waveformin figure 10 is thus formed using these vectors using Euler Methodin Coherence vectors Simulation Engine[27].

TABLE 3 DESIGN VECTOR

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The 12800 are samples utilized with convergence tolerance of0.001000, effective radius of cell is 65 nm and maximum iterationsper sample is 100 in bistable simulations in the simulation engineof QCA designer tool[26].

Figure 9 Layout of the QCA based shift register

Figure 10 Simulation waveform of Serial-in Serial-out Shift Register

The Hamiltonian matrix is used to estimate the dissipation ofenergy and power in the QCA Cells array. Therefore, the energydissipation of the QCA cell is one clock cycle of TCC = [-T, T], asdescribed in equation 4.

Ediss = h̄2

∫ +T

−T→Γ.d

→λdtdt = h̄

2

∫ +T

−T [[→Γ.→λ]−T −

∫ +T

−T→λ.d

→Γdtdt] (4)

The power dissipation model is given shown in equation 5. Thetable 4 shows the energy dissipation results.

Pdiss = Ediss

Tcc< h̄

2Tcc

→Γ+× [−

→Γ+

|Γ+|tanh( h̄|→Γ+|kbT

) =→Γ−

|→Γ−|tanh( h̄|

→Γ−|kbT

)] (5)

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TABLE 4 ENERGY DISSIPATION RESULTS

6 CONCLUSION

In this paper, firstly an effective QCA based JK Flip Flop was re-design. The proposed structure consumes low energy and has alow complexity in comparison with the best reported design. TheJK Flip Flop was designed and functionality, complexity is verifiedusing QCA designer tool whereas the QCA pro was used for esti-mating energy dissipation. The results shows that the proposed JKflip flop utilizes 78% lesser complexity as compared to best reportedstructures. In the next step, by employing proposed JK flip flop,the 4 bit serial-in serial-out shift register has been constructed. Theproposed 4-bit shift register using the JK flip-flop showed an im-provement of 65% in terms of complexity and a 45% improvementin the occupation period of the region, respectively.

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Quantum Dot Cellular Automata (QCA) based 4-Bit Shift Register using e cient JK Flip Flop · 2018-03-15 · Quantum Dot Cellular Automata (QCA) based 4-Bit Shift Register using e

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