Quantum Devices and Integrated Circuits Based on Quantum ...web.cecs.pdx.edu/~mperkows/CLASS_FUTURE/Single... · University Hokkaido RC G ≈ G 0 ≡ 2 e 2 h J.E.Mooij, 1993 SSDM

UniversityHokkaido

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Quantum Devices and Integrated Circuits Based on Quantum Confinement

in III-V Nanowire Networks Controlled by Nano-Schottky Gates

ECS 2001 Joint Intenational Meeting, San Francisco Sept. 2-7, 2001Sixth International Symposium on Quantum Confinement

Hideki Hasegawa

Research Center for Integrated Quantum Electronics (RCIQE) andGraduate School of Electronics and Information Engineering

Hokkaido University, Japan

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Outline

1. Introduction

2. Hexagonal BDD Quantum Circuits

3. GaAs-Based Quantum BDD Node Devices and Circuits

4. Toward Room Temperature Operation and High Density Integration

5. Conclusion

• Novel nanometer-scale Schottky gates• GaAs-based quantum BDD node devices• Integration of BDD node devices on hexagonal nanowire networks

• Formation of InP-based high density hexagonal nanowire networks• Surface related key issue

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CollaboratorsRCIQE staff

Dr. S. Kasai, Dr. C. Jiang and Dr. T. SatoStudents

T. Muranaka, A. Ito and M. Yumoto

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G ≈ G0 ≡ 2e2

h

J.E.Mooij, 1993 SSDM Ext. Abs. 339

106

104

102

1

10-2

10-14 10-12 10-10 10-8 10-6 10-4 10-2

10-16Fτ

[ps]

P[W]

Single Electronics

Quantum Limit

thermal energy1K

300K 105K

10-15F

10-18F

present-daysemiconductor

devices

10-17F

τ = CG

Speed, Delay-Power Product of Quantum Devices

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Semiconductor Nanoelectronics based on Quantum Device and Circuit

Research on Semiconductor Nanostructure

Scale-down limit of Si CMOS LSIs

Growing demands on Information Technology (IT)

Nanotechnology in wide area~ chemistry, biology, etc.

• delay-power product near quantum limit • small-size and high-density • nano-sensing, nano-control

But, How to ? So far no realistic approach.

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High Density Integration ?

First Monolithic Integrated Circuit in the World (Noyce, 1959)

300µm rule

IBM PowerPC

64-bit0.18µm rule700MHz1.4mm x 1.4mmSOI technology

Current Microprocessor (2001)

Discrete quantum devices How to make QLSIs ?

Semi-classical devices

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5 µm

QWRTr(Active Load)

3-gateWPGSET

input output

QWRTr-load SET inverter

W = 440 nmSET: LG = 50 nm, df = 200 nmQWRTr: LG = 300 nm

VDD

VG(QWRTr)

Vin

Vout

WPG QWRTr (active load)

WPG SET (driver Tr.)

(S. Kasai and H. Hasegawa presented at DRC 2000)

0

5

10

15

20

25

-550 -500 -450 -400 -350 -300 -250

T = 1.6 K

Gain = 1.3 VDD = 40 mVVBG = -1.0 V

VG(QWRTr) = 0 mV

Vin (mV)

small delay•power product but low gain

voltage mismatch poor Vth controlpoor drivabilitylow temperature

Example of Quantum Logic Circuits

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Novel Approach for III-V QLSI

1. Digital Processing ArchitectureBinary Decision Diagram (BDD) logic architecture

5. DeviceBDD node devices using gate-controlquantum wire (QWR) and quantum dot (QD)

2. NanostuctureHexagonal nanowire networks byGaAs etched nanowires andInGaAs nanowires by Selective MBE

3. Nanoscale Gate TechnologySchottky in-plane gate (IPG) and wrap gate (WPG)

4. Surface and Interface ControlNano-Schottky interfaceInterface control layer (ICL)-based passivation

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Digital Logic Architecture

Digital processing (operations on digital functions)

Implementation of digital functionsRepresentation

Boolean Equation Truth Table Binary Decision Diagram (BDD)

etc.

Implementation

Binary Logic Gate Look-Up Tableusing Memory

BDD Device

Transistor Switch ROM device

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BDD node device

Hexagonal BDD QLSI Approach

Example: Exclusive OR Logic Function

messenger

Xi

entry branch

0 1

1-branch0-branch

input

QWRswitch

quantumdot

tunnelbarrier

x1

x2 x2

f

0

0 1

0 1 0 1

BDD Boolean Logic Gate

x1

x2f

5 gates, 16 Trs3 devices

BDD logic architecture

terminal

x1x1

x1x3 x1xi

x1xn

0 1

input

r1

0 1

0 1 0 1

0 1

rootx1x2

r2

0 1

node

Hexagonalnetwork

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Ultra-low delay-power product near the quantum limit

•no precise voltage matching•no large voltage gain•no large current drivability•no large fan-in and fan-out

No direct input-output connection is requiredBDD is suited to quantum devices

Conventional Logic Gate Architecture

Hexagonal quantum BDD

node

r1 r2

x1 x2

x4x3

xn

xi

1 0

root

terminal

input

Features of Our Approach

The circuit itself works at room temperatureat sacrifice of delay-power product

IPG/WPG QWRTr-based BDD devices act as classical path switching devices even under non-quantum conditions.

single electronregime

few electronregime

many electronclassical regime

High density integration•hexagonal closely packed nanowire network•free from contact problem•reduced device count

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Basic Schottky Gate Structure

Schottky In-Plane Gate (IPG) and Schottky Wrap Gate (WPG) control of AlGaAs/GaAs etched nanowires

Schottky In-plane Gate (IPG)

AlGaAs

GaAs

GaAs nanowire

electrons

Schottky Wrap Gate (WPG)

·stronger confinement size ~ smaller high temperature operation

·lateral structure suitable for planar integration

AlGaAs/GaAs nanowire

depletion layer

quantum wire

2-gate WPG single electron transistor(SET)

tunnel barrier controlWPGs

quantum dotWPG quantum wire transistor

(QWRTr)

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Wgeo

Source

IPG

Drain 1µmB (T)

0

3

1

2

4 T = 4.2K

-0.4V

VG=0V

-0.6V

2 4 60 1 3 5 7 8

SdH oscillation

0

600

200

400

800

-1.5 -0.5-2 -1 0

IPG QWR

VG (V)

Controlof Weff IPG QWRTr

GaAsexit branch

SchottkyWPG

LG

W500 nm

WPG QWRTr

0

5

10

15

20

B (T)

VG=0V-0.24V

-0.42V

0 1 2 3 4 5 6

-0.36V-0.48V

T=1.6 K

-0.6 -0.2-0.4 00

300

100

200

400

500WPG QWR

VG (V)

Gate Control Characteristics of IPG/WPG Structures

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I-V Characteristics of IPG/WPG QWRTrsAlGaAs/GaAs etched nanowire

VDS (V)

0

2

4

6

8

10

0 0.1 0.2 0.3 0.4 0.5

VG = 0 V

-0.05 V

-0.1 V

-0.15 V-0.2 V

T=1.7K

VG (mV)

0

1

2

3

4

-600 -550 -500 -450

W = 750 nmLG = 300 nmT = 1.7 K

-800 -600 -400 -2000

1

2

3

VG (mV)

W = 530 nmLG = 600 nmT = 3 K

0

5

10

15

20

25

30

0 0.5 1 1.5 2

VG =0V

-0.2V

-0.4V

-0.6V

-0.8V

VDS (V)

T = 300 K

IPG QWRTr WPG QWRTr

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Single Electron Transport in 2-WPG SET

I = |T(E)|2 [f (E) – f (E+qVDS)] dEe2

h

Lateral resonant tunnling of single electron

0

20

40

60

80

0 5 10 15 20 25 30T (K)

Breit-Wigner formula

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0 5 10 15 20 25 30T (K)

e2ΓlΓr4kTΓl+Γr

1

cosh2 E-EF 2kT

~~

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

-1.3 -1.25 -1.2 -1.15 -1.1VG (V)

T = 30 K

20 K

15 K

7.5 K

4.2 K

2.5 K

1.5 K

df = 160 nm, W = 820 nmExperiment

-1.3 -1.25 -1.2 -1.15 -1.1VG (V)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4T = 30 K

20 K

15 K

7.5 K

4.2 K

2.5 K

1.5 K

Theory

GaAs SETWPG

GaAs nanowire

AlGaAs GaAs

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QWR-based BDD node device

GaAs nanowire WPG

entry

IPG

1-branch0-branch

QWR

GaAs nanowire

quantum dot

tunnel barrier

WPG

WPG

SET

Single electron BDD node device

Various Types of BDD Node Devices by IPG/WPG Control of III-V Nanowires

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WPG BDD Quantum Node Device

500 nm

0-branch 1-branch

GaAs nanowire

WPGxixi

entry

QWRTr

xixi

0-branch 1-branch

entry

WPG QWR-based BDD device

WPG single electron BDD devices

branch switch type

500 nm

0-branch 1-branch

GaAs nanowire

WPG

xixi

entry

SET

xixi

tunnel barrier

quantum dot

branch switch type

xixi

quantum dot

tunnel barrier

entry

10

WPG

GaAs nanowire

1 µm

xixi

node switch type

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0

1

2

-1

0

1

0 1 2 3 4Time (s)

0-branch 1-branch

xx

VDD = 200 mV

T = 300 K

Switching Characteristics

0

1

2

3

4

0 100 200 300 400 500VG (mV)

1-branchVG = 0 V

-0.2

-0.4

-0.6

-0.8-1.0

T = 300 KBranch I-V Switching characteristics

QWR branch- switch BDD node device

QWRTr

xixi

0-branch 1-branch

entry

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entry

0-branch

WPG

GaAs nanowire

1 µm

xixi

1-branch

WPG BDD Single Electron Node Device

Conductance oscillation due to single electron transportClear path switching

0

0.02

0.04

0.06

-2.0 -1.8 -1.6 -1.4 -1.2VGxi (V)

T = 1.5 KVGent = -3.0 VVGxi = 0.4 V

0-branch: open

Conductance oscillation from single channel

Switching characteristics

0

1

2

3

-1.9 -1.8 -1.7

0-branch

1-branch

VGent = -2.4 VVGxi = +0.4 V

T = 1.5 K

VGxi (V)

QD-based node switch device

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Quantum BDD Implementation

Quantum BDD large scale integration

x1 x1

x2x2

x3

x4x4

0 1 0 1

0 10 1

0 1

0 10 1

hexagonal nanowire network + WPG

branchcut-off(etching, FIB)

x1

x2

x3

x4

x1

x2

x3

x4

wiring

WPG

one level metallization

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WPG BDD OR Logic Function Block

1000 nm

x1x1

x2

1- terminal

root

WPG

GaAs nanowire

x1

x2

10

1

1

root

1-terminal

node device

f

hexagonallayout

WPG single electron BDD OR circuit

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Operation of WPG BDD OR Logic

Input/Output waveform

VDD = 1 mV

clock: 2 Hz x2: 250 mV x1: 100 mV

pulse height

entry gate: 0 mV

0

0.1

0.2

0.3

0 2 4 6 8

x1

x2

output

T = 1.6 K

10Time (s)

VDD = 0.2 mV

clock: 0.1 Hz x2: 1000 mV

pulse height x1: 1200 mV entry gate: +1000 mV

00.10.20.30.40.50.60.7

0 50 100 150 200

x1

x2output

Time (s)

T = 120 K

x1

x2

OR

1

0 1

0 1

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Time (s)

Half adder (exclusive OR)

pulse h offset+x1: 0.02 V -0.4 V- x1: 0.44 -1.2+x2: 1.7 1.9- x2: 0.1 1.6VDD: 250 mVVDD = 0.2 mV

x2: 1000 mV

pulse height x1: 1200 mV

entry gate: +1000 mV

0

0.2

0.4

0.6

0 50 100 150 200

x1

x2output

Time (s)

120 K

0 5 10 15 20 25 30 35

20 nA

output

RTx1

x2

OR

x1

x2

OR

1

0 1

0 1

x1

x2 x2

0 1

01 0

ExOR

1

1

0 0 00 1 11 0 11 1 0

x1 x2 x1+ x2

0 0 00 1 11 0 11 1 1

x1 x2 x1+x2

WPG BDD Fundamental Logic Family

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Fabricated 2-bit adder circuit

1-terminal

c1 s1 s0

QWRTrnode device

WPG

GaAsnanowire

a1

b1

a0

b0

5 µm

Circuit Design and Fabrication Technology Towards BDD Quantum Integrated Circuit

Example: BDD 2-bit adder

augend: a1, a0addend: b1, b0

a1 a1

b1b1b1b1b1

a01 0

b01 0

a1 1 0 0 11 0

a0a0

b0

0 10 10 11 01 0

1 00 1

1 0 1 0b0

c1 s1 s0

1

rootnode

terminal-1sum: s1, s0carry:c1

circuit diagram WPG/nanowire layout

augend: a1, a0addend: b1, b0sum: s1, s0carry:c1

1 0 0 1

00 11

1 0

1 0 1

1 00 1

10

1

1

a1 a1

b1b1b1

a1

b1b1

a0a0

b0b0

a0

b0

c1 s1 s0

1

root

terminalnanowire

WPG

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Hexagonal BDD 2 bit Adder

5 µm

C S1S0

terminal 1

a1b1

a0

b0 a1b1

b0

hexagonalnanowirenetwork

nodedevice

WPG

a0

T = 300 KVDD = 250 mV

time (s)0

200

400

600

800

0 10 20 30 40 50 60 70 80

a1a0b1b0

input

carry

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InGaAs Ridge Nanowires for Room Temperature Operation

InGaAs ridge quantum wire InAlAs

InGaAs

patterned InP sub. 3µm

AlGaAs/GaAs etched nanowires: possible minimum width = 70-100 nm

Room temperature operation requires sub-10 nm width

Growth of InAlAs/InGaAs/InAlAs

MBE growthof InGaAs

Pre-growth etching & O desorptionby atomic Hydrogen

InGaAs ridge QWRInGaAs ridge

(111)A

InP patterned sub.

4µm

1µm

Formation Process

T=20K

1.0 1.41.20.8

QWR

23meV

Energy (eV)

PL

Effective width, Weff (nm)

1.4

1.2

1.0

0.8theory

0 10 20 30 40 50

narrowest QWR by H* cleaning

Wire width of 6 nm has been achieved

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SEM image of hexagonal InGaAs nanowire network

3 µm

43

21

µm

12

34

0.4

µm0.8

AFM image

Hexagonal InGaAs Ridge Nanowire Network

( Ito et al. IPRM01, ICFSI-8)

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Potential Controllability of Nanometer-Sized Schottky Gates

φMS = 1.0 eVLg = 90nm

nano-Schottky gate

1. Strong pinning (0.88 eV)2. Unpinning

Semiconductor surface

Control of an environmental Fermi level pinning is important

1. With strong pinned surface 2. With unpinned surface

0 500 1000(nm)

0.8 ~ -2.0 V step 0.4 V

gate

500 1000(nm)

0.8 ~ -2.0 V step 0.4 V

gate0

500

n-GaAs

0

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Conclusion

A new, simple and realistic approach for quantum LSIs is presented and discussed.

1)

•Architecture: BDD logic architecture

WPG QWR and single electron BDD node devices using GaAs etched nanowires have been fabricated and BDD switching was realized.

Hexagonal BDD ICs using GaAs etched nanowires have been fabricated. Logic operation has been confirmed.

Hexagonal InGaAs nanowire network by H* assisted selective MBE combined with IPG/WPG gate technology gives good prospect for high density BDD QLSIs that are operating at delay-power products near the quantum limit at RT.

2)

3)

4)

•Hardware: Schottky WPG control of hexagonal III-V nanowire networks.

Control of surface/interface remains to be a key issue.5)