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Restricted Distribution. Not to be distributed to non-employees of QUALCOMM or its subsidiaries without the express approval of QUALCOMM’s Configuration Management.
Not to be used, copied, reproduced in whole or in part, nor its contents revealed in any manner to others without the express written permission of QUALCOMM.
QUALCOMM is a registered trademark and registered service mark of QUALCOMM Incorporated. Other product and brand names may be trademarks or registered trademarks of their respective owners. CDMA2000 is a registered certification mark of the Telecommunications Industry Association, used under license. ARM is a registered trademark of ARM Limited. QDSP is a registered trademark of QUALCOMM Incorporated in the United States and other countries.
Export of this technology may be controlled by the United States Government. Diversion contrary to U.S. law prohibited.
30 fps WVGA15 fps QVGAQcamcorder™(offline video encoding)
MSM7200AMSM6280Features liu.h
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System Architecture
Page 880-VE263-25 Rev. AMarch 2007
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Sample 1 Limitations
• Sample 1 (March 2007)– TBD
Refer to the MSM7200A Mobile Station Modem™ Revision Guide (80-VE263-4) for more information.
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MSM7200A Device Design Consideration
Page 1080-VE263-25 Rev. AMarch 2007
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MSM7200A Power Supply
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Voltage Requirements
VV
1.952.7
1.82.6
1.652.5
Supply voltage for USB (HS) interfaceVDD_USBH1
V1.91.81.7Supply voltage for stacked memory interfaceVDD_SMI
V32.92.8Supply voltage for Qfuse programmingVDD_QFUSE_PROG
V1.951.81.65Supply voltage for MDDI interfaceVDD_MDDI
VV
1.952.7
1.82.6
1.652.5
Supply voltage P4 for camera interfaceVDD_P41
V2.692.62.5Supply voltage P3 for peripheral interfacesVDD_P3
VV
1.952.7
1.82.6
1.652.5
Supply voltage P2 for EBI2 and peripheralinterfaces
VDD_P21
V1.91.81.7Supply voltage P1 for EBI1 and peripheralinterfaces
VDD_P1
V2.72.62.5Supply voltage for internal analog coreVDD_A
V1.41.2TBDSupply voltage for MSM digital core #2 (ARM11)VDD_C2
V1.41.2TBDSupply voltage for MSM digital core #1 (everything but ARM11)
VDD_C1
UnitsMax1TypMin1DescriptionSymbol
Notes:1) This voltage must match the external device voltage. It is a dual-voltage pin, and can be either 1.8 VDC nominal or 2.6 VDC nominal.2) Trace length for VDD_C1 and VDD_C2 should be as short and thick as possible to minimize IR drop between the PM7540™ IC and the
MSM™ device.
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MSM7200A/PM7540 Power Supply Connections
Note:Connect VSS_THERMAL to ground for better thermal flow and to reduce RFI.
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Power-up/down Sequence
• Power-up sequence (as controlled by the PM7540™ device):
1) VDD_C1: modem subsystem
2) VDD_C2*: application processor
3) VDD_E: pad group EBI1/SMI (EBI2**/MDDI and camera)
4) VDD_P**: pad group GPIO (2.6 V domain/EBI2)
5) VDD_A: pad group analog
• Power-down sequence (as controlled by the PM7540 device):1) VDD_A: analog
2) VDD_P**: pad group GPIO (2.6 V domain/EBI2)
3) VDD_E: pad group EBI1/SMI (EBI2**/MDDI and camera)
4) VDD_C2*: application processor
5) VDD_C1: modem subsystem
* Application processor (VDD_C2) power supply is controlled by the modem master.
** EBI2 can be powered by 1.8 V or 2.6 V power rail.
Page 1480-VE263-25 Rev. AMarch 2007
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GPIO Power-up States
• Specific power-up sequence is required for the MSM7200A IC.
• If the power-up sequence is not achieved, GPIO pads may come up in undefined states.
• QUALCOMM power management ICs such as the PM7540 IC ensure the proper supply sequence and states.
• The initial GPIO state is maintained until programmed by software.
VD D_C
VD D_P
R ESIN_N
GPIO_ PAD
Treset1
VDD _C Ram p
Undefined Default State SW Programmed
GPIO pin is set to “ input” and in its default “pull state” , w ith proper power sequence requirem ents fulfilled .
SW program m ed GPIOPin State
RESIN_ N deasserted
SW Initialization
VD D_C m ust reach 90 % before VD D_P ram p to guarantee GPIO pin is powered up in a know n state
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Power-up Sequencing
• The use of the QUALCOMM PM7540 power management IC ensures the correct power-up sequence.
• When using the MSM7200A IC with the PM7540 IC, it is required that customers configure GPIO[25] as PS_HOLD signal during boot-up.
• After the voltage rails are brought up, PON_RST_N is asserted byPM7540 IC, and then the MSM7200A IC asserts PS_HOLD signal.
– This is done early in the boot process (PBL) to ensure that PMIC does not turn the MSM device off.
Page 1680-VE263-25 Rev. AMarch 2007
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KPDPWR _N (in)
BAT_FET_N (out)
VREG outputs
PON_RST_N (out )
PS_HOLD (in)
Operating state
treg1
tregtreset1
tpshold
Power-on sequence ON Power-off sequence
treset0toff
OFFOFF
must stay low at least until PS _HOLD is driven high by MSM device
tsettle
1 = MSMC12 = MSMC23 = MSME4 = MSME2
1 2 3 4 55 = MSMP6 = MSMA & AUX27 = TCXO all
others
5676 7 4
PS_HOLD Assertion
PS_HOLD (GPIO[25]) is asserted in the PBL
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Clock Source Generation
AB4
MSM7200A
U5
AG8
PLL_TEST_SE
TCXO
SLEEP_CLK
VCTCXO
VREG_ TCXO
XTAL_INXTAL_OUT
C C
xtal
SLEEP_ CLK
TCXO_IN TCXO_OUT
PM7540
100 2 k R11TRK_LO_ADJ
TCXO_EN
0. 033 uF
AE1TCXO_EN
0. 01 uF
From an external clock source
TCXO controller and buffer ckts
Crystal oscillator ckts SLEEP clock ckts
100pF
51
Page 1880-VE263-25 Rev. AMarch 2007
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Clock
• MSM7200A system uses three clocks:– 19.2 MHz for system clock
– 32.768 kHz» Sleep clock» Refer to PM7540 Power Management IC Device Specification (80-VD691-1) for
complete specifications.
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Secure Boot
• Secure boot ensures that MSM7200A IC boots from code that cannot be altered or hacked.
• Enables phone manufacturer and QUALCOMM to ensure that their own code is running unchanged on the device.
• Hardware requirements for secure boot:– Boot ROM (primary boot loader)
• Secure boot capability is provided through an on-chip ROM. MSM7200A IC has built-in 64 kb of on-chip BOOT ROM. This ROM contains the primary boot loader (PBL).
• This boot ROM is programmed in silicon – it CANNOT be changed for different configuration or for different uses by customers.
• The PBL is mapped to address 0xFFFF0000.– Internal RAM (IRAM)
• IRAM is a 4 kB memory space that is used to load the basic configuration data.– Secondary boot loader (SBL)
• The SBL is an external flash memory device.• SBL must be implemented as a NAND device on EBI2.• Since SBL is external to the MSM7200A device, SBL contents MUST be
authenticated by PBL before execution.
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Configuring MSM7200A Device in Secure Boot
• Two ways to ensure that MSM7200A IC is booting in secure boot:– External mode pin– On-chip Qfuses
• External mode pin (BOOT_SCUR pin)– GPIO[95] is used for this purpose.– If this pin is enabled (high), it forces the secondary boot loader or any
subsequent code to be authenticated for security.– This pin setting is valid only if security-enabled Qfuse is NOT blown.
• On-chip Qfuse– One-time programmable fuse– FORCE_TRUSTED_BOOT Qfuse is used for MSM7200A secure boot
configuration.– If this Qfuse is blown, forces secondary boot loader and any subsequent code to
be authenticated for security.– When the FORCE_TRUSTED_BOOT Qfuse is blown, the BOOT_SCUR pin setting
is meaningless, and BOOT_SCUR pin is available for use as GPIO[95].– It needs to be blown by customer if secure boot is deemed mandatory.– Qfuse is blown through software or JTAG.
• VDD_QFUSE_PROG must be connected to GND if Qfuse programming is not being performed.
• Refer to Application Note: MSM7500™/MSM7200 Qfuses and Security(80-V9038-15) for more information.
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Secure Boot Process Flow
Secondary boot loader starts executing here
Configure all controllers, peripherals etc
Copy warm boot configuration data intoMemory within “always-on” domain
Copy AMSS code from flash into RAM
SecurityEnabled ?
Authenticate AMSS code for security
Transfer control toThe AMSS code
Transfer control toSecurity fail handler
YES
NOFailed
Passed
Page 2280-VE263-25 Rev. AMarch 2007
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Boot Operation
• Cold boot– Happens at initial power-up.– Follows the PBL and SBL boot process flow from previous slide.
• Warm boot– Happens when a device comes out of its shutdown (power-saving)
mode.– PBL executes and determines system is powering up from
power-saving mode and executes warm-boot loader.– System is reconfigured almost the same way as cold boot, but
configuration comes from a small memory on the always-on domain.– Once memory controllers are configured, data in the RAM (SMI) can be
accessed. SBL does not need to be reloaded from the flash.
• The MSM7200A IC provides GPIO pins that are software programmable.
• GPIO pads are assigned functions using AMSS software.
• Many pads can be assigned more than one function, depending on the application.
• GPIO pins can be configured as follows:– B: Bidirectional – these can be configured as input, output, or bidirectional– K: Keeper – indicates a weak keeper device (cannot drive external buses)– H: Digital input that allows input voltage up to 3.0 V– W: Input pad that provides a wake-up interrupt during MPM mode– Programmable pull resistor
• Refer to MSM7200A Mobile Station Modem Device Specification(80-VE263-1) for more information regarding GPIO pins and their functions.
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GPIO Pad Structure
• Output configurations– Normal GPIO output signal– Alternate GPIO output signal– Special GPIO signal
• Input configuration– Buffer– Interrupt: the input signal’s (interrupt
source) level or edge, with selectable polarity, is used to generate an interrupt.
• Pull configurations– Keeper– Pull up– Pull down
• Programmable drive strengths– Most of GPIO pin’s output drive strength is
programmable from 2 to 16 mA, in 2 mA increments.
– High voltage (3 V) GPIO pin’s output drive strength is programmable from 2 to 8 mA, in 2 mA increments.
– SDCC CLK GPIO pin’s output drive strength is non-linear 4 to 7 mA. Refer to the MSM7200A Mobile Station Modem Device Specification (80-VE263-1) for more information.
R
D
Q
KEEP
GPIO_PULL = 10
PU
GPIO_PULL = 11
PDGPIO_PULL = 01
Pull up circuit
VDD
Pull down circuit
GND
GPIO_CFG(5:2)
RESOUT
GPIO_CFG_REG
(write)
SPECIAL_CONDITION
SPECIAL_CONDITION_DATA
SPECIAL_CONDITION_OE
GPIO_OE(i)
ALT_FUNCTION_OE
GPIO_OUT(i)
ALT_FUNCTION
Highlighted multiplexers and signals apply to special GPIOs only - GPIO[106:98]
INTERRUPT CIRCUITS
GPIO_INT_POLARITY(i)
GPIO_INT_CTL(i)
INT_CLR(i)
GPIO_INT_EN(i)
GPIO_GROUP_IRQ
GPIO_IN(i)
GPIO PAD
GPIO_INT_STATUS_MASK(i)
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Modem Power Manager
• Modem power manager (MPM) is a feature of the MSM7200A IC that will reduce the leakage current in phone designs during sleep mode.
• When the MPM feature is used, only a select number of GPIO pins can turn on the MSM device from sleep.
– 26 GPIO pins are capable of wake-up interrupt.– Other GPIO pins cannot be used as a wakeup-capable interrupt (only applicable if the
MPM feature is enabled).
• During power-saving mode, all pins in the MSM device will be held by the keeper.
• Keepers provide < 30 µA per pad of drive strength capability on all MSM pads.
• It is recommended to avoid using external pulls on the MSM device, which pull to the state opposite to that nominally found on the pin.
– Excessive DC current will be drawn in such a condition.
GPIO pins that can detect interrupt during modem power manager (MPM) shutdown:
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Top-level Mode Multiplexer
• The top-level mode multiplexer (TLMM) provides a convenient mechanism for sharing multiple internal functions onto the same set of GPIO pads.
• The mode assignment for each set of GPIOs is specified using a combination of input pin settings and software-programmed register settings.
• Using TLMM allows higher-level instructions, resulting in faster and easier GPIO assignments.
– Without TLMM, each GPIO pad would require individual programming.
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TLMM Modes
• TLMM provides three modes of software-controlled MUXing (or DEMUXing) of the MSM7200A I/Os.
– Standard: Most GPIOs fall into this category (106, 105, 97:43, and 15:0). These GPIOs are configured as inputs on power-up, and then set by software to the desired functionality.
– EBI2: Only GPIO[103:98] falls into this category; these GPIO pads are used for EBI2 functions. On power-up, these GPIOs assume default EBI2 functions.
– Special condition: These are primarily GPIOs used in ETM modes (GPIO[42:16]).
Page 3080-VE263-25 Rev. AMarch 2007
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TLMM Architecture
Special condition MUXing (ETM & test functions)
EBI2 GPIO MUX
STD GPIO MUX
GPIO MUXing
GPIO DEMUXing
EBI2 GPIO
DEMUX
STD GPIO
DEMUX
UART/UIM glue logic
GPIO registers
Special condition DEMUXing (ETM & test functions)
Interrupt Controller
Keypad
GPIO1
GPIO2
Control registers
GP
IO1
I/F
&
ctl
ckts
standard functional outputs
GPIO registers
Control registers
GP
IO2
I/F
& c
tl ck
ts
ctls
ctls
standard functional
inputs
interrupts
USB functional
I/Os
ARM & DSP ETM/JTAG
System Peripheral
Bridge (SPB)
UART/UIM functional
I/Os
GPIO pads
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GPIO Configuration
• The MSM7200A IC GPIO pin functionality is controlled through thefollowing registers:
– External bus interface 2 (EBI2) supports lower-speed devices» 8 or 16-bit NAND (512 and 2048 bytes/page)» 16 or 18 or 24-bit LCD support» 16-bit oneNAND (muxed and de-muxed modes)
– Most testing and verification to date is done on NAND+DDR SDRAM configuration.
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MSM7200A Memory Map
EBI2Chip Selects
EBI1Chip Selects
SMI
PBL liu.h
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EBI1
• Features– Support for only low-power memories at 1.8 V I/O power supply– Bus frequencies up to 166 MHz (DDR SDRAM mode)– EBI1 connections
» 28-bit address bus» 32-bit bi-directional data bus» Other bus signaling: data strobes, data masks, clocks, chip selects, enables, etc.
MSM7200A
DDRSDRAM
controller
AXI MemCBridge
Read channel
Write channel
Write response
Address channel
Write response ch
AXI
glob
albu
sin
terc
onne
ct
MU
Xlo
gic
ctls
ctls
Peripheral bus
I/O
SDRAM specific I/O-
Page 4880-VE263-25 Rev. AMarch 2007
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EBI1 Pins
MGNDVDD_
C1
EBI2_ DATA
_5
EBI2_ DATA
_3
EBI2_ DATA
_4
EBI2_ DATA
_1MGNDGNDGNDGNDGNDGND
GPIO_111
GPIO_14M
LGNDVDD_ SMIC
EBI2_ DATA
_2
EBI2_ DATA
_0
EBI1_ OE_N
EBI1_ ADR_
4LGND
EBI1_ ADR_
11
EBI1_ ADR_
15
EBI1_ ADR_
17
GPIO_118
GPIO_117
GPIO_116L
KGNDVDD_ SMIP
EBI1_ RESOUT_N
EBI1_ ADR_
6
EBI1_ ADR_
0
EBI1_ ADR_
21817161514131211
JGNDVDD_
C1EBI1_ WE_N
EBI1_ ADR_
3
EBI1_ ADR_
1
EBI1_ ADR_
14
HGNDVDD_ SMIP
EBI1_ ADR_
5
EBI1_ ADR_
7
EBI1_ ADR_
9GND
EBI1_ ADR_
13
EBI1_ CS1_
N
EBI1_ CKE0
EBI1_ DQ_0
EBI1_ DQ_4
EBI1_ DQ_1
3
EBI1_ DQ_1
4
EBI1_ DQ_1
6
EBI1_ DQ_2
4
EBI1_ DQ_2
6
EBI1_ DQ_3
0
HPH_L
GGNDVDD_ SMIP
EBI1_ ADR_
8
EBI1_ ADR_
10GND
EBI1_ ADR_
16
EBI1_ ADR_
21
EBI1_ RAS_
N
EBI1_ DQ_1
EBI1_ DQ_6
EBI1_ DQ_1
1
EBI1_ DQ_1
2
EBI1_ DQ_1
5
EBI1_ DQ_1
7
EBI1_ DQ_2
5
EBI1_ DQ_2
7
EBI1_ DQ_3
1
HPH_R
FGNDVDD_
P1
EBI1_ ADR_
12
EBI1_ ADR_
19
EGNDVDD_
P1
EBI1_ ADR_
18GND
EBI1_ ADR_
23
EBI1_ ADR_
20
EBI1_ CS3_
N
EBI1_ CS4_
N
EBI1_ DQ_3
EBI1_ DQ_7
EBI1_ DQ_9
EBI1_ DQ_1
0
EBI1_ DM_1
EBI1_ DQ_1
8
EBI1_ DQ_2
0
EBI1_ DQS_
3
EBI1_ DQ_2
8
VDD_P4
VDD_A
DGNDVDD_ SMIP
GNDEBI1_ ADR_
22
EBI1_ ADR_
24
EBI1_ CS5_
N
EBI1_ CS2_
N
EBI1_ DQ_2
EBI1_ DQ_5
EBI1_ DQ_8
EBI1_ WAIT0_N
EBI1_ DQS_
1
EBI1_ DM_2
EBI1_ MEM_ CLK
EBI1_ DQ_2
1
EBI1_ DM_3
EBI1_ DQ_2
9GND
GND_A
CGNDVDD_ SMIC
BVSS
THERMAL
EBI1_ ADR_
25
EBI1_ ADR_
26
EBI1_ DCLK
B
EBI1_ DCLK
EBI1_ DM_0
VDD_C1
EBI1_ CS0_
N
VDD_P1
VDD_P1
VDD_C1
VDD_P1
VDD_C1
VDD_P1
EBI1_ DQS_
2
EBI1_ DQ_2
2
VDD_P1
VDD_P1
VDD_C1
EAR1_ ON
AVSS
THERMAL
VSSTHERM
AL
EBI1_ ADR_
27
VDD_P1
GNDEBI1_ CKE1
GNDEBI1_ DQS_
0GNDGNDGNDGNDGNDGND
EBI1_ DQ_1
9
EBI1_ DQ_2
3GNDGNDGND
EAR1_
OP
282726252423222120191817161514131211109
MGNDVDD_
C1
EBI2_ DATA
_5
EBI2_ DATA
_3
EBI2_ DATA
_4
EBI2_ DATA
_1MGNDGNDGNDGNDGNDGND
GPIO_111
GPIO_14M
LGNDVDD_ SMIC
EBI2_ DATA
_2
EBI2_ DATA
_0
EBI1_ OE_N
EBI1_ ADR_
4LGND
EBI1_ ADR_
11
EBI1_ ADR_
15
EBI1_ ADR_
17
GPIO_118
GPIO_117
GPIO_116L
KGNDVDD_ SMIP
EBI1_ RESOUT_N
EBI1_ ADR_
6
EBI1_ ADR_
0
EBI1_ ADR_
21817161514131211
JGNDVDD_
C1EBI1_ WE_N
EBI1_ ADR_
3
EBI1_ ADR_
1
EBI1_ ADR_
14
HGNDVDD_ SMIP
EBI1_ ADR_
5
EBI1_ ADR_
7
EBI1_ ADR_
9GND
EBI1_ ADR_
13
EBI1_ CS1_
N
EBI1_ CKE0
EBI1_ DQ_0
EBI1_ DQ_4
EBI1_ DQ_1
3
EBI1_ DQ_1
4
EBI1_ DQ_1
6
EBI1_ DQ_2
4
EBI1_ DQ_2
6
EBI1_ DQ_3
0
HPH_L
GGNDVDD_ SMIP
EBI1_ ADR_
8
EBI1_ ADR_
10GND
EBI1_ ADR_
16
EBI1_ ADR_
21
EBI1_ RAS_
N
EBI1_ DQ_1
EBI1_ DQ_6
EBI1_ DQ_1
1
EBI1_ DQ_1
2
EBI1_ DQ_1
5
EBI1_ DQ_1
7
EBI1_ DQ_2
5
EBI1_ DQ_2
7
EBI1_ DQ_3
1
HPH_R
FGNDVDD_
P1
EBI1_ ADR_
12
EBI1_ ADR_
19
EGNDVDD_
P1
EBI1_ ADR_
18GND
EBI1_ ADR_
23
EBI1_ ADR_
20
EBI1_ CS3_
N
EBI1_ CS4_
N
EBI1_ DQ_3
EBI1_ DQ_7
EBI1_ DQ_9
EBI1_ DQ_1
0
EBI1_ DM_1
EBI1_ DQ_1
8
EBI1_ DQ_2
0
EBI1_ DQS_
3
EBI1_ DQ_2
8
VDD_P4
VDD_A
DGNDVDD_ SMIP
GNDEBI1_ ADR_
22
EBI1_ ADR_
24
EBI1_ CS5_
N
EBI1_ CS2_
N
EBI1_ DQ_2
EBI1_ DQ_5
EBI1_ DQ_8
EBI1_ WAIT0_N
EBI1_ DQS_
1
EBI1_ DM_2
EBI1_ MEM_ CLK
EBI1_ DQ_2
1
EBI1_ DM_3
EBI1_ DQ_2
9GND
GND_A
CGNDVDD_ SMIC
BVSS
THERMAL
EBI1_ ADR_
25
EBI1_ ADR_
26
EBI1_ DCLK
B
EBI1_ DCLK
EBI1_ DM_0
VDD_C1
EBI1_ CS0_
N
VDD_P1
VDD_P1
VDD_C1
VDD_P1
VDD_C1
VDD_P1
EBI1_ DQS_
2
EBI1_ DQ_2
2
VDD_P1
VDD_P1
VDD_C1
EAR1_ ON
AVSS
THERMAL
VSSTHERM
AL
EBI1_ ADR_
27
VDD_P1
GNDEBI1_ CKE1
GNDEBI1_ DQS_
0GNDGNDGNDGNDGNDGND
EBI1_ DQ_1
9
EBI1_ DQ_2
3GNDGNDGND
EAR1_
OP
282726252423222120191817161514131211109
• 28 address lines, 32 data lines
• 1.8V interface
• 84 dedicated pins
• Supports DDR-SDRAM
• 2 chip selects (both CS must use same number of column and row and density)
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EBI1 Pin Connections
ReservedP1ID17EBI1_WAIT0_N
Output enable for DDR/SDRAMP1OL22EBI1_OE_N
ReservedP1OJ25EBI1_WE_N
DDR RAS_NP1OG19EBI1_RAS_N
P1OH18EBI1_CKE0
DDR clock enablesP1OA23EBI1_CKE1
P1OB21EBI1_CS0_N
DDR SDRAM chip selectP1OH19EBI1_CS1_N
P1OD21EBI1_CS2_N
P1OE21EBI1_CS3_N
ReservedP1OE20EBI1_CS4_N
ReservedP1OD22EBI1_CS5_N
ReservedP1OD14EBI1_MEM_CLK
P1OB25EBI1_DCLKB
Differential clock for DDR SDRAMP1OB24EBI1_DCLK
EBI1 data masksP1OEBI1_DM[3:0]
EBI1 data strobesP1BEBI1_DQS[3:0]
Other EBI1 signaling
32-bit EBI1 data bus; DQ[31] is the MSB, DQ[0] is the LSB.
P1BEBI1_DQ[31:0]
28-bit EBI1 address bus; ADR[27] is the MSB, ADR[0] is the LSB.
P1OEBI1_ADR[27:0]
CommentsDescriptionVoltagedomain
I/OPin #Signal name
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EBI1 Supported Configurations
MSM7200ADDR
SDRAM(32-bit)
32-bitFor 32-bit DDR SDRAM Configuration 1
DDRSDRAM
(16-bit)
DDRSDRAM
(16-bit)
MSM7200A
Two 16-bit DDR SDRAM combined for 32-bit operation. Bus loading may limit actual clock speed.
32-bit
Configuration 2
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DDR SDRAM Support (1 of 2)
• MSM7200A IC supports 32-bit external DDR SDRAM devices.
• MSM7200A IC supports self-refresh.– One CKE for each chip-select signal– Each SDRAM can be powered down individually.
• Supported configurations include:– Single 32-bit DDR device– 32-bit DDR device (2x16-bit)– Both chip selects must have same rows and columns
• Extremely high data rates, hence timing is very crucial– Care must be taken during trace layout and design.– Refer to MSM7200A Mobile Station Modem
IC User Guide (80-VE263-3) for more information regarding design guidelines for DDR SDRAM. EBI 1_DCLK
EBI1_DCLKB
EBI1_CS_N(0/1)
EBI1_ADDR [31:0]
EBI1_DQ [31:0]
EBI1_DQS
DCLK
DCLKB
CS_N
DQS
A [31:0]
D [31:0]
MSM7200A
DDR SDRAM32-bit
Note:
It is recommended to use DDR-SDRAM devices of same density when both EBI1 chip selects are used.
Refer to MSM7200A Mobile Station Modem Revision Guide (80-VE263-4) for more details.
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DDR SDRAM Support (2 of 2)
MSM7200MSM7200A
EBI1_DQS[3:0]
EBI1_CKEEBI1_
EBI1_ DCLKEBI1_ DCLK
EBI1_ DCLKBEBI1_ DCLKB
EBI1_CS_N(0/1)EBI1_CS_N(0/1)
EBI1_WE
EBI1_RAS
EBI1_ADDR[24:0]
EBI1_DQM[3:0]
EBI1_DATA[31:0]
SDRAM SDRAM 16-bit
DCLK
DCLKB
CKE
CS_NCS_N
WE
RAS
DQS[1:0]
DQM[1:0]ADDR[24:0]DATA[15:0]
SDRAM SDRAM 16-bit
DCLK
DCLKB
CKE
CS_NCS_N
WE
RAS
DQS[1:0]
DQM[1:0]ADDR[24:0]DATA[15:0]
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DDR SDRAM Clock
• EBI1_DCLK and EBI1_DCLKB are differential clock outputs.
• All address and control signals are sampled at the rising edge of DCLK and falling edge of DCLKB.
• All data signals are sampled at the crossing of DCLK and DCLKB.
• This effectively doubles the data rate, since the signal is sampled at both rising and falling edges of the clock signal.
tCL
tCK
tIS
EBI1_DCLK
EBI1_DCLKB
EBI1_CKE[1:0]
tCH
tIH
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DDR SDRAM Access Timing
READ Timing
Write Timing
EBI1_DCLK
EBI1_DCLKB
COMMAND
EBI1_ADR
EBI1_DQS
EBI1_DQ
tDV
tDQSQ
tRHZ2
tRPRE
tRHZ
tIPW
tIHtIS
READ NOP NOP NOP NOP NOP
CL = 3
tDQSS
tDH
tDS
tDH
tDS
tDQSL
tDQSH
tIHtIS
EBI1_DCLK
EBI1_DCLKB
EBI1_ADR/COMMAND
EBI1_DQS
EBI1_DQ/DM
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DDR SDRAM Design Considerations
• The extremely high data rates demand very careful timing calculations and controlled impedance routing.
• Signal integrity can be violated with a long PCB trace, excessive parasitic capacitance, or similar layout issues.
• The various DDR signals can be grouped into categories:– Clocks– Data– Address/command– Control– Power
• Special considerations for each group need to be taken; some of the important considerations are listed in the following slides.
Page 5680-VE263-25 Rev. AMarch 2007
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DDR Differential Clock Considerations
• Use controlled impedance lines for each of the two traces.
• Route the traces in parallel and close to each other. – If the trace width is W, spacing between the traces should be on the
order of 2W to 3W.
• The two clock traces must have nearly equal length.– Maintain the trace length difference to be less than 100 mil.– Complementary phase relationship between the two signals will be
degraded if the traces are of different trace lengths.» This can impact the timing and duty cycle.
• Other layout considerations– Route the clock pair on the same critical layer to ensure clocks have
similar signal integrity.– Maintain a solid ground reference for routed clocks, thereby providing
a low-impedance path for return currents.
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DDR DQ and DQS Signal Considerations
• The MSM7200A™ device drives the DQS signal to capture data during reads, and the DDR device drives DQS during writes.
• The timing difference between DQ and DQS signals needs to be minimized. Trace matching is very important.
• DQ and DQS signals are divided into 4 groups» EBI1_DQS[3] ↔ EBI_DQ[31:24]» EBI1_DQS[2] ↔ EBI_DQ[23:16]» EBI1_DQS[1] ↔ EBI_DQ[15:8]» EBI1_DQS[0] ↔ EBI_DQ[7:0]
• Layout considerations– Every eight bits of data and the corresponding DQS signal MUST have
similar trace characteristics:» Trace length differences must be less than 100 mil for the entire group.» Capacitive loading must be similar.
– Make sure to reduce cross-talk noise from adjacent signals on DQS signals.» Maintain at least 4W spacing between DQS and other non-data group signals.
Page 5880-VE263-25 Rev. AMarch 2007
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Other DDR Design Considerations
• All address/command and control signals should have similar trace characteristics (trace length, capacitance, etc.).
– Trace length difference between signals should be less than 150 mil.
• Use distributed and balanced decoupling.
• Keep the VDD_MSME trace as wide a trace as possible, and isolate the trace as much as possible with adjacent ground tracesegments.
• Provide a solid ground reference to all signals.
• Avoid crossing high-speed traces.
• Keep traces short and direct to minimize loss and undesired coupling.
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EBI2
• EBI2 provides support for slower peripheral devices.– NAND flash memory– LCDs– Async devices– FLO receiver– oneNAND
• The EBI2 controller includes three separate controllers:– Serial Flash controller– LCD controller– External memory controller
• Supports 1.8 V or 2.6 V power supply voltages.
• Supports any generic external peripheral whose timing is similar to async memories.
• EBI2 pin connections– 20-bit address bus– 16-bit bidirectional data bus– Six chip-select signals (two LCD, two NAND/oneNAND, and two async)
Also used to select 2nd LCDChip selectP2OAC27EBI2_CS5_N
Output enableP2OP22EBI2_OE_N
Write enableP2OR25EBI2_WE_N
Byte access of 16-bit memoryUpper byte enableP2OR24EBI2_UB_N
Byte access of 16-bit memoryLower byte enableP2OR22EBI2_LB_N
Other EBI2 signaling
16-bit data bus; DATA[15] is the MSB, DATA[0] is the LSB.
P2BEBI2_DATA[15:0]
20-bit address bus; ADR[20] is the MSB, ADR[1] is the LSB.
P2OEBI2_ADR[20:1]
CommentsDescriptionVoltagedomain
I/OPin #Signal nameliu
.hongm
ei2-zt
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LCD Device Support
• Supports 16/18/24-bit port-mapped LCDs.
• Supports 16-bit read and 16-bit, 18-bit and 24-bit writes through parallel interface.
– EBI2_UB/LB_N are used as LCD_DATA[17:16] for 18-bit LCD interface.
– EBI2_UB/LB_N are used as LCD_DATA[17:16] and EBI2_ADR[6:1] are used as LCD_DATA[23:18] for 24-bit LCD interface.
• Two chip selects available:– EBI2_CS4_N (use A16 as LCD_RS for this
chip select).– EBI2_CS5_N* (use A17 as LCD_RS for this
chip select).
• Intel timing – Two chip selects are available.
• Motorola timing– One chip select is available (EBI2_CS4_N).– EBI2_CS5_N is used as LCD_EN.
*NOTE: EBI2_CS5_N is not available in Motorola-style LCD devices; it is used as the LCD_EN signal.
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NAND Memory Support
• MSM7200A IC provides support for 8-bit and 16-bit NAND flash devices.
• Programmable page sizes of 512-byte and 2048-byte (256-byte is NOT supported).
• Hardware supports both MLC and SLC mass storage technologies.
– Current S/W only supports SLC NAND.– MLC NAND will be supported by S/W in Q2
2007.
• Error correction coding (ECC):– 1-bit Reed-Solomon code is used to support SLC-
based devices.– 4-bit Reed-Solomon code is used to support
MLC-based devices.– For each 512 bytes of user data, 4 bytes of ECC is
available.» For every 512 bytes of user data, there are 4
bytes of ECC data to recover 1 bit of user data.
• NAND interface shares the EBI2 ports with other external SRAM devices.
• Two chip selects are available for NAND:– EBI2_CS0_N– EBI2_CS1_N
• Maximum addressable memory space of greater than 1 GByte.
Note: MSM7200A does not support simultaneous NAND and oneNAND operation.
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NAND Pin Connections
NAND dataP2BEBI2_DATA[15:0]
NAND signalVoltage domain
DirectionPin #EBI2 pin
Busy signal P2IAA25EBI2_BUSY0_N
Chip select 1st NANDP2OY25EBI2_CS0_N
Chip select 2nd NANDP2OV21EBI2_CS1_N
NAND_RE_NP2OP22EBI2_OE_N
Write enableP2OR25EBI2_WE_N
NAND_CLEP2OR24EBI2_HB_N
NAND_ALEP2OR22EBI2_LB_N
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NAND Interface Timing
• Each access to NAND flash devices involves the controller executing a sequence of signal assertion and de-assertion, according to the timing requirements of the connected device.
• The transfer sequence is defined using registers FLASH_XFR_STEP(1–7).– The register values dictate the signal status.
• There are seven distinct configurations, including wait states: – FLASH_XFR_STEP1 to FLASH_XFR_STEPn
startPads state are controlled by step register FLASH_XFR_STEPx
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NAND Flash Timing
• Step configuration registers (FLASH_XFR_STEPn) are divided as follows:– Bits [31:16]: “Command” and “Address” cycles– Bits [15:0]: “Data” cycles
• If the step configuration is changed, then the timing parameters mapped to the registers can be adjusted accordingly.
31:30
29:26
24
23
22
21
20
19
18
15:14
13:10
8
7
6
5
4
3
2
1:0
CMD_SEQ_SETP_NUM
CMD_STEP1_WAIT
CMD_DATA_EN
CMD_CE_EN
CMD_CLE_EN
CMD_ALE_PIN
CMD_WE_EN
CMD_RE_EN
CMD_WIDE
DATA_SEQ_STEP_NUMBER
DATA_STEP1_WAIT
DATA_DATA_EN
DATA_CE_EN
DATA_CLE_EN
DATA_ALE_PIN
DATA_WE_EN
DATA_RE_EN
DATA_WIDE
EXTA_READ_WAIT
FLASH_XFR_STEPx (x = 1 to 7)
Command/Address Data
17:16 RESERVED*
25 CMD_AOUT_EN* 9 DATA_AOUT_EN*
* Not used
NOTE:
1. ALE_PIN and CLE_EN bits are the "enable" control of the external pin. When set (1), the ALE and CLE are controlled by the NANDC sequencer. When clear (0), ALE and CLE are disabled (signal=low).
2. Read data wait can be incremented without changing the write data wait states using bits [1:0].
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NAND Flash Timing Example
1. Assert CS_N (CS_N = 0).
2. Wait for CS_N-to-OE_N setup time for read from flash.
3. Assert OE_N (OE_N = 0) and read data.
Repeat for consecutive data reads.
NAND_CSx_N
ValidEBI2_DQ[15:0]
t(dh)
ALE/CLE
OE_N
1
NAND Data Read
Data 0
Commandcycle
EBI2_BUSY0_N
Data 1 Data n
2 3 2 3 2 3 4
t(ds)
t(rd) t(rdw)
t(rr)
t(bsy)
*
* During data read wait period , ALE and CLE stay low only if NAND _CSx_N is driven low as required by the FLASH device .
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oneNAND
• oneNAND is a NAND-type flash memory that interfaces like NOR memory.
• Supported oneNAND configuration– 16-bit oneNAND– Asynchronous and synchronous timing
• Testing is ongoing
Note: MSM7200A does not support simultaneous NAND and oneNAND operation.
MSMMSM7200A
EBI2_CS_N (0/1)
SDRAM oneNAND
CE
A[15:0]
DQ[15:0]
EBI2_OE_N
EBI2_WE_N
EBI2_ADR[19](EBI2_ONENAND_RDY_IN)
EBI2_DATA[15:0]
OE
WE
AVD
INTEBI2_BUSY0_N
VREG_MSME
EBI2_LB_N(oneNAND_AVD_N)
EBI2_CLK CLK
READY
EBI2_ADR[16:1]
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MSM7200A Device InterfacesMDDI
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Mobile Display Digital Interface (MDDI)
• MDDI is a cost-effective, low-power solution that enables high-speed, short-range communication between the MSM device and camera/display device.
• MSM7200A device has three dedicated MDDI interfaces.
– Two “host” interfaces for LCDs
– One “client” interface for camera application
• Two Type I MDDI “host”interfaces
– Two low-swing differential signal pairs (data and strobe)
• Type II MDDI “client” interface– Supports higher data rates by
sending multiple bits in parallel (data0, data1, and strobe).
MSM7200A
MDDIClient
( Type II )
MDDIHost
( Type I )
MDDIHost
( Type I )
MDDIHost
MDDIClient
MDDIClient
Camera Module
Device LCDs
External Device
MDDI Link3 pairs
MDDI Link2 pairs
MDDI Link2 pairs
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MDDI Pin Connections
MDDI groundGNDIAE15VSS_MDDI
From PM7540 IC; 1.8 V typ, programmable from 1.500 to 3.050 V in 50 mV steps.
MDDI power supply1.8IAD15VDD_MDDI
MDDI power and ground
1.8BAB15MDDI_E_DATA_P
Low-swing differential signal; connects to MSM host; high-Z default state
Peripheral differential data pair1.8BAA15MDDI_E_DATA_N
1.8OAA14MDDI_E_STB_P
Low-swing differential signal; connects to MSM host; high-Z default state
Peripheral differential strobe pair
1.8OAB14MDDI_E_STB_N
External MDDI connections (peripheral)
1.8BAH13MDDI_C_DATA1_P
Low-swing differential signal; connects to MSM client; high-Z default state
Camera differential data pair 11.8BAG13MDDI_C_DATA1_N
1.8BAH14MDDI_C_DATA0_P
Low-swing differential signal; connects to MSM client; high-Z default state
Camera differential data pair 01.8BAG14MDDI_C_DATA0_N
1.8OAH15MDDI_C_STB_P
Low-swing differential signal; connects to MSM client; high-Z default state
Camera differential strobe pair1.8OAG15MDDI_C_STB_N
MDDI camera connections
1.8BAE14MDDI_P_DATA_P
Low-swing differential signal; connects to MSM host; high-Z default state
LCD differential data pair1.8BAD14MDDI_P_DATA_N
1.8OAE13MDDI_P_STB_P
Low-swing differential signal; connects to MSM host; high-Z default state
LCD differential strobe pair1.8OAD13MDDI_P_STB_N
Primary MDDI connections (LCD)
CommentsDescriptionVoltageI/OPin #Signal name liu.h
Typical DVB-H modules do not support TSIF. DVB-H modules usually support SDIO output.
8 MHzCOFDMUS/EuropeDVB-HDigital Video Broadcast -Handheld
Typical S-DMB modules use TSIF.25 MHz4XWCDMAKoreaS-DMBSatellite - Digital Mobile Broadcast (ARIB STB-B41)
Typical ISDB-T modules use TSIF.6 MHz or 6/13 MHzOFDMJapanISDB-TIntegrated Service Digital Broadcasting -Terrestrial transmission(ARIB STD-B31)
CommentsBandwidthTechnology and modeRegionStandard
Mobile broadcast standard
The handset’s mobile broadcast implementation (see figure) that uses a separate, non-WCDMA radio link has its own antenna.
Depending on the standard used, the broadcast module may or may not output H.222.0 MPEG2 Transport Stream packets that the MSM7200A supports.
TS interface in MSM7200A IC ONLY supports transport of TS packets from broadcast module to the MSM. Most DVB-H modules only support SDIO interface which requires OEM to provide its own driver.Handset DMB receive block diagram
H.222.0 Transport
Stream
CustomerSolution
MSM7200A
Handset Radio Link
BroadcastTuner Demodulator
RF
Inte
rface
CDMA Radio Antenna
DMB Antenna
LCD Display&
Sound
TSIF
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TSIF Block Diagram
Inpu
tsta
tem
achi
ne
EHIs
tate
mac
hine
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TSIF Signaling
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 07
TSIF_CLK
TSIF_EN
TSIF_DATA
Byte 0MSB…………………..…LSB
Byte 187
Min. 1504 (188x8) TSIF_CLK cycles and 188 Bytes
TSIF Packet Timing
TSIF_EN
Valid Packet
Valid Packet
1504 Clocks 1504 Clocks
Min. 1 TSIF_CLK5 to 20 (Typ.)
Note: (1) TSIF_EN input can be programmed as “active low” or “active high” signal. (2) TSIF_EN and TSIF_DATA are sampled on either rising or falling TSIF_CLK edge.
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MSM7200A TSIF Features
• 3- or 6-pin serial interface
• Supports external clocks up to 4 MHz with a maximum data rate of0.5 MB per second.
• The data mover (DM) transfers HTS packets directly from the external interface to system memory.
• 4 bytes of additional information (time stamp and flags) are provided with every HTS packet.
– TSIF time stamp (TTS) is based upon a 27-MHz TSIF clock reference (TCR).
• Enhanced fallback and/or debug support using a software-based copy mechanism when HTS packets are transferred directly from the external interface to system memory
• Reports the status of each HTS packet transferred to memory via the DM or software copy.
• Optional interrupts for critical events: loss-of-sync, packet available, and packet overflow
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Universal Broadcast Modem (UBM)
• QUALCOMM Universal Broadcast Modem™ (UBM™) provides single-chip solution for the world's leading mobile broadcast standards. It provides handset manufacturers unprecedented flexibility while creating a time to market advantage. By combining digital and RF functionality into a single package, UBM chip is a size- and cost-efficient solution. QUALCOMM's UBM chipset family includes:
– MBP1600™ - supports wideband MediaFLO™, DVB-H, and ISDB-T– MBP1610™ - supports MediaFLO in US
• These chipsets are single-chip solution that includes RF and baseband processing. They are MSM-companion ICs that provide broadcast receive-only tuning, demodulation, and decoding capabilities.
• There are two MBP/MSM interfaces: the MSM’s EBI2 and the Transport Stream Interface (TSIF). The MSM device’s ARM® always configures the MBP via EBI2. The interface used for physical layer data transport from the MBP1600 device to the MSM device depends upon the broadcast standard being supported:
– MediaFLO uses EBI2 only– DVB-H and ISBD-T use both EBI2 and TSIF
• The MediaFLO, DVB-H, and ISDB-T software protocol stacks (including video decoding and processing) are all handled within the MSM device.
progressive to interlace scan /anti-flicker filter
NTSC/PAL Encoder
Periph bus I/F
video data
synchronization
Video DAC
10-bit data
SLEEP
Periph bus
AXI bus TV_OUT to PMIC
27 MHz clock
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MSM7200A TV-out Implementation Example
VIDEO_ OUTVIDEO_INVideoDAC
PM7540
TV present detection
15 uH
30 pF
VREG_ MSMA
MSM7200AVDD_A
TVOUT
VSS_ TVOUT_DACTVDAC_R_SET649
39 pF
649
2. 7 pF
0.1 uF
75
VDDVDD
TV load
Shielded cable
75
ESD protection device; 10 pF max
interrupt
3 2
reconstruction filter
U4
4.64 k
T8
U2
4.7 uF
1%
Note: Reconstruction filter component values may not be the most up-to-date. Refer to the MSM7200A Baseband Reference Schematic (80-VE263-41) for the latest information.
Note: Ensure that the MSM7200A and PM7540 devices are placed close together. Keep the TVOUT signals between these devices as short as possible.
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MSM7200A Device InterfacesHKADC
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Housekeeping ADC (HKADC)
• The MSM7200A IC has an on-chip 12-bit analog-to-digital converter.
• This HKADC is used for digitizing signals that support handset-level housekeeping functions.
– Nine inputs» Three inputs are available as general purpose inputs.» Five inputs are dedicated for touchscreen functions.» One reserved pin
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HKADC Connections
Signal Name Pin # I/O Description Comments
General Housekeeping inputs
HKAIN[0] F2 I
HKAIN[1] F1 I
HKAIN[2] B4 I
Three general purpose inputs to the HKADC analog multiplexer
Touchscreen inputs
TS_LR D1 I 5-wire LR; 4-wire Y-
TS_LL D2 I 5 wire LL; 4-wire X-
TS_UR E1 I 5-wire UR; 4-wire Y+
TS_UL E2 I 5-wire UL; 4-wire X+
WIPER C1 I 5-wire back panel input
Not used for 4-wire
Note:
If 4-wire touchscreen interface is used, wiper pin can be used as HKADC general input pins.
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HKADC Block Diagram
anal
og m
ux
mux_sel_n
TS_LLD2
D1
HKAIN[0]
HKAIN[2]
HKAIN[1]
F2
B4
F1available as general purpose HKADC inputs
from the touch screen panel
TS_LR
TS_UR
WIPER
TS_UL
E1
C1
E2
sample and hold
12-bit ADC
A_IND_OUT
CLK
VREF
EOC
TSHK_PARAM[7:6]
TCXO/8
TCXO/16
TCXO/32
TCXO/4
HKADC_DATA_RD [11:0]
ADC_EOC
VDD_A
Internal
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MSM7200A Device InterfacesTouchscreen
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Touchscreen Interface
• MSM7200A IC supports both 4-wire and 5-wire resistive touchscreen panels.
– All resistive touchscreens use the voltage divider principle to generate voltages that represent X and Y coordinates.
– 4-wire consists of two resistive layers. The controller supplies voltages to one layer and reads the voltages from the other layer to determine the X and Y values.
– 5-wire works very similarly to the 4-wire. It consists of one conductive and one resistive layer. Controller alternates voltages between two of the four corners on the resistive layer and reads voltages on the conductive layer via wiper to determine the X and Y values.
• The TSADC is a 12-bit successive approximation device.
• The conversion result is sent to the touchscreen sampling controller (TSSC) via SSBI, and TSSC generates the necessary interrupts.
• Detailed information on how the touchscreen interface works is included in Application Note: Touchscreen Operation for MSM7200 and MSM7500 (80-V9038-11).
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Touchscreen Features
• One interface supports both 4-wire and 5-wire resistive touch panels.
• Pen-down detection
• Programmable debounce logic
• Programmable number of samples (1, 4, 8, or 16)
• Programmable precharge and panel voltage-stabilization duration
• Programmable resolutions (8-bit, 10-bit, or 12-bit)
• Programmable sampling periods (3, 24, 36, and 48 clock cycles of a 2.4 MHz clock)
• Ratiometric conversion
• Touch pressure Z1 and Z2 measurement
• X and Y coordinate measurement
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Touchscreen Interface Diagram
Codec/TSADCSSBI Master
Codec/TSADCSSBI Slave
TSADCSBI Registers
TSADC Controller
TSADC
Touch ScreenSampling Controller
(TSSC)
ADC_EOC
Debounce LogicAO Domain
PEN_IRQ_N
PenIrqN
tssc1_irqtssc2_irq
SPB
ADSP
SPB
MSM7200ATS_UL TS_LRTS_URTS_LL WIPER
5-wireTouch Screen Panel
UL LRURLL Wiper
4-wireTouch Screen Panel
Xp YmYpXm
WakeUp Interrupt
SSBI
Page 9880-VE263-25 Rev. AMarch 2007
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MSM7200A Touchscreen Operation Flow
PenIrq B sensed
Sample Data
Start Conversion
Wait for EOC
Intrvalid?
Sample Data
N samples collected?
X, Y measured?
Precharge PenIrqB
Idle
Yes
Yes
Yes
No
No
No
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Touchscreen ADC Contention Issue
• Contention issue arises when another ADC sampling request is trying to access the ADC controller while touchscreen sampling is ongoing.
– If another ADC sampling request comes in when the touchscreen sampling process is ongoing (ex: HDET, VBATT, etc.), the touchscreen sample will be corrupted and a TSSC_ADC_EOC timeout error occurs.
– The touchscreen sample is corrupted and ADC is no longer sampling the touchscreen. TSSC is unaware of this and keeps waiting until the timeout occurs. The touchscreen operation is frozen.
• Software workaround will be available.– During touchscreen sampling activity, the ADC will not accept any
other sampling requests.– Please consult with QUALCOMM for further details.
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MSM7200A Device InterfacesUART/USB/UIM/SDIO
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USB Connectivity
• The MSM7200A IC supports internal full-speed OTG USB and external high-speed OTG ports.
• Supported speeds– The MSM7200A USB-OTG core supports two speeds while acting as a host:
» Full speed (12 Mbps)
» High speed (480 Mbps)
• Full-speed USB– On-chip (internal) USB solution with external transceiver provided by PM7540.– FS USB is on-the-go (OTG) compliant, and hence can be configured either as host or
peripheral.
– This port should be configured to support devices with three-wire interface only.
– USB port uses a mini-AB receptacle.
• High-speed OTG USB– On-chip (internal) USB solution with an external PHY transceiver.
– This port has USB-OTG capabilities.
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HS-USB Pin Connections Diagram
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USB Pin Connections
P8IK1USBH_CLK
P8BUSBH_DATA[7:0]
P8IU7USBH_DIR
P8IV12USBH_NEXT
P8OJ8USBH_STOP
High-Speed OTG USB
Active low enables the D+ and D- pins; resets to output driving high.
P3BAE9USB_OE_INT_N
Single-ended data or differential minus (D-); resets to input.
P3BAB12USB_SE0_VM
Single-ended data or differential plus (D+); resets to input.
P3BAD12USB_DAT_VP
Full-Speed OTG USB
CommentsDescriptionVoltageI/OPin #Signal name
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USB-UICC
• MSM7200A supports USB-UICC– Enables the use of SIM cards with mass storage capability.
• Level translator may be required on the USB3 lines depending on desired operating voltage of the UICC card.
– Pins AC24 and AE28 are GPIO pins and has its own fixed operating voltage range that may or may not be compatible with the UICC card’s operating voltage.
– The direction pin on level translator can be controlled from USB3_OE_INT_N of the MSM device.
Contact QUALCOMM for more details and schedule.
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UART Connectivity
• The MSM7200A IC is capable of providing up to four UART ports.
• Each UART port communicates with serial data ports that conform to the RS-232 interface protocol.
• The UART port can be used for test and debug functions, and can support additional interface functions such as external keypad or ringer.
• UART supported speeds– UART1
» UART1 is capable of supporting a maximum transfer speed of up to 230 kbps.– UART2 and UART3
» These two ports have smaller FIFOs, and therefore the supported speeds are much slower.» Supports a maximum speed of up to 115 kbps.» UART2 must be used for USIM.
• High-speed UART– High-speed UART is achieved using UART1DM and UART2DM interfaces.
» UART1DM is behind the UART1 interface.» UART2DM has its own set of GPIOs.
– Maximum speeds up to 4 Mbps
• UART featuresThe UART has several features that are common to both transmit and receive modes:
– Hardware handshaking– Programmable parameters
» Data size» Stop bits» Parity» Bit rate» Selectable clock source
• All UART signals use GPIOs; this allows them to be configured for alternate functions.
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UART Pin Connections Diagram
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UART Pin Connections (1 of 2)
Transmit serial data outputP3OV17UART2DM_TXGPIO[108]
Receive serial data inputP3IAG18UART2DM_RXGPIO[21]
Clear to sendP3IAA18UART2DM_CTS_NGPIO[20]
Ready for receivingP3OAE17UART2DM_RFR_NGPIO[19]
UART2DM
Shares same GPIO as UART1DM.Transmit serial data outputP3OAA9UART1_TXGPIO[46]
Shares same GPIO as UART1DM.Receive serial data inputP3IAB9UART1_RX_DATAGPIO[45]
Shares same GPIO as UART1DM.Clear to sendP3IAG6UART1_CTS_NGPIO[44]
Shares same GPIO as UART1DM.Ready for receivingP3OAA10UART1_RFR_NGPIO[43]
UART1 / UART1DM
CommentsDescriptionVoltageI/OPin #Signal name
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UART Pin Connections (2 of 2)
Transmit serial data outputP3OAD25UART3_TX GPIO[87]
Receive serial data inputP3IAC25UART3_RX_DATAGPIO[86]
Clear to sendP3IAE28UART3_CTS_NGPIO[85]
Ready for receivingP3OAC24UART3_RFR_NGPIO[84]
UART3
USIM must use UART2.Transmit serial data outputP3OAD9UART2_TXGPIO[50]
USIM must use UART2.Receive serial data inputP3IAE8UART2_RX_DATAGPIO[49]
USIM must use UART2.Clear to sendP3IAH6UART2_CTS_NGPIO[48]
USIM must use UART2.Ready for receivingP3OAD8UART2_RFR_NGPIO[47]
UART2
CommentsDescriptionVoltageI/OPin #Signal name liu.h
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UART Block Diagram
• The UART core consists of separate transmit and receive channels.
• The Tx and Rx data is processed with separate FIFOs.
– Both Tx and Rx FIFOs are 512 bytes (UART1).
• Other support blocks include:– Clock source
» Each UART interface has its own clock source.
» The UART clock is derived from the selected clock source.
» The clock source is selected by setting the MISC_CLK_SEL1 register.
– Bit rate generator (BRG)» The desired bit rate for the receive and
transmit channels is selected using the UART_CSR register.
» Each UART can be set independently.» Speeds range from 75 bps to 230 kbps
and 1.152 Mbps.– Microprocessor interface– Interrupt control
• UART2 and UART3 interfaces have a 64-byte FIFO in the transmit and receive channels.
– The speed of these two interfaces is much slower than UART1.
Tx FIFO
Tx control module
Channel control
BRG Interrupt control
Rx FIFO
Rx control module
Microprocessor interface
Clock generator & M/N counter
Internal uP bus
TCXO/4SLEEP_XTAL
Transmit Channel
Receive Channel
Tx data Controls
CTS_N
Err
orbi
ts
Rx data
Status
Data FIFO control
DP_TX_DATA
UA
RT
_IN
T
RFR_N
DP_RX_DATA
Con
tro
ls
Status
Data FIFO control
MSM7200A
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IrDA through UART Interface
• The MSM7200A IC contains an IrDA transceiver that interfaces between the UART and RX_DATA/TX_DATA pins.
• The IrDA feature is available for all three UART interfaces (UART1, UART2 and UART3).
• The IrDA feature is fully supported in hardware, but it is NOT supported by QUALCOMM software.
Refer to MSM7200A Mobile Station Modem IC User Guide (80-VE263-3) for information regarding the IrDA interface.
• IrDA Tx converts the serial data into IrDA format.
• Some USB OTG core signals ( DAT_VP and SE0_VM) and UART1 signals (RX_DATA and TX_DATA) are multiplexed onto the same pins (AD12 and AB12).
• The pin functionality is selected by setting the USB_PIN_SEL register.
• There are three modes of operation:– USB mode– UART mode– Register mode (bit-banged)
• Therefore, in order to use the UART GPIO pins for alternate functions, the UART1 RX_DATA and TX_DATA can be routed to pins AD12 and AB12, respectively.
V 18
USB_DAT_ VP
AD12
AB12
USB_SE0_ VM
USB_OE_INT_N
USB_RCVGPIO[ 83]
usb3_oe_n
usb3_dat_vp_ out
usb3_se0_ vm_ out
usb3_dat_ vp_in
usb3_se0_vm_in
USB3
usb2_oe_n
usb2_dat_vp_ out
usb2_se0_ vm_ out
usb2_dat_ vp_in
usb2_se0_vm_in
USB2
USB_OE_N
USB_DAT_VP_ OUT
USB_SE0_VM_ OUT
USB_DAT_VP_IN
USB_SE0_VM_IN
USB-OTG core
USB_RCV_IN
USB_OE_IRQ_N
USB2_PORT_ SEL
USB_ REG_ SEL
REG_SE0_VM_OE
REG_ DAT_VP_OE
TLMM registers
REG_DAT_VP_ OUT
REG_ OE_ INT_OE
REG_OE_ OUT_N
USB_UART_ SEL
REG_SE0_VM_ OUT
UART1_ TXD
UART1_ RXD
UART1
usb3_oe_int_n
usb3 _<dat_vp,se0_vm>_en
usb3_dat_vp_ out
usb3_dat_vp_in
usb3_se0_vm_out
TLMM GPIO mux
usb3_se0_vm_in
usb2_oe_int_n
usb2 _<a, b>_<dat_vp,se0_vm>_en
usb2 _<a, b>_dat_vp_ out
usb2_a_dat_vp_in
usb2 _<a, b>_se0_vm_ out
usb2_a_se0_vm_in
usb2_b_dat_vp_in
usb2_b_se0_vm_in
1
0
1
0
1
0
1
0keeper
1
0
1
0
keeper
usb_ rcv
1
0
AE 9keeper
1
0
1
0
uart1_tx_ data
uart1_rx_data
AA9
UART1_TX_ DATAGPIO[ 46]
AB9
UART1_RX_ DATAGPIO[ 45]
MSM7200A
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UART1DM/UART2DM (UART1/UART2 Data Mover)
• The MSM7200A IC needs to provide support for medium-rate IrDA (1.15 Mbps).
• The UART block is connected on the slow peripheral (microprocessor) bus, and cannot provide such a high bandwidth.
• To support this data rate, the UART1DM and UART2DM block is implemented in the MSM7200A IC.
• The UART1DM and UART2DM are on the fast peripheral bus (AHB), and can support the high bandwidth required for medium-rate IrDA.
• UART1DM/UART2DM features:– Support for medium-rate IrDA (1.15 Mbps)– Support for high-speed UART feature (up to 4 Mbps)– Separate Tx/Rx FIFOs (implemented in one SRAM)
» Tx/Rx FIFOs share the same 512 byte memory.
– 32-bit wide AHB interface– Rate-controlled data mover (separate channel for Rx/Tx)
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UARTDM Architecture
Clock and bit-rate
generator
Transmit channel
CTS_N
DP_ TX_ DATA
RFR_N
DP_ RX_ DATA
MSM7200A
Receive channel
UART clock domainAHB clock domain
8
data_ load
8
data_ ready
8
data_ load
8
data_ ready
AHB bridge
Interrupt registers
Rx & Tx registers
DM registers
BRG registers
Registers
AHB bus
uart_irq
uart_ fund_clk
tx_ dm_ reg
tx_ dm_ ack
rx_ dm_ reg
rx_ dm_ ack
Controller
128 x 32RAM
Clockdomains
translation
CGC
reg
IrDAifc
stable_cts_n
Page 11480-VE263-25 Rev. AMarch 2007
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UARTDM Operation (1 of 2)
Traditional UART transfer
1. Initialize UART.
2. UART sends an interrupt to CPU each time FIFO holds less than pre-programmed number of characters. This interrupt signals the CPU that new data burst can be sent to UART Tx block.
3. UART transmits character-by-character until Tx FIFO is empty.
UARTDM transfer
1. Initialize UART.
2. Initialize data mover (DM).
3. Enable the Tx-DM transfer mode.
4. UART sends a request to DM when there is space available in Tx FIFO. DM responds by sending the data burst via AHB bus to Tx FIFO. This continues until Tx FIFO is full.
5. UART transmits character-by-character until Tx FIFO is empty.
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UARTDM Operation (2 of 2)
• UARTDM is connected to the AHB bus, and includes two rate-controlled data mover interfaces (one for Tx and one for Rx).
• All configuration registers are in the AHB clock domain.
• Rx path is independent of Tx path. Therefore, UART block can receive data during an active Tx transfer.
• Commonality is the shared SRAM between Tx/Rx FIFOs.– Sharing occurs during the initialization phase.
– Memory space is not necessarily shared equally.
Page 11680-VE263-25 Rev. AMarch 2007
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UARTDM IrDA
• To support an IrDA medium data rate of 1.15 Mbps, UART must run at a high clock frequency of 18.4 MHz.
• The UART1DM CSR register needs to be set to determine the bit rate for Tx and Rx.
• The UART1DM_IRDA register enables the IrDA function. This register also controls the IrDA transceiver that optionally interfaces between the UART and the RX_DATA and TX_DATA pins.
• Refer to the MSM7200A Mobile Station Modem Software Interface (80-VE263-2) for information regarding UART1DM and UART2DM registers and settings.
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1-bit 4-bit 8-bit Max. frequency of operation (MHz)
SDIO v2.0 Yes Yes Yes 50
SD v2.0 Yes Yes Yes 50
MMC v4.1 Yes Yes Yes 52
SD Interface
• MSM7200A IC supports MMC, SD, SDIO, and T-Flash.– Supports 1-bit, 4-bit and 8-bit modes.– Four SDC ports are available on the MSM7200A IC.
• 2.5 to 3.0 V operation
• Supported Standards
SDCC architecture
SDCC
SD/MMC
Interrupt
DM lfc
Slave
Host
D[3:0]
CMD
CLK
SDCC interrupts
DMReq/Ack
AHBinterface
Note: Refer to Application Note: MultiMedia Card / SD Card (80-V7837-1) for more details.
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SDC1 Connections
SDC1 clockDigitalOAB11GPIO[56]SDC1_CLK
SDC1 command and response bit
DigitalBAE10GPIO[55]SDC1_CMD
SDC1 data bit #0DigitalBAD11GPIO[54]SDC1_DATA[0]
SDC1 data bit #1DigitalBV13GPIO[53]SDC1_DATA[1]
SDC1 data bit #2DigitalBAH8GPIO[52]SDC1_DATA[2]
Primary SDC data busSDC1 data bit #3DigitalBAA11GPIO[51]SDC1_DATA[3]
SDC1
CommentsDescriptionVoltageI/OPin #Signal name
AD11
MSM7200ASDC1_ DATA[3]
GPIO[51]AA11
V13
AH8
AE10
AB11
SDIO#1
SDC1_ DATA[2]GPIO[52]
SDC1_ DATA[1]GPIO[53]
SDC1_ DATA[0]GPIO[54]
SDC1_ CMDGPIO[55]
SDC1_CLKGPIO[56]
SD
C_D
AT
A[3
:0]
SDC_ CMD
SDC_CLK
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SDC2 Pins
SDC2 clockDigitalOAE11GPIO[62] SDC2_CLK
SDC2 command and response bit
DigitalBAA12GPIO[63]SDC2_CMD
SDC2 data bit #0DigitalBV14GPIO[67]SDC2_DATA[0]
SDC2 data bit #1DigitalBV15GPIO[66]SDC2_DATA[1]
SDC2 data bit #2DigitalBAE12GPIO[65] SDC2_DATA[2]
SDC2 data bit #3DigitalBAA13GPIO[64]SDC2_DATA[3]
SDC2
CommentsDescriptionVoltageI/OPin #Signal name
V14
MSM7200ASDC2 _ DATA[3]
GPIO[64]AA13
V15
AE12
AA12
AE11
SDIO#2
SDC2 _ DATA[2]GPIO[65]
SDC2 _ DATA[1]GPIO[66]
SDC2 _ DATA[0]GPIO[67]
SDC2 _ CMDGPIO[63]
SDC2_CLKGPIO[62]
SD
C_D
AT
A[3
:0]
SDC_ CMD
SDC_CLK
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SDC3 Pins
SDC3 clockDigitalOAA16GPIO[88] SDC3_CLK
SDC3 command and response bit
DigitalBAG16GPIO[89]SDC3_CMD
SDC3 data bit #0DigitalBAD16GPIO[93]SDC3_DATA[0]
SDC3 data bit #1DigitalBV16GPIO[92]SDC3_DATA[1]
SDC3 data bit #2DigitalBAE16GPIO[91] SDC3_DATA[2]
Can be combined with SDC4 to enable 8-bit SD interface.
SDC3 data bit #3DigitalBAB16GPIO[90]SDC3_DATA[3]
SDC3
CommentsDescriptionVoltageI/OPin #Signal name
AD16
MSM7200ASDC3 _ DATA[3]
GPIO[90]AB16
V16
AE16
AG16
AA16
SDIO#3
SDC3 _ DATA[2]GPIO[91]
SDC3 _ DATA[1]GPIO[92]
SDC3 _ DATA[0]GPIO[93]
SDC3 _ CMDGPIO[89]
SDC3_CLKGPIO[88]
SD
C_D
AT
A[3
:0]
SDC_ CMD
SDC_CLK
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SDC4 Pins
SDC4 clockDigitalOAB25GPIO[109] SDC4_CLK
SDC4 command and response bit
DigitalBAB24GPIO[107]SDC4_CMD
SDC4 data bit #0DigitalBV17GPIO[108]SDC4_DATA[0]
SDC4 data bit #1DigitalBAG18GPIO[21]SDC4_DATA[1]
SDC4 data bit #2DigitalBAA18GPIO[20] SDC4_DATA[2]
Can be combined with SDC3 to enable 8-bit SD interface.
SDC4 data bit #3DigitalBAE17GPIO[19]SDC4_DATA[3]
SDC4
CommentsDescriptionVoltageI/OPin #Signal name
V17
MSM7200ASDC4 _ DATA[3]
GPIO[19]AE17
AG18
AA18
AB24
AB25
SDIO#4
SDC4 _ DATA[2]GPIO[20]
SDC4 _ DATA[1]GPIO[21]
SDC4 _ DATA[0]GPIO[108]
SDC4 _ CMDGPIO[107]
SDC4_CLKGPIO[109]
SD
C_D
AT
A[3
:0]
SDC_ CMD
SDC_CLK
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SDC3 8-bit Interface
SDC3 (8-bit)
SDC3 data bit #7DigitalBAE17GPIO[19]SDC3_DATA[7]
SDC3 data bit #6DigitalBAA18GPIO[20] SDC3_DATA[6]
SDC3 data bit #5DigitalBAG18GPIO[21]SDC3_DATA[5]
SDC3 data bit #4DigitalBV17GPIO[108]SDC3_DATA[4]
SDC3 clockDigitalOAA16GPIO[88] SDC3_CLK
SDC3 command and response bit
DigitalBAG16GPIO[89]SDC3_CMD
SDC3 data bit #0DigitalBAD16GPIO[93]SDC3_DATA[0]
SDC3 data bit #1DigitalBV16GPIO[92]SDC3_DATA[1]
SDC3 data bit #2DigitalBAE16GPIO[91] SDC3_DATA[2]
SDC3 data bit #3DigitalBAB16GPIO[90]SDC3_DATA[3]
DescriptionVoltageI/OPin #Signal name
AD16
MSM7200A
AB16
V16
AE16
AG16
AA16
SDIO
SDC_ CMD
SDC_ CLK
V17
AE17
AG18
AA18
SDC3 (8-bit) SDC3_DATA[3]GPIO[90]
SDC3_DATA[2]GPIO[91]
SDC3_DATA[1]GPIO[92]
SDC3_DATA[0]GPIO[93]
SDC3_CMDGPIO[89]
SDC3_CLKGPIO[88]
SDC3_DATA[7]GPIO[19]
SDC3_DATA[6]GPIO[20]
SDC3_DATA[5]GPIO[21]
SDC3_DATA[4]GPIO[108]
SDC
_DAT
A[7:
0]liu
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MSM7200A Device InterfacesAudio
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Audio
• MSM7200A IC audio front end includes the following:– Stereo wideband codec– PCM interface– Additional DSP audio processing
• Stereo wideband codec– MSM7200A IC supports stereo wideband sampling in both Tx and Rx paths.– Stereo music/ringer melody applications through line-in inputs– Supports 8 kHz voice-band applications on forward link.– Software-selectable sampling rate up to 48 kHz in receive path**
• PCM interface– The PCM interface allows for an external codec to be used instead of the internal
codec.– Supports I2S modes that allow an external stereo DAC to be used.
legacy or OCL stereo headset output (stereo single-ended or mono differential), single-ended mono AUX output and dedicated stereo line-output
– 13/16-bit DAC with typical 88 dB dynamic range
– Rx sampling rates: 8, 16, 22.05, 24, 32, 44.1, and 48 kHz (Rate support varies between voice and playback; check software release plan.)
– Supports summing an external device's stereo (left, right) single-ended analog signal into earphone outputs.
– CodecRxGain, RxVolume software-adjustable from –84 dB to +12 dB in steps of 1dB
– RxPcmFilter – similar to TxPcmFilter– RxHPF – similar to TxHPF
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Stereo Wideband CODEC + Audio DSP
Note: Internal loopbacks exist to drive speakers for external input device or for signal-level verification: AUX-PGA, CodecStGain, PCM, and audio loopbacks.
Earphone
MicrophoneMIC1P
MIC1N
MIC2P
MIC2N
EAR1ON
EAR1OP
HS/HPH_L
AUXON / Line_R
-+
+ --
+
70mW max.*
21.6 mW max.*
Codec Rx
Codec Tx
A/D
-+HPH_R
D/A
D/A
AUXOP / Line_L + --+
2.30 mW max.*
Mux+
SumOut
HPF &SLOPE X
CODEC_TX_GAINTX_HPF_DIS_N
TX_SLOPE_FILT_DIS_N
CODEC_ST_GAIN X
HPF
RX_HPF_DIS_N
Right Data In
+ Left Data In
PCM Interface
PC
M_
LOO
PB
AC
K
CODEC Audio DSP
Line_L_IP
AUXIP
AUXIN Mux
HPF &SLOPE
A/D
X
CODEC_RX_GAIN
HPF
RX_HPF_DIS_N
X
CODEC_RX_GAIN
0dB or+24dB
MIC_AMP1
X
CODEC_TX_GAIN
MIC_AMP2
-6dB to +25.5dB1.5dB steps
0dB+24dB
MIC_AMP1
MIC_AMP2
-6dB to +25.5dB1.5dB steps
Left Data Out
Right Data Out
TX_HPF_DIS_N
TX_SLOPE_FILT_DIS_N
Line_R_IP
Line_L_IN
Line_R_IN
0.58 mW max.*-+
AUX_OUT
Capless Driver
PCMIF
PCMIF
X
13K QCELP
HR/FR/EFRAMR
Encoder
TX_VOLUME
RX_VOLUME
nsSwitch TxPcmFilt
RxPcmFiltecSwitchecMode
DTMFGeneration
DTMFDetection
DTMF_RX_GAIN
DTMF_TX_GAIN
ESECor
AEC
Encoder
Decoder
Tx FIR
NES(DFMonly)
AAGC
AUDIOLOOPBACK++
** Gain = 20LOG (Value/16384 )Range is -84dB to +12dB
– Intended to remove continuous sounds that have no value in being transmitted to the far-end user – automobile noise (engine noise, tire noise) and continuous tones (whistles, horns)
– On Tx link only
– Typically turned on for most phone modes. Does not require special tuning.
– Possible problems: may not let tones or other test audio be transmitted, may cause unexpected volume variations if the test lab has a changing acoustic environment, should be one of the first things to disable if unexplained volume issues occur with audio.
– Intended to make sound volume more uniform on Tx and Rx sides (independently controlled Tx and Rx), and remove unnecessary low-level noise
– By using static gain feature, can give greater control of gains.
– Possible problems fixed by Audio AGC: large variations in sound levels and inability to hear soft sounds
– This issue is discussed in greater detail later in this presentation.
• Audio front-end features – comfort noise– Intended for use when muting the audio on the TX path
– On Tx path only
– When muting the microphone, a white noise of equivalent level to the measured background noise will play, instead of just pure silence.
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Audio Connections
MSM7200A audio connections fall into seven categories:
• Microphone inputs
• Auxiliary inputs
• Line inputs
• Earphone outputs
• Stereo headphone outputs
• Auxiliary outputs
• Line outputs
MSM7200A
MIC1
MIC2
AUX
Line left
Line right
Earphone
Stereo headphones
AUX
Line left
Line right
Mul t
i pl e
xer c
ircui
ts
Left channel gain
Right channel gain
AD
CA
DC
Tx paths
Capless driver
Mul
t iple
xerc
i rcu i
ts
Rx paths
DA
CD
AC
to R audio DSP ckts
to L audio DSP ckts
from L audio DSP ckts
from R audio DSP ckts
MIC1PA 7
LINE_L_I_ NB 6
LINE_L_I_ PB 5
LINE_R_I_ NA 6
LINE_R_I_ PA 5
AUXINE 7
AUXIPD 7
MIC2NE 6
MIC2PD 6
MIC1NB 7
MICBIASE 5
EAR1 OPA 9
EAR1 ONB 8
HPH_RG 9
HPH_ VREFG 7
HPH_LH 9
AUX_ OUTG 8
LINE_OPB 8
LINE_ONA 8
CCOMPE 4
MSM7200A
MIC1
MIC2
AUX
Line left
Line right
Earphone
Stereo headphones
AUX
Line left
Line right
Mul t
i pl e
xer c
ircui
ts
Left channel
gain
Right channel gain
AD
CA
DC
Tx paths
Capless driver
Mul
t iple
xerc
i rcu i
ts
Rx paths
DA
CD
AC
to R audio DSP ckts
to L audio DSP ckts
from L audio DSP ckts
from R audio DSP ckts
MIC1PA
MSM7200A
MIC1
MIC2
AUX
Line left
Line right
Earphone
Stereo headphones
AUX
Line left
Line right
Mul t
i pl e
xer c
ircui
ts
Left channel
gain
Right channel
gain
AD
CA
DC
Tx paths
Capless driver
Mul
t iple
xerc
i rcu i
ts
Rx paths
DA
CD
AC
to R audio DSP ckts
to L audio DSP ckts
from L audio DSP ckts
from R audio DSP ckts
MIC1PA 7
LINE_L_I_ NB 6
LINE_L_I_ PB 5
LINE_R_I_ NA 6
LINE_R_I_ PA 5
AUXINE 7
AUXIPD 7
MIC2NE 6
MIC2PD 6
MIC1NB 7
MICBIASE 5
EAR1 OPA 9
EAR1 ONB 8
HPH_RG 9
HPH _VREFG 7
HPH_LH 9
AUX_ OUTG 8
LINE_OPB 8
LINE _ONA 8
CCOMPE 4
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Audio Pin Connections (1 of 2)
analogIB6LINE_L_I_N
Left channel stereo function with three options
analogIB5LINE_L_I_P
analogIA6LINE_R_I_N
Options: 1) Line in; 2) Microphone; 3) Summing function to Rx
Right channel stereo function with three options
analogIA5LINE_R_I_P
Line inputs
Auxiliary differential negative (-) input
analogIE7AUXIN
Auxiliary differential positive (+) input
analogID7AUXIP
Auxiliary input
No decoupling capMicrophone bias supplyanalogBE5MICBIAS
Microphone #2 differential negative (-) input
analogIE6MIC2N
Microphone #2 differential positive (+) input
analogID6MIC2P
Microphone #1 differential negative (-) input
analogIB7MIC1N
Microphone #1 differential positive (+) input
analogIA7MIC1P
Microphone inputs
CommentsDescriptionVoltageI/OPin #Signal name
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Audio Pin Connections (2 of 2)
Earphone outputs
CommentsDescriptionVoltageI/OPin #Signal name
0.1 µF recommendedExternal decoupling cap for CODEC voltage reference
analogIE4CCOMP
Other audio-related pin
Negative (-) line (LINE_OUT_R) output or stereo right channel output
analogOA8LINE_ON
Positive (+) line (LINE_OUT_L) output or stereo left channel output
analogOB8LINE_OP
Line outputs
Single-endedAuxiliary output to carkit, PMIC, or external speaker
analogOG8AUX_OUT
Auxiliary output
Capless modeHeadphone common mode voltage
analogIG7HPH_VREF
Stereo headphone left output or positive (+) headphone out
analogOH9HPH_L
Stereo headphone right output or negative (-) headphone out
analogOG9HPH_R
Stereo headphone outputs
Earphone differential negative (-) output
analogOB8EAR1ON
Earphone differential positive (+) output
analogOA9EAR1OP
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Audio Summary
Mono/stereoRx CODEC DAC path
Internal gain: +25.5 to –6 dB, 1.5 dB stepsTx MIC_AMP2 gain
Internal gain: 0 dB or +24 dBTx MIC_AMP1 gain
+11.5 to –24.5 dB; 3 dB stepsAUX PGA path gain settings
Line out and AUX_OUTLine out and AUX_OUT
In standby and sleep modes via an interrupt
Headset switch detect (HSSD)
Cap-coupled and capless modesHPH driver
16 bitTx ADC max resolution
48 kHzRx max sampling rate
Mono/stereoTx CODEC ADC path
Five pairsTx differential inputs
MSM7200A ICItem
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PCM Interface
• Two PCM interface modes are supported:– Auxiliary PCM running at 128 kHz (default)– Primary PCM running at 2.048 MHz– API to call is snd_set_device. – Pins used for AUX_PCM can be used to interface with an external stereo DAC
(SDAC – details on next page).– Refer to Application Note: External PCM Interface (80-V7143-1) for more PCM
interface details and implementation.
• Auxiliary PCM– Communicates with an external codec. – 8-bit μ-law and 8-bit A-law codecs are supported.– Uses standard long-sync timing and a 128 kHz clock.
• Primary PCM– Supports 16-bit linear, 8-bit μ-law, and 8-bit A-law codecs.– 2.048 MHz PCM data and short sync timing– Can be configured and controlled two ways:
» Direct register access (CODEC_CTL register)» aDSP CODEC configuration commands (the preferred method)
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Interfacing with External Stereo DAC
• The MSM7200A pins used for AUX_PCM can also be used to interface with external stereo DAC (SDAC) to play stereo sound or music (MP3 or MIDI, for example).
– I2S used to transfer audio data for this interface. Currently can only be used as output mode to SDAC.
• The following pins are used:– SDAC_DOUT: Serial PCM data stream for both channels are output from
the MSM device through this pin.– SDAC_L_R_N: This signal specifies the present data stream’s intended
stereo channel.» Left channel = 1» Right channel = 0
– SDAC_CLK: Bit clock generated by the MSM7200A IC– SDAC_MCLK: An optional clock output from the MSM device to the external
– Headset switch detect (HSSD) – HSSD using capless driver
MSM7200A
MSM7200A
Note: MIC inputs must be in single-ended mode in order to enable HSSD.
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External Analog Interface (5 of 7)
• Line input to output audio
MSM7200A
Note: Analog audio signal can be routed to any output amplifiers (EAR1O, EAR20, HPH, AUXO); not limited to just HPH.
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External Analog Interface (6 of 7)
• Interface to external speaker amplifier (PM7540 IC)
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External Analog Interface (7 of 7)
• Interface to external speaker amplifier (PM7540 IC)– PM7540 input: Stereo single-ended/differential or mono differential
» Stereo single-ended inputs can be summed together and output in mono.
– PM7540 output: Stereo differential delivering 500 mW to each 8-ohm speaker
» Can also be configured as mono or dual mono sound.
– Interface recommendations» Set MSM digital gains and PMIC speaker analog gain appropriately to ensure
speaker amps do not saturate.» Set analog high-pass filter corner according to the resonant frequency of the
fair-field speaker transducer. » Corner can be changed by either changing capacitor or by using PM7540 IC’s
NEW variable input impedance feature. » For more information, see PM7540 Power Management IC User Guide
(80-VD691-3).
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MSM7200A Device InterfacesJTAG and ETM
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MSM7200A Debug and Test
• MSM7200A IC provides two debugging methods:– JTAG
– ETM
• Joint Test Action Group (JTAG)– Aids in board-level testing and debugging.
– The JTAG interface allow test instructions and data to be shifted into the MSM device, and the test results to be read out in a serial format.
• Embedded Trace Macrocell (ETM)– Enables tracing while running ARM processors at high speed.
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JTAG Debug and Test
• MSM7200A IC provides two separate JTAG ports (primary and auxiliary ports):
– The primary JTAG port is a dedicated port.– The auxiliary JTAG port is available through configurable GPIO pins.
• These JTAG pins communicate with the ARM9 and ARM11 cores, depending upon the mode setting.
– The JTAG mode is selected by setting the MODE[3:0] pins.
• MSM7200A JTAG features– Provides JTAG access to both ARM9 and ARM11 microprocessors.
» Using daisy-chained ARM9+ARM11 mode on the primary JTAG port» Using two separate JTAG ports with ARM9 on the primary and ARM11 on the auxiliary JTAG
port
• WDOG_EN can expire during JTAG operation.– Disable by grounding pin or through software.
• Refer to Application Note: JTAG Setup Procedure on MSM7500/MSM7200(80-V9038-13) for more information on how to use the JTAG interface with the MSM7200A device.
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JTAG Connectivity Modes
Reserved0101 to 1111
Boundary scan mode**0100
Reserved0011
Reserved0010
TLMM_INT_JTAG_CTL register specifies the internal version of the MODE pin value for the Primary JTAG port:
TLMM_INT_JTAG_CTL settings:
0000 : ARM9 only
0001 : ARM9+ARM11 daisy-chained
0010 : Reserved
0011 : Reserved
1001 : ARM9+ARM11+rtck daisy-chained
0001
Native, ARM9 on Primary JTAG, ARM11 on AUX JTAG0000
Phone mode and JTAG selectionMode pins [3:0]
The four mode pins are AA7, AB8, AD7, and AE7 (MSB to LSB).
* ARM9 must enable ARM11 through software to enable daisy-chain mode.
** Separate TAP controller is required for the MSM in boundary-scan mode.
Note: The modes listed above have not been fully tested.
• ETM consists of two parts:– Trace port: This port broadcasts trace information (instruction or data trace).
– Triggering facilities: These control the ETM to filter and control trace operations.
• ETM architecture is different for ARM9 compared to ARM11.– ETM is designed to be connected directly to the ARM core it is tracing.
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ETM9 Architecture
• ETM9 architecture has trace port that includes four signals:– PIPESTAT (2:0): Pipeline status pins– TRACEPKT: Trace packet port (4/8/16 pins)– TRACESYNC: Trace packet synchronization pin– TRACECLK: Clock signal
ARM9 processor
ETM9
Pipeline status
generation
Trace packet capture
FIFO
Trigger logic
TRACECLK
PIPESTAT [2:0]
TRACEPKT[n-1:0]
TRACESYNC
n
3
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ETM11 Architecture
• Major differences between ETM11 and ETM9 are:– ETM11 removes the PIPESTAT signals.
– ETM11 trace-port protocol enables the trace port and the core to run at different speeds.
– Trace data is collected on both clock edges.
ARM11 processor
ETM11
P-header generation
Trace packet
generation
FIFO
Trigger logic
TRACECLK
TRACEDATA[n-1:0]n
TRACECTL
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ETM9 Modes
• MSM7200A IC supports several different ETM9 configurations and modes.
• The configuration options supported by MSM7200A ETM9 include:– 16-bit normal mode: ETM pins are toggled at ARM9’s maximum
clock rate.» 21 pins are needed.» One trace port analyzer is needed.
– 8-bit deMUXed mode: This mode is used when at-speed core operation is required and 16-bit mode is not available due to I/O speed limitations.
» 25 pins are needed.» ARM9/ETM9 speed: 192 MHz» Pin speed: 192/2 MHz» Two trace port analyzers are needed.
– Both ETM9 modes listed above are still being verified for maximum supported clock rate.
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8-bit deMUXed ETM9 Mode
TRACEPKT[7:0] DEMUX_TPA1_TRACEPKT[7:0]
DEMUX_TPA2_TRACEPKT[7:0]
PIPESTAT[2:0] DEMUX_TPA1_PIPESTAT[2:0]
DEMUX_TPA2_PIPESTAT[2:0]
TRACESYNC DEMUX_TPA1_TRACESYNC
DEMUX_TPA2_TRACESYNC
DEMUX LOGIC
DEMUX LOGIC
DEMUX LOGIC
Signals @ ARM/ETM clock frequency
ETM
Signals @ half the ARM/ETM clock frequency
• This mode is used only when at-speed core operation is required and 16-bit mode is unavailable due to I/O speed limitations.
• Number of pins is doubled, so 8-bit trace is used instead of 16-bit trace.
• 25 pins are required.
• Requires two trace port analyzers.
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ETM Pin Connections
P3OAA19ETM_GPIO_IRQGPIO[28]
P3IAG18ETM_KEYSENSE_IRQGPIO[21]
P3IAE18ETM_GPIO_CS_NGPIO[24]
ETM9 trace sync … or …Dual port ETM trace clock
P3OAH26ETM9_TRACESYNCBDP_ETM_TRACECLK_BGPIO[82]
P3OAB17ETM9_PIPESTATB2GPIO[18]
P3OAD17ETM9_PIPESTATB1GPIO[17]
Reserved for demux mode; 133 MHz clock rate; 10 pF max load capacitor
P3OAA17ETM9_PIPESTATB0GPIO[16]
ETM9 only – pipestat2P3OAD19ETM9_PIPESTAT2GPIO[26]
ETM9 pipestat1 … or …ETM11 trace control
P3OAE19ETM9_PIPESTAT1ETM11_TRACECTLGPIO[27]
ETM9 pipestat0 … or …ETM11 trace data0
P3OAB20ETM9_PIPESTAT0ETM11_TRACEDATA0GPIO[29]
Trace sync in ETM9P3OAH20ETM9_TRACESYNCGPIO[31]
133 MHz clock rate; 10 pF max load capacitor
ETM trace clockP3OAB19ETM_TRACECLKGPIO[30]
133 MHz clock rate; 10 pF max load capacitor
16-bit ETM trace data; DATA[15] is the MSB, DATA[0] is the LSB.
P3OAE17ETM_TRACEDATA[15:0]
CommentsDescriptionVoltageI/OPin #Signal name liu.h
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ETM GPIO Emulation
• During ETM mode, MSM7200A GPIO [16:42] and GPIO [82] are used for ETM signals.
• When these GPIO pins are used in ETM mode, the alternate functionality is lost.
• The displaced functionality behind the ETM pins that functionally used the GPIO is replicated off-chip by FPGAs.
• These GPIOs are emulated using the EBI2 memory-mapped interface.