Q16 051-6338-C.bak

Page 1

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPDENG

DATE

APPDCK

ECNZONEREV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTIOND

SIZE

APPLICABLENOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OFSHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PARTII NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

12345678

12345678

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD

QTY DESCRIPTIONPART#

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

DRAWING

TABLE_5_ITEM

CPU CORE VOLTAGE POWER SUPPLY

SOUND/LEFT USB/BLUETOOTH, SERIAL DEBUG

TITLE PAGE AND CONTENTS

PCB NOTES AND HOLES

SYSTEM BLOCK DIAGRAM 23

26

INTREPID MEMORY INTERFACE / BOOT ROM

GIGABIT ETHERNET INTERFACE

USB_MODEM

ATI_MEMIO_HI

OPTICAL DRIVE

41

38

External TMDS (DVI Transmitter SIL1162)M10 AGP INTERFACE & SPREAD SPECTRUM SUPPORT

20

18

19

16

15

14

13

12

400PIN STACKED DDR SODIMM CONNECTOR

INTREPID AGP 4X/PCI

DDR MEMORY MUXES

INTREPID POWER RAILS/1.5V LDO

CARDBUS INTERFACE (PCI1510)

USB 2.0 INTERFACE (uPD720101)

SIGNAL CONSTRAINTS (2 OF 4) - CPU

PAGE CONTENTS PAGE

M10 LVDS/TMDS/GPIO & GPU VCORE

INTREPID ENET/FW/UATA/EIDE INTERFACES

INTREPID DECOUPLING

INTREPID MAXBUS AND BOOT STRAPS

CPU PLL AND CONFIGURATION STRAPS

POWER BLOCK DIAGRAM

MPC7447 MAXBUS INTERFACE

SSCG

5V_HD_LOGIC

BBANGNO_BBANG

3V_HD_LOGIC

INT_2_5V_HOT

ATI_MEMIO_LO

SOFT_MODEM

INT_2_5V_COLD

GPU_PWRMSR

GPU_SS

BOM OPTIONS (IN COMMON PARTS)

STUFF

22

INTERNAL CONNECTORS - AIRPORT, HARD DRIVE,

NO_SSCG

32

2

25

39

27

40

3

COMPONENT LOCATIONS (2 OF 2)

COMPONENT LOCATIONS (1 OF 2)

REVISION HISTORY

SIGNAL LOCATIONS

43

42

PMU

37

36

33

34

30

1

4

5

6

8

7

10

9

17FUNCTIONAL TESTPOINTS

35

21 M10 POWER

SIGNAL CONSTRAINTS (4 OF 4) - POWER NETS

28

24

LVDS

SIGNAL CONSTRAINTS (1 OF 4) - DDR MEM/CLK

FIREWIRE PHY

29

NO STUFF

31 PBUS SUPPLY / PMU SUPPLY / BACKUP BATTERY

1_8V_MAXBUS 1_5V_MAXBUS

11

FAN CONTROLLER, USB MODEM/SOFT MODEM,

MPC7447 DATA / NC PINS / BOOTBANGER

BATTERY CHARGER AND CONNECTOR

CONTENTS

3.3V / 5V SYSTEM POWER SUPPLY

FIREWIRE PORTS

INTREPID GPIOS/SERIAL/USB INTERFACES/SSCG

VGA_BUFFER_RES

EXT_TMDS

INT_TMDS

VIDEO CONNECTORS - INVERTER, DVI, S-VIDEO,

KBD,TPAD,HALL EFFECT,PWR BUTTON,LMU/SENSOR

1.5V/ 1.8V / 2.5V SYSTEM POWER SUPPLIES

SIGNAL CONSTRAINTS (3 OF 4) - DIGITAL/DIFF

051-633840

?12/05/0202

1

ENGINEERING RELEASED248015

C

SCHEM,MLB,PB15"DMS630-47211065-4479 DMS3SELPRTS,MLB,PB15,BST

1 PCB1820-1441 PCBF,MLB,PB15

1 DMS1065-3951 DMS630-4285&DMS630-4721CMNPRTS,MLB,PB15

051-6338 1 SCH1SCHEM,MLB,PB15

SCHEM,MLB,PB15

DMS630-4285065-3952 DMS21 SELPRTS,MLB,PB15,BTR

Fri Jan 23 20:30:40 2004

Page 2

DSIZE

OFSHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

12345678

12345678

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.SCALE

NONE

TMDS

(VIA SIL1162)

Connector

J4

ConnectorP.22

ConnectorP.22P.22

2:1 DDR MUXES

64BITS167MHZ

MEMORY BUS2.5V

LVDS

EDID (I2C)

RGB

DDC

J22

DVI-I

PCI

MEMORY

U17

RIGHT USB

(VIA LIO)LEFT USB

(INTERNAL MEM)

EHCI HCNEC USB2.0

P.24

DC-In

NOT USED

NOT USED

NOT USED

BOOT ROM

(MPC7447)

P.25

3.3V/5V16/32 BITS33MHZ

I2C

PMU

167MHZ1.8VMAXBUS

32BIT ADDRESS64BIT DATA

NOT USED

EIDE

UIDE

1394 OHCI3.3V

50MHZ8BIT TX/RX

P.24

P.24

@ 400MHZ

2 DATA PAIRS

P.27PHY

FW - BFW - A

125MHZ

8BIT RX

8BIT TX

G/MII3.3V

10/100/1000

P.26

P.26

PHY

66MHZ

1.5V/3.3V

AGP BUS

32BITS

ConnectorP.14SCCA

I2C

P.25

Connector

Connector

Power Supply& Charger

ConnectorULTRA ATA/100

P.18

P.22

S-VIDEO

LCD PanelConnector

P.19-21

4X AGP

CPUP.5-6

P.7

PCI BUS32BITS33MHZ3.3V

CardBus

64MB CH. B

CH. A

MEMORY MEMORY

I2S

CPU PLLConfig

USB PORT E

USB PORT D

10/100/1000ETHERNET FIREWIRE

SO-DIMM Connector

DDR SDRAM DIMM 0

DDR SDRAM DIMM 1

DDR MEMORY

UATA 100

33MHZ

64BITS

CARDSLOT

VIA/PMU

SYSTEM BLOCK DIAGRAM

FireWire

USB PORT F

USB PORT C

P.25

ConnectorBattery

SMBUS

3.3V

INTREPID

400 MB/S

APOLLO

Ethernet

Connector

USB PORT B

USB PORT A

@ 200MHz

ConnectorP.28

INTREPID

P.28

P.13 P.13P.13

P.14

P.14

P.14

P.14

P.14

P.14

P.8

P.9

P.10

J25

P.11

P.13 P.14 P.13P.14

P.14

P.12

P.12

P.30

U28

P.29

P.9

Inverter

COMPOSITE

S-Video

P.30-34 P.30

U8

P.17

P.25

P.25

FanI2CI2S

ConnectorLIO/Audio

P.25

NOT USED

EIDEP.13

P.25

MAXBUS

(INTERNAL MEM)

Serial Debug

TI PCI1510

ControllerConnector1M X 8

(VIA STATLER)

CH. D

(INTERNAL MEM)

MEMORY

ATIM10

P.12

(INTERNAL MEM)

BlueTooth (LIO)

4 DATA PAIRS

Ethernet

J23 J24

U43U36

J20

J13

J12

J3

J28

U11

J26 J27

J6

U47

J3

J17

J21J14

U16/U18/U28/U27U56

J15

J3

U51

J5

ConnectorP.18

CARDBUS

PMU

AIRPORT

CH. C

TRACKPAD

J10

P.23

SERIAL5V

Connector

Connector

LED

J8

P.23

SLEEP

U53/J1/J18

Circuit

BOOTROM

OPTICAL DRIVE

ConnectorConnector

J11

ConnectorP.23

Keyboard

I2C

2 DATA PAIRS

RUX Board

LMU LUX Board

P.23

P.23

J2

J19

Modem/SW ModemConnector

051-6338

2 40C

Page 3

DSIZE

OFSHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

12345678

12345678

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.SCALE

NONE

BACKUP

SLEEP: D3COLD(+1.385V)

+1.2V(LTC1778) GPU_VCORE

CPU_VCORE

+3V_SLEEP

1_5V_2_5V_OK

+3V_MAIN

+2_5V_SLEEP

SLEEP_L_LS5

~2.23MS

SHUTDOWN: STOPPED

RUN: RUNNING

RUN/SSSLEEP: RUNNING

DC/DC(LTC3411)

SHUTDOWN: STOPPEDSLEEP: STOPPED

RUN: RUNNING

(MAX1772)

FEED-IN PATH

NO INRUSH PROTECTION

BATTERYCHARGER

PG 30

WHEN ONLY BATTERY IS CONNECTED

+4_6V_BU

SHUTDOWN: RUNNING

AC: 12.8V

REGULATOR(LTC1625)

MAIN 2.5V/1.5V

SHUTDOWN: STOPPED +PBUS

INTREPID CORE

SHUT-DOWNCHARGER INPUT

PG 20

PG 33

INTERNAL 1.2UA CURRENT SOURCETURNS ON AS LOW AS 0.8V/TYP 1.5V

PG 34

PG 34

PG 32

PG 31

PG 31

PG 30

PG 30

PG 30

PG 31

PG 31

NO AC: BATTERY VOLTAGE

VCC

POWER SYSTEM ARCHITECTURE

MAP31 DDR I/O MAP31 DDR CORE

AND PREVENTS +PBUS AND +24V_PBUS FROM DROPPING BELOW 6V

BACKUP BATTERY CIRCUIT CHARGES OFF +PBUS

+PBUS

+PBUS

+PBUS

BATTERY VOLTAGE

RUN/SS

STARTS ~4.25MSEC AFTER DCDC_EN_L BECOMES LOWRC AT 1M*0.1UF @ 24V

STARTS 2.0MSEC AFTER DCDC_EN_L BECOMES LOWRC AT 1M*0.047UF @ 24V

INTERNAL ZENER CLAMP TO 6V<100UA ALLOWEDTURNS ON AT >1VRUN/SS - 5V

<100UA ALLOWED

MAIN 3V/5V

(LTC3707)DC/DC

TURNS ON AT >1V

VCC

DCDC_EN_LAFTER PMU IS UP AND RUNNINGDCDC_EN_L WILL PULL ON1/ON2LOW IN SHUTDOWN

+5V_MAIN

+1.8V_MAIN

+5V_MAIN

VCC

1_5V_2_5V_OK

+BATT

+BATT

+24V_PBUS

+24V_PBUS

NO INRUSH PROTECTION

TURNS ON OUTPUT @ 2.4V

RUN: RUNNING

SHUTDOWN: STOPPED

RUN/SS - 3V

SLEEP: RUNNINGRUN: RUNNING

24V IS OUTPUT ONLY FROM

BATTERY

BACKUP BATTERY

1V20_REF

+

-

& BOOST OUTPUT

POWER BLOCK DIAGRAM

(UNTIL DRAINED)

AC

IN

ADAPTERLIMITERINRUSH

>~13.44V TURNS-ON

<~13.44V SHUTS-OFF

BUCK

RUN: RUNNING

+3.3V_MAIN

STBYMD

+3V_PMULDO +3V_PMU

14V_PBUS

14V_PBUS

+5V_MAIN

WHEN ONLY BATTERY IS CONNECTED

14V CHARGES BACKUP BATTERY

HOLDS BOTH RUN/SS AT GNDWHEN IT’S CONNECTED TO GND

WHEN IT’S OPENTURNS CONTROL TO RUN/SS

INVERTER

BACKLIGHT

DC/DC

(MAX1715)

PGOOD 3V_5V_OK

PGOOD

1625 NOT RUNNINGON1/ON2

+1.5V_MAIN

+2.5V_MAINDDR POWER

AGP I/O

MAXBUS

SLEEP: STOPPEDSHUTDOWN: STOPPED

RUN: RUNNING

DC/DC(MAX1717)

+5V_MAIN

SHDNVCC

SLEEPDCDC_EN

MAXBUSSEQUENCING

+5V_MAIN

DC/DC

EXT_VCCVCC

D3_COLDSLEEP

DCDC_EN

HOWEVER, 5V SHOULD TURN ON ~2.23MS AFTER

RC CHARGING AT INT_VCC (5V)

DCDC_EN_L OR PMU_POWERUP_LBECOMES ’1’; MUCH LESS THAN THE

+5V_MAIN TURNS ON1_5V_2_5V_OK WILL NOT PULL LOW UNTIL

D3_HOT

D3_HOT

1_5V_2_5V_OK

DCDC_EN_L

SEQUENCING

GPU_VCORE

~5.88MS TO START SWITCHER1M & 0.1UF @14V, IT TAKES

DCDC_EN_LDCDC_EN

+5V_MAIN+5V_SLEEP

2.4V - ??? MS3V_5V_OK

SLEEP

??? MS+2_5V_MAIN

??? MS+1_5V_MAIN+1_5V_SLEEP

1_5V_2_5V_OK(MAX1715 OUTPUT)

(AT LTC1778 RUN/SS)

GPU_VCORE(D3HOT)

GPU_VCORE(D3COLD)

~8.2MS

~7.36MS

SLEEPRUNSHUT-DOWN RUN

3S 2P 18650 CELLS

SLEEP: RUNNING

+5V_MAIN

INTERNAL ZENER CLAMP TO 6V

C

3 40051-6338

Page 4

DSIZE

OFSHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

12345678

12345678

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.SCALE

NONE

GROUND VIAS

PCB SPECSTHICKNESS : 1.2 MM / 0.047 IN

PREPREG (3 MIL)

PREPREG (3 MIL)

CORE (3 MIL)

CORE (3 MIL)

PREPREG (3 MIL)

PREPREG (3 MIL)

PREPREG (5 MIL)

PREPREG (5 MIL)

CORE (5 MIL)CUT POWER PLANE (1 OZ)

CUT POWER PLANE (1 OZ)

SIGNAL (1/2 OZ + COPPER PLATING)

SIGNAL (1/2 OZ + COPPER PLATING)

BOARD HOLES

BOARD INFORMATION

SEE PCB CAD FILES FOR MORE SPECIFIC INFO.

IMPEDANCE : 50 OHMS +/- 10%

1/2 OZ CU THICKNESS: 0.7 MILS

DIELECTRIC: FR-4LAYER COUNT: 10

BOARD STACK-UP AND CONSTRUCTION

SIGNAL TRACE WIDTH: 4 MILS

PREPREG THICKNESS: 2-3 MILSSIGNAL TRACE SPACING: 4 MILS

I/O AREA

1394

1

4

5

7

6

3

2

8

9

10

GROUND (1/2 OZ)

SIGNAL (1/2 OZ)

SIGNAL (1/2 OZ)

1-8-1 BLIND MICROVIA/20R10 BURIED VIA/20R10 TH VIA

SIGNAL (1/2 OZ)

GROUND (1/2 OZ)

SIGNAL (1/2 OZ)

1.0 OZ CU THICKNESS: 1.4 MILS LWR CPU

UPPER RT GPU

LEFT CPU

LWR RT GPU

INVERTER

DVI

DVI

BATT. CHRGR

CHASSIS MOUNTS

ASICS HEATSINK MOUNTS

MECH. HOLES

1

ZT70HOLE-VIA-20R10

1

ZT9HOLE-VIA-20R10

1

ZT2HOLE-VIA-20R10

1

ZT73HOLE-VIA-20R10

1

ZT75HOLE-VIA-20R10

1

ZT63HOLE-VIA-20R10

1

ZT77HOLE-VIA-20R10

1

ZT66HOLE-VIA-20R10

1

ZT65HOLE-VIA-20R10

1

ZT62HOLE-VIA-20R10

1

ZT25HOLE-VIA-20R10

1

ZT24HOLE-VIA-20R10

1

ZT19HOLE-VIA-20R10

1

ZT67HOLE-VIA-20R10

1

ZT37HOLE-VIA-20R10

1

ZT29HOLE-VIA-20R10

1

ZT31HOLE-VIA-20R10

1

ZT1HOLE-VIA-20R10

1

ZT12HOLE-VIA-20R10

1

ZT14HOLE-VIA-20R10

1

ZT27HOLE-VIA-20R10

1

ZT26HOLE-VIA-20R10

1

ZT13HOLE-VIA-20R10

1

ZT30HOLE-VIA-20R10

1

ZT33HOLE-VIA-20R10

1

ZT18HOLE-VIA-20R10

3

2

1

SH1SHLD-SM

OG-503040

CHGND5

1

ZT7HOLE-VIA-20R10

1

ZT21HOLE-VIA-20R10

1

ZT59HOLE-VIA-20R10

1

ZT58HOLE-VIA-20R10

1

ZT85HOLE-VIA-20R10

1

ZT86HOLE-VIA-20R10

1

ZT16HOLE-VIA-20R10

1

ZT74HOLE-VIA-20R10

1

ZT36HOLE-VIA-20R10

1

ZT23HOLE-VIA-20R10

1

ZT42HOLE-VIA-20R10

CHGND2

CHGND1

CHGND3

1

ZT76HOLE-VIA-20R10

1

ZT41HOLE-VIA-20R10

1

ZT40HOLE-VIA-20R10

1

ZT39HOLE-VIA-20R10

1

ZT38HOLE-VIA-20R10

1

ZT61HOLE-VIA-20R10

1

ZT64HOLE-VIA-20R10

1

ZT68HOLE-VIA-20R10

1

ZT69HOLE-VIA-20R10

1

ZT72HOLE-VIA-20R10

1

ZT28HOLE-VIA-20R10

1

ZT46HOLE-VIA-20R10

1

ZT71HOLE-VIA-20R10

1

ZT78HOLE-VIA-20R10

1

ZT80HOLE-VIA-20R10

1

ZT51HOLE-VIA-20R10

1

ZT50HOLE-VIA-20R10

1

ZT52HOLE-VIA-20R10

1

ZT53HOLE-VIA-20R10

1

ZT57HOLE-VIA-20R10

1

ZT82HOLE-VIA-20R10

1

ZT60HOLE-VIA-20R10

1

ZT22HOLE-VIA-20R10

1

ZT17HOLE-VIA-20R10

1

ZT35HOLE-VIA-20R10

1

ZT45HOLE-VIA-20R10

1

ZT79HOLE-VIA-20R10

1

ZT83HOLE-VIA-20R10

1

ZT81HOLE-VIA-20R10

1

ZT49HOLE-VIA-20R10

1

ZT47HOLE-VIA-20R10

1

ZT48HOLE-VIA-20R10

1

ZT54HOLE-VIA-20R10

1

ZT55HOLE-VIA-20R10

1

ZT56HOLE-VIA-20R10

1

ZT5HOLE-VIA-20R10

1

ZT84HOLE-VIA-20R10

1

ZT15HOLE-VIA-20R10

1

ZT44HOLE-VIA-20R10

1

ZT4HOLE-VIA-20R10

1

ZT8HOLE-VIA-20R10

1

ZT6HOLE-VIA-20R10

1

ZT3HOLE-VIA-20R10

1

ZT32HOLE-VIA-20R10

1

ZT10HOLE-VIA-20R10

1

ZT34HOLE-VIA-20R10

1

ZT11HOLE-VIA-20R10

1

ZT20HOLE-VIA-20R10

1

ZT43HOLE-VIA-20R10

C

404051-6338

ZT10_SPNNO_TEST=TRUE

ZT302_SPNNO_TEST=TRUE

NO_TEST=TRUEZT301_SPN

Page 5

(1 OF 3)

TEST4TEST3TEST2TEST1TEST0

EXT_QUAL

TBEN

L2TSTCLKL1TSTCLK

TCKTMSTDOTDI

DTI0DTI1DTI2DTI3

PLL_EXTPLLCFG3PLLCFG2PLLCFG1PLLCFG0CLKOUTSYSCLK

BVSEL

TT3TT2TT1

TSIZ0

TSIZ2TSIZ1

TT4

TT0

A33A34A35

AP0

AP3AP2

AP4

AP1

A25A24A23

A26A27A28A29A30A31A32

A13A14A15A16A17A18A19A20A21A22

A12

A10A9A8A7A6

A3A4A5

A11

A2

A0A1

OVDDVDD

GND

AVDD

BR*BG*

TS*

TRST*LSSDMODE*

TA*

TEA*

QREQ*QACK*

CKSTP_IN*CKSTP_OUT*

INT*SMI*MCP*

SRESET*HRESET*

PMON_IN*PMON_OUT*

BMODE0* BMODE1*

TBST*

GBL*WT*CI*AACK*ARTRY*SHD0*

HIT*SHD1*

DRDY*DBG*

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTIONTABLE_5_HEAD

PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)

DSIZE

OFSHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

12345678

12345678

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.SCALE

NONE

MORE 0805 10UF CAPS ON VCORE POWER SUPPLY PAGE (PG 32)

CPU_VCORE DECOUPLING NETWORK

NC

470OHM FOR BOOT BANGER

NC

NC

NC

NC

NC

NC

470OHM FOR BOOT BANGER

470OHM FOR BOOT BANGER

MPC7447 PULL-UPS

MPC7447 MAXBUS

CPU_OVDD DECOUPLING NETWORK

MPC7447

CPU INTERNAL PLL FILTERING21

R4610K

5%1/16WMF402

21

R13

5%1/16WMF402

10K

21

R20

402MF

1/16W5%

10K

21

R32470

5%1/16WMF402

21

R11

5%1/16WMF402

10K

2

1R10NO_BBANG

402

2005%1/16WMF

21

R4

402MF

1/16W

10K

5%

21

R71K

1/16WMF402

5%

21

R24

1/16WMF402

5%

10K

21

R3410K

1/16WMF402

5%

2

1 C890.1uF20%

CERM402

10V

2

1 C730.1uF

402

10V20%

CERM

2

1 C180.1uF20%

CERM402

10V

2

1 C200.1uF10V

402CERM

20%

2

1 C750.1uF

CERM

20%

402

10V2

1 C90.1uF

CERM

20%10V

402

2

1 C490.1uF

402

10VCERM

20%

2

1 C460.1uF

CERM402

10V20%

2

1 C300.1uF20%

CERM10V

402

2

1 C560.1uF20%10V

402CERM

2

1 C450.1uF20%

CERM10V

402

2

1 C480.1uF

CERM402

10V20%

2

1 C440.1uF10V

402CERM

20%

2

1 C860.1uF

402

10V20%

CERM

2

1 C880.1uF10V

402CERM

20%

2

1 C100.1uF

402

10V20%

CERM

2

1 C380.1uF20%

CERM402

10V

2

1 C720.1uF

402

10V20%

CERM

2

1R89

MF

5%4701/16W

402

2

1 C500.1uF

402

10VCERM

20%

2

1 C280.1uF20%10V

402CERM

2

1 C390.1uF

402CERM

20%10V

2

1 C470.1uF

CERM402

10V20%

2

1 C260.1uF20%

CERM10V

402

2

1 C310.1uF20%10V

402CERM

2

1R38470

5%1/16W

MF402

21

R36

5%1/16WMF402

10K

21

R45470

5%1/16WMF402

21

R28

5%

10K

402

1/16WMF

21

R3

5%

402MF

1/16W

1K

C3210uF

805CERM6.3V20%

2

1 C3310uF

805CERM

20%6.3V

C59

805CERM6.3V20%10uF

2

1 C58

6.3V20%

CERM805

10uF

21

R27

MF

5%1/16W

402

10K

21

R33

402

1/16WMF

5%

10K

1

2R748

1/16WMF402

4021%

2

1 C622.2uF10V

805CERM

20%2

1 C342.2uF20%

805

10VCERM

21

R25

5%

10K

1/16WMF402

21

R8

5%

10K

1/16WMF402

21

R2811_5V_MAXBUS

603MF

1/16W5%

0

21

R2831_8V_MAXBUS

603MF

1/16W5%

0

+1_5V_SLEEP

+1_8V_SLEEP

2

1R9

1/16W

4705%

MF402

BBANG

21

R2

402MF

1/16W5%

470

D3

K10

K8

J13

J11

J9

J7

H12

H10

M12

M10

M8

L13

L11

L9

L7

K14

K12

H8

C5

E9

F6

E6

E5

E7

F7

G6

L4

A5

F1

D10

E10

B10

B6

A12

L1

A4

B9

C6

F11

E1

K6

A10

A2

F9

H5

E4

P4

G5

A9

D9

A7

D7

C7

C8

B8

J5

H3

G18

F2

E18

D5

C12

V14

V10

V7

V4

U16

U12

U2

T9

T6

C2

R16

R13

R4

P11

P8

P2

N6

M3

L5

K2

B4

C9

E8

B3

G8

D4

D8

B2

H7

H4

G17

F3

E17

V15

V11

V8

V5

U17

U13

U3

D13

T10

T7

R17

R14

R5

P12

P9

P3

N7

M13

D6

M11

M9

M7

M4

L12

L10

L8

L6

K13

K11

C3

K9

K3

K7

J12

J10

J8

J6

H13

H11

H9

B5

E2

A11

N1

P1

K1

G1

R3

M2

H2

B1

A3

J1

B7D2

F8

G9

M1

A8

N2

G7

F5

H6

E3

C1

R1

G2

C10

D1

D11

L2

F10

B11

G10

C4

B12

W1

N5

G3

U1

V2

T1

N3

P5

M5

J3

N4

K4

J2

C11

W2

K5

R2

J4

V1

F4

T2

G4

L3

D12

H1

E11

U56800MHZ

BGAAPOLLO_MPC7445_360

OMIT

2

1 C290.1uF20%

CERM10V

402

2

1 C270.1uF

402

10VCERM

20%

2

1 C250.1uF20%

CERM10V

4022

1 C540.1uF20%

CERM10V

402

2

1 C530.1uF20%

CERM10V

402

2

1 C550.1uF20%

CERM10V

4022

1 C870.1uF20%

CERM402

10V

2

1 C690.1uF10V

402CERM

20%

2

1 C170.1uF20%

CERM402

10V2

1 C820.1uF10V

402CERM

20%

2

1 C810.1uF20%

CERM402

10V

2

1 C610.1uF10V

402

20%

CERM

21

R6

5%1/16WMF402

10K

21

R37

5%1/16WMF402

10K

21

R19

5%1/16WMF402

10K

21

R26

5%1/16WMF402

10K

2

1 C20.1uF20%

CERM10V

402

2

1 C1030.1uF20%

CERM10V

402

2

1 C680.1uF20%

CERM10V

4022

1 C10920%

CERM10V

0.1uF

402

2

1 C107

CERM

20%0.1uF10V

402

2

1 C10410uF

805CERM

20%6.3V

2

1 C1080.1uF

402

10VCERM

20%

2

1 C1100.1uF20%

CERM10V

402

2

1 C10.1uF20%

CERM10V

402

21

XW34SM

OMIT

2

1 C810

402

10V20%

CERM

0.1uF

2

1 C811

805CERM

20%10V

2.2uF

1 CRITICAL CPU_BTR337S2732 U56IC,APOLLO7,1.x,1.0GHZ,1.XV CORE,85C

U56 CPU_BST1 CRITICALIC,APOLLO7,1.X,1.25GHZ,1.XV CORE,85C337S2748

405051-6338 C

CPU_SHD1_L

MAXBUS_SLEEP

CPU_AVDD

CPU_DRDY_L

CPU_EDTI

MAXBUS_SLEEP

CPU_PULLDOWN

CPU_PULLDOWN

CPU_SRWX_L

JTAG_CPU_TDI

CPU_LSSD_MODE

CPU_PULLDOWN

JTAG_CPU_TCK

CPU_EDTI

JTAG_CPU_TMS

CPU_L1TSTCLK

MPIC_CPU_INT_L

CPU_SRESET_L

CPU_SMI_L

CPU_HRESET_L

CPU_EMODE1_L

CPU_PULLUP

CPU_PMONIN_L

CPU_SRWX_L

CPU_CHKSTP_OUT_L

CPU_MCP_L

CPU_SHD0_L

CPU_TBEN

CPU_CHKS_L

CPU_TT<0>

CPU_BR_L

CPU_TS_L

CPU_ADDR<2>

CPU_ADDR<0>

CPU_ADDR<1>

CPU_ADDR<3>

CPU_ADDR<4>

CPU_ADDR<5>

CPU_ADDR<6>

CPU_ADDR<7>

CPU_ADDR<10>

CPU_ADDR<9>

CPU_ADDR<8>

CPU_ADDR<12>

CPU_ADDR<11>

CPU_ADDR<15>

CPU_ADDR<14>

CPU_ADDR<13>

CPU_ADDR<17>

CPU_ADDR<16>

CPU_ADDR<20>

CPU_ADDR<19>

CPU_ADDR<18>

CPU_ADDR<22>

CPU_ADDR<21>

CPU_ADDR<25>

CPU_ADDR<23>

CPU_ADDR<24>

CPU_ADDR<27>

CPU_ADDR<26>

CPU_ADDR<28>

CPU_ADDR<29>

CPU_ADDR<30>

CPU_ADDR<31>

CPU_TT<1>

CPU_TT<4>

CPU_TT<3>

CPU_TT<2>

CPU_TSIZ<0>

CPU_TBST_L

CPU_TSIZ<1>

CPU_GBL_L

CPU_TSIZ<2>

CPU_AACK_L

CPU_WT_L

CPU_CI_L

CPU_ARTRY_L

CPU_SHD0_L

CPU_SHD1_L

CPU_HIT_L

MAXBUS_SLEEP

JTAG_CPU_TRST_L

CPU_PLL_CFG<0>

CPU_PLL_CFG<1>

SYSCLK_CPU

CPU_CLKOUT_SPN NO_TEST=TRUE

CPU_PLL_CFG<4>

CPU_PLL_CFG<2>

CPU_DTI<2>

CPU_DTI<0>

CPU_DTI<1>

CPU_DBG_L

CPU_PLL_CFG<3>

CPU_L2TSTCLK

CPU_LSSD_MODE

CPU_L1TSTCLK

JTAG_CPU_TMS

JTAG_CPU_TRST_L

JTAG_CPU_TCK

JTAG_CPU_TDO_TP

JTAG_CPU_TDI

CPU_QACK_L

CPU_QREQ_L

CPU_TBEN

CPU_TEA_L

CPU_SRESET_L

CPU_HRESET_L

CPU_SMI_L

CPU_MCP_L

MPIC_CPU_INT_L

CPU_CHKSTP_OUT_L

CPU_PMONIN_L

CPU_EMODE0_L

CPU_EMODE1_L

CPU_CHKS_L

CPU_PULLUP

CPU_BUS_VSEL

CPU_L2TSTCLK

CPU_VCORE_SLEEP

ADT7460_VCORE_MON

CPU_VCORE_SLEEP

CPU_PULLDOWN

CPU_TA_L

CPU_BG_L

38

38

38

33

33

33

16

16

16

15

15

15

8

8

39

8

39

39

39

7

7

39

39

39

7

7

39

39

39

39

39

7

38

38

6

36

6

6

6

6

14

39

29

6

39

8

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

6

6

35

36

36

36

36

6

6

6

6

36

36

8

36

39

6

29

14

39

33

33

36

36

5

5

38

8

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

5

5

8

5

5

7

7

8

7

7

8

8

8

8

7

5

5

5

5

5

5

39

5

8

8

5

8

5

5

5

5

5

5

5

7

5

5

5

7

5

5

25

5

5

8

8

Page 6

(2 OF 3)

D0

D60D61D62D63

DP7

DP0DP1DP2DP3DP4DP5DP6

D59

D56D57D58

D55D54D53D52

D50D51

D49

D46D45

D47D48

D44D43D42D41D40D39D38D37D36D35D34D33

D30D31D32

D29

D26D25D24D23

D27D28

D22D21D20D19D18D17D16D15D14D13D12D11D10D9D8D7D6D5D4

D1D2D3

(3 OF 3)

NC_B14NC_B13NC_E12NC_B18NC_N19NC_K17NC_N18NC_N12

NC_A6

NC_C13NC_G11NC_A14NC_F12NC_A13NC_A18NC_C14NC_A15NC_B16NC_E13NC_F13NC_F14NC_G12NC_A17NC_C15NC_G14NC_H14NC_E14NC_G13NC_C16NC_C17NC_B17NC_B15NC_E15NC_D14NC_A19NC_B19NC_A16NC_C18NC_G15NC_D15NC_C19NC_K16NC_J17NC_K18NC_L18NC_L19NC_M18NC_P16NC_L16NC_H15NC_J16NC_K19NC_J15NC_J19NC_J18NC_J14NC_K15NC_L14NC_L17NC_M15NC_N17NC_P19NC_M16NC_M19NC_N16NC_N13NC_M17NC_M14NC_N14NC_P18NC_N15

NC_D19NC_F15NC_G19NC_E16NC_D17NC_D16

NC_P15NC_L15

NC_H19NC_H18NC_H17NC_H16NC_E19NC_D18NC_F16NC_G16

NC_F19NC_F17NC_F18

VCC

RESET*

XTAL1

XTAL2

PB0

PD6PD5PD4PD3PD2PD1PD0

GND

PB1PB2PB3PB4PB5PB6PB7

SYM_VER2

WC*

VCC

VSS

SDASCL

NC1NC2NC3

Y

B

A

Y

B

A

DSIZE

OFSHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

12345678

12345678

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.SCALE

NONE

REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD

QTY DESCRIPTIONPART#TABLE_5_ITEM

NC

NC

UNSTUFFING Ra AND STUFFING Rb

WILL DISABLE THE CONTROLLER

MPC7447/BBANG

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

009-6240 FW GT4 BBANGER

INPUTS ARE 3V TOLERANT INPUTS ARE 3V TOLERANT

BOOT BANGER - TWEAK PROCESSOR BITS AFTER POWER-ON

(Rb)

(Ra)

W6

N8

V3

M6

W9

T4

W4

T3

W13

V13

P14

T8

W8

R8

P6

U15

R7

U7

U8

U4

V17

W3

T17

T18

T16

W18

T15

W17

U18

W19

U19

T19

V19

R18

V18

R19

P17

W16

V6

P7

R6

W7

U5

T5

U6

W5

V9

U9

V16

W10

R9

U10

P10

N9

R10

T11

W11

U11

R11

T14

N10

N11

V12

W12

T12

R12

W14

U14

P13

T13

W15

R15

U56OMIT

BGA

APOLLO_MPC7445_360

800MHZ

P19

P18

P16

P15

N19

N18

N17

N16

N15

N14

N13

N12

M19

M18

M17

M16

M15

M14

L19

L18

L17

L16

L15

L14

K19

K18

K17

K16

K15

J19

J18

J17

J16

J15

J14

H19

H18

H17

H16

H15

H14

G19

G16

G15

G14

G13

G12

G11

F19

F18

F17

F16

F15

F14

F13

F12

E19

E16

E15

E14

E13

E12

D19

D18

D17

D16

D15

D14

C19

C18

C17

C16

C15

C14

C13

B19

B18

B17

B16

B15

B14

B13

A6

A19

A18

A17

A16

A15

A14

A13

U56800MHZ

BGA

OMIT

APOLLO_MPC7445_360

+3V_SLEEP

9

8

7

6

4

3

2

1

10

5

RP46

SM

25V1/32W5%10K

BBANG

2

1 C762BBANG

20%10VCERM402

0.1uF

2

1R69210K1%1/16WMF603

BBANG

2

1R709NO STUFF

10K1%1/16WMF603

2

1R707BBANG

603MF1/16W1%10K

2

1R71210K1%1/16WMF603

BBANG

+3V_SLEEP

4

5

20

1

11

9

8

7

6

3

2

19

18

17

16

15

14

13

12

10

U54

OMIT

SSOPAT90S1200A

2

1 C120BBANG

CERM10V20%

402

0.1uF

+3V_SLEEP

7

4

8

5

6

3

2

1

U52

BBANG

SOI32KX8_M24256B

2

1R100BBANG

402MF

1/16W5%

10K

4

5

3

2

1

U9

SN74AUC1G08SC70-5

BBANG

21

R104

402MF

1/16W5%

0

NO_BBANG

+3V_SLEEP

2

1R103BBANG

402MF

1/16W5%

10K

4

5

3

2

1

U10

SN74AUC1G08SC70-5

BBANG

2

1R10510K

5%1/16W

MF402

BBANG

2

1R637BBANG

603MF1/16W1%10K

C051-6338

406

U54 BBANG1341S1135 MCU,PROGRAMMED W/ BBANGER

PMU_CPU_HRESET_L

BFR_TDO

INT_I2C_DATA0

BBANG_HRESET_L

PMU_CPU_HRESET_L

ICT_TRST_L

BFR_TDO

ESP_EN_L

BBANG_JTAG_TCK

BB_MOSI

BB_MISO

BB_SCK

BB_EEPR_ADDR

JTAG_CPU_TCK

BBANG_JTAG_TCK

BBANG_TCK_EN

MAXBUS_SLEEP

RESET_VREF

BB_RESET_L

BB_XTAL1_SPN

ESP_EN_L

BBANG_JTAG_TCK

JTAG_CPU_TDI

BBANG_HRESET_L

INT_I2C_CLK0

BB_MOSI

BB_SCK

BB_EEPR_WP_PD

INT_I2C_CLK0

INT_I2C_DATA0BB_EEPR_ADDR

CPU_DATA<0>

CPU_DATA<2>

CPU_DATA<1>

CPU_DATA<3>

CPU_DATA<5>

CPU_DATA<4>

CPU_DATA<6>

CPU_DATA<7>

CPU_DATA<8>

CPU_DATA<10>

CPU_DATA<9>

CPU_DATA<12>

CPU_DATA<11>

CPU_DATA<13>

CPU_DATA<15>

CPU_DATA<14>

CPU_DATA<17>

CPU_DATA<16>

CPU_DATA<18>

CPU_DATA<19>

CPU_DATA<20>

CPU_DATA<21>

CPU_DATA<22>

CPU_DATA<23>

CPU_DATA<24>

CPU_DATA<25>

CPU_DATA<26>

CPU_DATA<27>

CPU_DATA<28>

CPU_DATA<29>

CPU_DATA<30>

CPU_DATA<31>

CPU_DATA<33>

CPU_DATA<32>

CPU_DATA<34>

CPU_DATA<35>

CPU_DATA<36>

CPU_DATA<37>

CPU_DATA<38>

CPU_DATA<40>

CPU_DATA<41>

CPU_DATA<42>

CPU_DATA<43>

CPU_DATA<44>

CPU_DATA<46>

CPU_DATA<45>

CPU_DATA<47>

CPU_DATA<48>

CPU_DATA<49>

CPU_DATA<51>

CPU_DATA<50>

CPU_DATA<52>

CPU_DATA<53>

CPU_DATA<54>

CPU_DATA<56>

CPU_DATA<55>

CPU_DATA<57>

CPU_DATA<58>

CPU_DATA<59>

CPU_DATA<61>

CPU_DATA<60>

CPU_DATA<62>

CPU_DATA<63>

ICT_TRST_L

CPU_HRESET_L

MAXBUS_SLEEP

BB_MISO

JTAG_CPU_TMS

JTAG_CPU_TRST_L

CPU_DATA<39>

38

38

33

33

16

16

39

15

39

39

39

15

23

8

23

23

23

8

39

13

39

7

13

13

13

39

7

29

11

29 39

6

39

11

11

11

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

7

6

39

39

36

6

6

6

6

6

6

6

6

6

6

6

6

6

5

6

5

39

6

6

5

6

6

6

6

6

6 6

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

6

5

5

6

5

5

8

Page 7

G

D

S

G

D

S

04

G

D S

G

D

S

S

D

G

DSIZE

OFSHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

12345678

12345678

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.SCALE

NONE

MULTIPLIER

R10D

STATE ENCODING CPU_PLL_STOP_OC CPU_VCORE_HI_OC

CPU CONFIGURATION

+5V_SLEEP NOW REQUIRED FOR PLL_STOP_LPULLUP TO ENSURE THAT Vgs OF PASSTRANSISTOR ON CPU_PLL_CFG<4> IS MET.

R10AR00A

MAXBUS VSEL

1.5V INTERFACE

INVERTED HRESET_L

BUSTYPE SELECT

APOLLO ONLY SUPPORTS MAXBUS

(PROCESSOR)CPU_BUS_VSEL

SIGNAL

(PROCESSOR)CPU_EMODE0_L

CPU_HRESET_L

CPU_HRESET_INV

CPU_HRESET_L

TIEDHIGH

LOW 1.8V INTERFACE

1.5V INTERFACE

2.5V INTERFACE

60X BUS MODE

APPLICATION

MAX BUS MODE

DESKTOP HAD PROBLEM USINGINVERTER TO INVERT HRESET_LNEED TO CHARACTERIZE

1.8V INTERFACE

933

267

400

533

867

800

733

667 0 1011 0B

0 1001 09917

8335.0X

5.5X

333

500

667

9.5X

8.5X

8.0X

9.0X

7.5X

7.0X

6.5X

6.0X

4.0X

3.0X

2.0X

1.0X

0.0X

APOLLO 7

R10E R00ER01A

PLL DISABLE 1 XHIGH SPEED 0 1

R01B R10B R00C R10C R00DR01D

LOW SPEED 0 0

R01E

CPU FREQUENCY CONFIGURATION

(MHZ)

PLL OFF

133MHZ

(Bus-to-Core)

0 1111 0F

CPU_PLL_CFG(AT BUS FREQUENCY)CORE FREQUENCY

167MHZ

PLL BYPASS 0 0011 03

0 0100 04

0 1000 08

0 1010 0A

0 1101 0D

0 0101 05

0 0010 02

0 1100 0C

0 0001 011000

1067

1000

1083

1167

1250

1333

1 0110 1632004000

3733466728.0X

24.0X

1 1010 1A

0 0000 00

1 1000 18

1 1001 191833

1667

1750

1917

1467

1333

1400

1533

1 1100 1C

1 0001 11

1 1101 1D

1 0101 15

0 1110 0E

1 0000 10

1 0010 12

1 0011 13

1 1011 1B

1 1111 1F

1 0100 14

1667

1600

2667

2400

2267

1800

1733

2133

2000

18672333

2500

2667

2083

2000

3333

3000

2833

2250

2167

3500 2800

16.0X

15.0X

14.0X

10.0X

10.5X

11.0X

12.0X

11.5X

12.5X

13.0X

13.5X

17.0X

18.0X

20.0X

21.0X

1 0111 1712001500

1417 1133 0 0110 06

1583 1267 0 0111 07

1 1110 1E

CPU CONFIGURATION

4 0123E ABCD HEX

R10E, R01E, OR PULLUP STUFFEDSTUFF PASS TRANSISTOR ONLY IF

CPU PLL CONFIG CIRCUITRY

R00B R01C

2

1R63

402MF

01/16W5%

CPU_BST

2

1R92NO STUFF

402MF1/16W5%0

2

1R35

1/16W5%

MF402

10K

2

1R50

402MF1/16W5%10K

2

1R6810K5%1/16WMF402 2

1R79

402MF1/16W5%10K

2

1R133

402

5%1/16W

MF

47K

2

1R132

402

5%1/16WMF

10K

2

1R1482K

402MF

1/16W5%

2

1R3105%1/16WMF402

NO STUFF

2

1R2305%1/16WMF402

NO STUFF

2

1R1810K5%

MF402

1/16W

NO STUFF

4

5

3

Q14SOT-3632N7002DW 1

2

6

Q14SOT-3632N7002DW

4

5

3

2

U12

SC70-5

SN74AUC1G04

1_5V_MAXBUS

2

1R12

402MF1/16W5%0

1

2

6

Q32N7002DW

NO STUFF

SOT-363

4

5

3

Q32N7002DW

NO STUFF

SOT-363

+5V_SLEEP

1 2

R5

1/16WMF

5%

22

402

1_5V_MAXBUS

1 2

R11022

1/16WMF

5%

402

2

1R1710

MF

5%1/16W

402

1_8V_MAXBUS

2

1

3

Q132N7002SM

2

3

1 Q12SM2N3904

21

R131249K

402MF

1/16W1%

2

1R43

MF

05%1/16W

402

CPU_BST

+3V_SLEEP

2

1R44NO STUFF

402MF1/16W5%0

2

1R48

402MF1/16W5%0

NO STUFF

2

1R60NO STUFF

402MF1/16W5%0

2

1R64

MF1/16W5%0

402

CPU_BTR

2

1R7005%1/16WMF402 2

1R76NO STUFF

5%01/16WMF402 2

1R84

402MF1/16W5%0

NO STUFF

2

1R78NO STUFF

05%1/16WMF402 2

1R88

402MF1/16W5%0

NO STUFF

C

407051-6338

CPU_PLL_CFG<1>

MAXBUS_SLEEP

CPU_PLL_CFG<0>

CPU_PLL_FS01

CPU_PLL_CFG<2>

CPU_PLL_FS00

CPU_PLL_STOP_BASE

CPU_PLL_CFG<4>

CPU_PLL_STOP_OC

PLL_STOP_L

PLL_STOP_L

CPU_PLL_STOP_OC

CPU_VCORE_HI_OC

CPU_BUS_VSEL

MAXBUS_SLEEP

CPU_HRESET_INVCPU_HRESET_L

CPU_HRESET_L CPU_EMODE0_L

CPU_PLL_FS10

CPU_PLL_CFGEXT

CPU_PLL_CFG<3>

38

38

33

33

16

16

15

15

8

8

39

39

7

7

7

7

6

29

29

33

6

6

6

5

5

5

5

5

7

7

7

7

29

5

5

5

5 5

5

Page 8

(PLL6)VSSA_7

(PLL6)VDD15A_7

D_42

D_41

D_40

D_39

D_38

D_44

D_43

D_45

D_46

D_47

D_48

D_52

D_51

D_50

D_49

D_53

D_55

D_54

D_56

D_57

D_58

D_60

D_59

D_62

D_61

D_63

DBG

DRDY

DTI_0

TEA

TA

DTI_2

DTI_1

D_1

D_0

D_2

D_6

D_5

D_4

D_3

D_7

D_11

D_10

D_9

D_8

D_12

D_14

D_13

D_15

D_16

D_17

D_22

D_21

D_20

D_19

D_18

D_23

D_24

D_25

D_26

D_27

D_32

D_31

D_30

D_29

D_28

D_34

D_33

D_35

D_36

D_37

BR

(1 OF 9)

MAXBUS

INTERFACE

TS

BG

A_0

A_1

A_2

A_3

A_4

A_5

A_9

A_6

A_7

A_8

A_10

A_14

A_13

A_12

A_11

A_20

A_16

A_17

A_18

A_19

A_15

A_27

A_22

A_21

A_30

A_29

A_28

A_26

A_25

A_24

A_23

TT_2

TT_1

TT_0

A_31

TBST

TSIZ_0

TSIZ_1

TSIZ_2

CI

GBL

TT_4

AACK

QREQ

ARTRY

TT_3

WT

HIT

ANALYZER_CLK

SUSPENDACK

SUSPENDREQ

QACK

STOPCPUCLK

CPU_FB_OUT

CPU_FB_IN

CPU_CLK

TBEN

ACS_REF

DSIZE

OFSHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

12345678

12345678

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.SCALE

NONE

2/ D46 - SELPCI1SPREADCLK - SLEEP/WAKE CYCLE REQUIRED

FB BUFFER HAS 50 OHM OUTPUT IMPEDANCE

1: PLL4

0: PLL5 (no spread)

1: PLL4

0: PLL5 (no spread)

PCI0 Source Clock

BIT 40 TO 47

0: Active high

INTREPID BOOT STRAPS

1: Active

OBSOLETE (Should remain high)

OBSOLETE

1: 0-1 IDE / 2-3 PCI1

0: 0 IDE / 1 PCI1

ROM_Ovrly_Rng

1: BootROM on PCI1

0: BootROM on IDE/CardSlot

En_PCI_ROM_P

1: External source

SelPLL4ExtSrc

1: TI PHY workaround

011: 33.3 ohm

101: 40 ohm

110: 66.6 ohm

0: PLL5

BUF_REF_CLK_OUTEnable_h

0: Inactive

1: Active

1/ D47 - SELAGPSPREADCLK - SLEEP/WAKE CYCLE REQUIRED

3/ D44 - PLL4MODESEL_NXT<0> - SLEEP/WAKE CYCLE REQUIRED4/ D43 - PLL4MODESEL_NXT<1> - SLEEP/WAKE CYCLE REQUIRED5/ D42 - PLL4MODESEL_NXT<2> - SLEEP/WAKE CYCLE REQUIRED6/ D33 - ANALYZERCLK_EN_H - IMMEDIATE EFFECT

IF A STRAP IS NOT LISTED, THENIT CANNOT BE CHANGED BY SOFTWARE

THE FOLLOWING STRAP BITS CAN BECHANGED BY SOFTWARE:

LONG = 1" LONGER THAN MATCHED LENGTHSHORT = 1" SHORTER THAN MATCHED LENGTH

NO BUS KEEPER - ?

NO BUS KEEPER - ?

NO BUS KEEPER - ?

NO BUS KEEPER - ?

INPUT - PU

INPUT - PD

NO BUS KEEPER - PU

NO BUS KEEPER - PU

NO BUS KEEPER - PU

INPUT - PU

NO BUS KEEPER - PU

NO BUS KEEPER - PU

INPUT

NO BUS KEEPER

NO BUS KEEPER

Vout = MaxBus rail (1.8V)Vin = Intrepid Vcore (1.5V)

BIT2 BIT1 BIT0

BIT0BIT1BIT2

001: 50 ohm

010: 100 ohm

100: 200 ohm

000: 200 ohm

111: 28.6 ohm

MaxBus output impedance

100: 83.20MHZ

001: 149.76MHZ

PLL4MODESEL_NXT[2:0]

INTREPID OUTPUTS HIGH BY DEFAULT

INTREPID BOOT STRAPS

DDR_TPDModeEnable_h

0: TDI input (JTAG)

Spare

Spare

PCI1_REQ1_L / PCI1_GNT1_L

PCI1_REQ2_L / PCI1_GNT2_L

0: REQ/GNT

1: GPIOs

1: GPIOs

0: REQ/GNT

0: REQ/GNT

1: GPIOs

PCI1_REQ0_L / PCI1_GNT0_L

Processor Bus Mode

0: Legacy interface

1: B-mode interface

FireWire PHY interface

1: 60x bus (G3)

0: Max Bus (G4)

BIT 56 TO 63

0: Normal 1394b

TI 1394b workaround

Spare

Spare

BIT 48 TO 55

0: Inactive

InternalSpreadEn

Spare

PCI1 Source Clock

AnalyzerClk_En_h

1: Active

0: Inactive

DDR_TPDEn_Pol

1: Active low

0: Active high

ExtPLL_SDwn_Pol

1: Active low

Spare

Spare

BIT 32 TO 39

Spare

Spare

Intrepid MaxBusNO BUS KEEPER - PU

MAXBUS PULL-UPS

000: 166.4MHZ (2.5X)

010: 133.12MHZ (2.0X)011: 99.84MHZ (1.5X)

MODE A (2.5X) IS FOR STATIC OPERATIONMODE C (2.0X) IS FOR CLOCK SLEW OPERATION

1: TDI output

2

1R1611K1%

1/16WMF402

2

1C1870.22uF

402CERM6.3V20%

21

R159

402MF

1/16W5%

4.7

21

R1680

5%1/16WMF402

2 1

R1550

402MF

1/16W5%

2

1R169511

402

1%1/16W

MF

2

1R666NO STUFF

5%1/16W

MF402

10K

2

1R63810K

402MF

1/16W5%

NO STUFF

2

1R6395%

1/16WMF402

10K

NO STUFF

2

1R650

MF402

10K5%

1/16W

2

1R6525%

1/16WMF402

10K

2

1R62010K

402MF

1/16W5%

2

1R62110K

402MF

1/16W5%

2

1R6535%

1/16WMF402

10K

2

1R61810K

402MF

5%1/16W

2

1R6195%

1/16WMF402

10K

2

1R640NO STUFF

5%1/16W

MF402

10K

2

1R6225%

1/16WMF402

10K

2

1R69910K

402MF

1/16W5%

NO STUFF

2

1R6935%

1/16WMF402

10K

NO_SSCG

2

1R6945%

1/16WMF402

10K

NO STUFF

2

1R664NO STUFF

10K

402MF

1/16W5%

2

1R66510K

402MF

1/16W5%

SSCG

2

1R641NO STUFF

5%1/16W

MF402

10K

2

1R684

MF

5%1/16W

402

10K

2

1R6795%

1/16WMF402

10K

2

1R6785%

10K

MF1/16W

402

SSCG

2

1R64910K

402MF

5%1/16W

2

1R65110K

402MF

1/16W5%

NO_SSCG

2

1R623

402MF

1/16W5%

10K

2

1R6775%

1/16WMF402

10K

2

1R6485%

1/16WMF402

10K

2

1R642NO STUFF

10K

402MF

1/16W5%

2

1R6985%

1/16WMF402

10K

2

1R643NO STUFF

5%1/16W

MF402

10K

2

1R668NO STUFF

10K

402MF

1/16W5%

2

1R6675%

1/16WMF402

10K

2

1R69510K

402MF

1/16W5%

SSCG

2

1R6265%

1/16WMF402

10K

2

1R68310K

402MF

1/16W5%

NO STUFF

2

1R62410K

402MF

1/16W5%

2

1R6255%

1/16WMF402

10K

2

1R65510K

402MF

1/16W5%

2

1R654NO STUFF

5%1/16W

MF402

10K

2

1R68010K

402MF

1/16W5%

NO_SSCG

2

1R6965%

1/16WMF402

10K

SSCG

2

1R6815%

1/16WMF402

10K

NO_SSCG

2

1R646NO STUFF

10K

402MF

1/16W5%

2

1R6445%

1/16WMF402

10K

2

1R670NO STUFF

10K

402MF

1/16W5%

2

1R697NO STUFF

5%1/16W

MF402

10K

2

1R645NO STUFF

10K

402MF

1/16W5%

2

1R6695%

1/16WMF402

10K

NO STUFF

2

1R6295%

1/16WMF402

10K

2

1R6585%

1/16WMF402

10K

2

1R62710K

402MF

1/16W5%

NO STUFF

2

1R68210K

402MF

1/16W5%

2

1R6285%

1/16WMF402

10K

2

1R65710K

402MF

1/16W5%

2

1R6855%

1/16WMF402

10K

2

1R65610K

402MF

1/16W5%

2

1R146NO STUFF

05%

1/16WMF402

21

R140

402MF

1/16W5%

0

2

1R14105%

1/16WMF402

21

R128

402MF

1/16W5%

0

NO STUFF

21

R1470

5%1/16WMF402

21

R1360

5%1/16WMF402

NO STUFF

D28

H25

H26

J25

D27

B28

G25

E25

D26

H24

G24

B27

E28

A28

A31

E27

AK9

AM8

AH9

A32

G27

B31

A29

D11

E12

A8

G20

B20

G19

E19

A9

D19

A20

J19

B19

H19

A19

A18

D18

B18

E18

B8

B17

A17

G18

D17

H18

J18

A16

E17

B16

A15

B9

H17

B15

G17

E16

D16

A13

A14

D15

J16

E15

H11

G16

A12

B14

D14

H15

B13

G15

B12

E14

H14

E11

G14

A11

D13

B11

G13

E13

D12

A10

J13

B10

G12

D10

B30

D29

K25

G28

A30H16

J24

J15

G26

E29

E26

E23

A25

D23

A26

B26

G23

A21

D20

E24

B21

E20

A22

H21

B22

H20

A23

D21

A24

E21

A27

G21

J21

E22

B23

B24

D22

G22

H22

B25

J22

D25

D24

H23

G8

H13

B29

U51INTREPID-REV2.1

BGA

CRITCAL

21

R15210K

402MF

1/16W5%

21

R150

5%1/16WMF402

10K

21

R15110K

402MF

1/16W5%

81

RP2

SM11/16W5%

10K

54

RP2

SM11/16W5%

10K

72

RP2

SM1

10K

5%1/16W

72

RP3

SM1

10K

5%1/16W

81

RP3

SM1

10K

5%1/16W

63

RP3

SM1

10K

1/16W5%

54

RP3

SM11/16W5%

10K

63

RP2

SM1

10K

1/16W5%

051-6338

408C

CPU_DATA<47>

CPU_DATA<38>

CPU_DATA<34>

CPU_DATA<35>

CPU_TSIZ<0>

CPU_GBL_L

SYSCLK_CPU

CPU_QREQ_L

CPU_DBG_L

CPU_BG_L

CPU_AACK_L

CPU_TEA_L

CPU_DRDY_L

CPU_HIT_L

CPU_ARTRY_L

CPU_BR_L

CPU_TS_L

CPU_TA_L

MAXBUS_SLEEP

MAXBUS_SLEEP

CPU_DATA<39>

CPU_DATA<37>

CPU_DATA<36>

CPU_DATA<33>

CPU_DATA<55>

CPU_DATA<54>

CPU_DATA<45>

CPU_DATA<43>

CPU_DATA<41>

CPU_DATA<40>

CPU_DATA<53>

CPU_DATA<52>

CPU_DATA<51>

CPU_DATA<50>

CPU_DATA<49>

CPU_DATA<48>

CPU_DATA<63>

CPU_DATA<62>

CPU_DATA<61>

CPU_DATA<60>

CPU_DATA<59>

CPU_DATA<58>

CPU_DATA<57>

CPU_DATA<56>

CPU_DATA<32>

+1_5V_INTREPID_PLL

INT_CPUFB_OUT INT_CPUFB_OUT_SHORT

INT_CPUFB_IN

INT_CPUFB_OUT_NORM

INT_CPUFB_IN_NORM

INT_CPUFB_LONG

MAXBUS_SLEEP

+1_5V_INTREPID_PLL7

CPU_TEA_L

CPU_TA_L

CPU_DTI<2>

CPU_DTI<1>

CPU_DTI<0>

CPU_DRDY_L

CPU_DBG_L

CPU_DATA<63>

CPU_DATA<61>

CPU_DATA<62>

CPU_DATA<60>

CPU_DATA<58>

CPU_DATA<59>

CPU_DATA<57>

CPU_DATA<56>

CPU_DATA<55>

CPU_DATA<53>

CPU_DATA<54>

CPU_DATA<52>

CPU_DATA<51>

CPU_DATA<48>

CPU_DATA<50>

CPU_DATA<49>

CPU_DATA<47>

CPU_DATA<46>

CPU_DATA<44>

CPU_DATA<45>

CPU_DATA<43>

CPU_DATA<41>

CPU_DATA<42>

CPU_DATA<40>

CPU_DATA<39>

CPU_DATA<38>

CPU_DATA<37>

CPU_DATA<36>

CPU_DATA<35>

CPU_DATA<34>

CPU_DATA<33>

CPU_DATA<32>

CPU_DATA<30>

CPU_DATA<31>

CPU_DATA<29>

CPU_DATA<28>

CPU_DATA<27>

CPU_DATA<25>

CPU_DATA<26>

CPU_DATA<24>

CPU_DATA<23>

CPU_DATA<22>

CPU_DATA<20>

CPU_DATA<21>

CPU_DATA<19>

CPU_DATA<17>

CPU_DATA<18>

CPU_DATA<16>

CPU_DATA<15>

CPU_DATA<14>

CPU_DATA<12>

CPU_DATA<13>

CPU_DATA<11>

CPU_DATA<10>

CPU_DATA<7>

CPU_DATA<9>

CPU_DATA<8>

CPU_DATA<6>

CPU_DATA<5>

CPU_DATA<2>

CPU_DATA<4>

CPU_DATA<3>

CPU_DATA<0>

CPU_DATA<1>CPU_BR_L

CPU_BG_L

CPU_TS_L

CPU_ADDR<1>

CPU_ADDR<0>

CPU_ADDR<2>

CPU_ADDR<3>

CPU_ADDR<4>

CPU_ADDR<5>

CPU_ADDR<6>

CPU_ADDR<7>

CPU_ADDR<8>

CPU_ADDR<9>

CPU_ADDR<10>

CPU_ADDR<12>

CPU_ADDR<11>

CPU_ADDR<14>

CPU_ADDR<13>

CPU_ADDR<15>

CPU_ADDR<16>

CPU_ADDR<17>

CPU_ADDR<19>

CPU_ADDR<18>

CPU_ADDR<20>

CPU_ADDR<22>

CPU_ADDR<21>

CPU_ADDR<24>

CPU_ADDR<23>

CPU_ADDR<25>

CPU_ADDR<26>

CPU_ADDR<27>

CPU_ADDR<29>

CPU_ADDR<28>

CPU_ADDR<30>

CPU_ADDR<31>

CPU_CI_L

CPU_TBST_L

CPU_TSIZ<2>

CPU_TSIZ<1>

CPU_TT<1>

CPU_TT<0>

CPU_TT<2>

CPU_TT<4>

CPU_TT<3>

CPU_WT_L

CPU_AACK_L

CPU_HIT_L

CPU_ARTRY_L

CPU_QREQ_L

CPU_QACK_L

INT_SUSPEND_REQ_L

INT_SUSPEND_ACK_L

INT_CPUFB_IN

INT_CPUFB_OUT

SYSCLK_LA_TP

CPU_CLK_EN

SYSCLK_CPU_UF

INTREPID_ACS_REF

CPU_TBEN

MAXBUS_SLEEP

CPU_DATA<42>

CPU_DATA<46>

MAXBUS_SLEEP

CPU_DATA<44>

38

38

38

38

38

33

33

33

33

33

16

16

16

16

16

15

15

15

15

15

8

8

8

8

8

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

7

7

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

38

7

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

7

36

36

7

36

8

8

8

8

36

36

35

8

8

8

8

8

8

8

8

8

8

8

6

6

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

14

35

35

6

8

8

36

36

36

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36 8

8

8

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

8

8

8

8

36

35

35

6

8

8

6

8

6

6

6

6

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

12

8 35

8

35

35

35

5

38

5

5

5

5

5

5

5

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6 5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

29

29

8

8

29

35

5

5

6

6

5

6

Page 9

A0A1

A6

A2A3A4A5

A9A8A7

A10A11A12A13A14A15A16

A20

A17A18A19

CEOEWEWPPWD

GND

DQ0DQ1

DQ6DQ5

DQ2DQ3DQ4

DQ7

VPP VCC

FEPR-1MX8

(2 OF 9)

DDR_VREF_1

DDR_VREF_0

DDR_DATA_0

DDR_DATA_1

DDR_DATA_2

DDR_DATA_3

DDR_DATA_4

DDR_DATA_5

DDR_DATA_6

DDR_DATA_7

DDR_DATA_8

DDR_DATA_9

DDR_DATA_10

DDR_DATA_11

DDR_DATA_12

DDR_DATA_13

DDR_DATA_14

DDR_DATA_15

DDR_DATA_16

DDR_DATA_17

DDR_DATA_18

DDR_DATA_19

DDR_DATA_20

DDR_DATA_21

DDR_DATA_25

DDR_DATA_26

DDR_DATA_27

DDR_DATA_28

DDR_DATA_29

DDR_DATA_30

DDR_DATA_33

DDR_DATA_34

DDR_DATA_35

DDR_DATA_36

DDR_DATA_37

DDR_DATA_38

DDR_DATA_39

DDR_DATA_40

DDR_DATA_41

DDR_DATA_42

DDR_DATA_43

DDR_DATA_44

DDR_DATA_45

DDR_DATA_46

DDR_DATA_47

DDR_DATA_48

DDR_DATA_49

DDR_DATA_50

DDR_DATA_51

DDR_DATA_52

DDR_DATA_53

DDR_DATA_54

DDR_DATA_55

DDR_DATA_56

DDR_DATA_57

DDR_DATA_58

DDR_DATA_59

DDR_DATA_60

DDR_DATA_61

DDR_DATA_62

DDR_DATA_63

DDR_DATA_22

DDR_DATA_23

DDR_DATA_24

DDR_DATA_31

DDR_DATA_32

DDR_BA_0

DDR_BA_1

DDRCS_3

DDRCS_2

DDRCS_1

DDRCS_0

DDR_DQS_7

DDR_DQS_6

DDR_DQS_5

DDR_DQS_4

DDR_DQS_3

DDR_DQS_2

DDR_DQS_1

DDR_DQS_0

DDR_DM_7

DDR_DM_6

DDR_DM_5

DDR_DM_4

DDR_DM_3

DDR_DM_2

DDR_DM_1

DDR_DM_0

DDRRAS

DDRCAS

DDRWE

DDRCKE0

DDRCKE1

DDRCKE2

DDRCKE3

DDR_MCLK_0_P

DDR_MCLK_0_N

DDR_MCLK_1_P

DDR_MCLK_1_N

DDR_MCLK_2_P

DDR_MCLK_2_N

DDR_MCLK_3_P

DDR_MCLK_3_N

DDR_MCLK_4_P

DDR_MCLK_4_N

DDR_MCLK_5_P

DDR_MCLK_5_N

DDR_REF

DDR_SELHI_0

DDR_SELHI_1

DDR_SELLO_0

DDR_SELLO_1

MEMORYDDR

INTERFACE

DDR_A_10

DDR_A_11

DDR_A_12

DDR_A_9

DDR_A_8

DDR_A_7

DDR_A_6

DDR_A_5

DDR_A_4

DDR_A_3

DDR_A_2

DDR_A_1

DDR_A_0

DSIZE

OFSHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

12345678

12345678

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.SCALE

NONE

1MB BOOT ROM

Weak pulldowns ensure CKEs stay low

OVERRIDE ROM MODULE

after 2.5V I/O to Intrepid shuts off.

SERIES RESISTORS FOR CLOCK/CONTROL SIGNALS

PINS ARE SWAPABLE FOR RPAKS

INTERCEPTS ROM CHIP SELECT

MEM_VREF

INT - DDR/BOOTROM

CLOCKS

CS

CKE

ADDR

BA

CNTL

’0’S ARE SAME POLARITY (ACTIVE-LO)’1’S ARE SAME POLARITY (ACTIVE-HI)

’0’ & ’1’ GO TO SLOT A’2’ & ’3’ GO TO SLOT B

’0’ & ’1’ GO TO SLOT A’2’ & ’3’ GO TO SLOT B

2

1R260INT_2_5V_COLD

10K5%1/16WMF402 2

1R265INT_2_5V_COLD

402MF1/16W5%10K

12

9

11 3130

10

24

3923

35

34

33

32

28

27

26

25

22

7

8

14

15

16

17

18

38

19

37

13

40

1

2

3

4

5

6

36

20

21

U11

TSOP1MX8-3.3V

21

R17622

5%1/16WMF402

2

1R2091K1%1/16WMF402

2

1R20810K

1%1/16W

MF402

2

1C2490.1uF

20%10V

CERM402

2

1R20210K

402MF

1/16W1%

2

1 C1252.2uF20%

805CERM10V 2

1 C773

402CERM10V20%0.1uF

2

1 C122

402CERM10V20%0.1uF

2

1R1125%

10K1/16W

MF402

+3V_MAIN

T22

Y22

T32

N30

AE29

AB32

AA22

W35

W36

V33

V32

W32

W33

Y30

W30

Y35

Y36

Y32

Y33

L32

N29

P32

V30

AB30

AD32

AH31

AJ31

L33

N32

T33

T35

AC35

AD33

AH33

AJ33

AG35

AG33

AJ36

K35

K36

J36

K33

AJ35

K32

J35

J33

J32

M30

N33

L36

M33

M35

L35

AJ32

M36

N35

R32

R33

R35

R36

P36

P35

R30

P33

AK36

T36

U35

U36

T30

V35

U32

U33

V36

AB33

AA32

AK35

AC36

AB35

AB36

AA33

AA35

AA36

AD35

AD36

AE33

AE35

AK31

AE36

AF36

AF35

AE32

AG31

AG32

AH32

AH36

AG36

AH35

AK33

AK32

M29

L30

H36

D36

G32

E36

E35

F35

F36

G36

D35

H33

G33

G35

H35

K30

L29

AL33

AL35

AN36

AN34

AL36

AM36

AM35

AN35

H32

U51

CRITICAL

INTREPID-REV2.1BGA

2

1R691

402MF1/16W

10K5%

21

R6741K

5%1/16WMF402

54

RP2022

5%1/16WSM1

63

RP20

SM1

22

5%1/16W

81

RP2222

5%1/16WSM1

72

RP22

SM1

22

5%1/16W

72

RP20

SM11/16W5%

22

63

RP22

SM11/16W5%

22

21

R16222

402MF

1/16W5%

81

RP20

SM11/16W5%

22

54

RP22

SM11/16W5%

22

63

RP31

1/16W5%

22

SM1

63

RP29

1/16W5%

22

SM1

72

RP31

1/16W5%

22

SM1

81

RP3122

5%1/16WSM1

54

RP3122

5%1/16WSM1

54

RP29

1/16W5%

22

SM1

81

RP2922

5%1/16WSM1

72

RP2922

5%1/16WSM1

63

RP14

1/16W5%

22

SM172

RP12

1/16W5%

22

SM181

RP12

1/16W5%

22

SM1

63

RP1222

5%1/16WSM1

54

RP12

SM11/16W5%

22

72

RP922

5%1/16WSM1

81

RP922

5%1/16WSM1

72

RP1422

5%1/16WSM1

54

RP922

5%1/16WSM1

81

RP1422

5%1/16WSM1

54

RP14

1/16W5%

22

SM1

54

RP1722

5%1/16WSM1

63

RP9

SM11/16W5%

22

81

RP17

SM11/16W5%

22

72

RP17

SM11/16W5%

22

63

RP17

SM11/16W5%

22

+3V_MAIN

2

1R247INT_2_5V_COLD

402MF1/16W5%10K

2

1R257INT_2_5V_COLD

402MF1/16W5%10K

051-6338

409C

INT_MEM_VREF

MEM_ADDR<12>

MEM_ADDR<11>

MEM_ADDR<10>

MEM_ADDR<9>

MEM_ADDR<8>

MEM_ADDR<7>

MEM_ADDR<6>

MEM_ADDR<5>

MEM_ADDR<4>

MEM_ADDR<3>

MEM_ADDR<2>

MEM_ADDR<1>

MEM_ADDR<0>

MEM_MUXSEL_LSB

MEM_MUXSEL_MSB_L_TP

INT_MEM_REF_H

INT_DDRCLK5_P_TP

INT_DDRCLK5_N_TP

SYSCLK_DDRCLK_B1_L_UF

SYSCLK_DDRCLK_B1_UF

SYSCLK_DDRCLK_B0_L_UF

INT_DDRCLK2_N_TP

SYSCLK_DDRCLK_B0_UF

INT_DDRCLK2_P_TP

SYSCLK_DDRCLK_A1_UF

SYSCLK_DDRCLK_A1_L_UF

SYSCLK_DDRCLK_A0_L_UF

SYSCLK_DDRCLK_A0_UF

MEM_CKE<3>

MEM_CKE<2>

MEM_CKE<1>

MEM_CKE<0>

MEM_WE_L

MEM_CAS_L

MEM_RAS_L

MEM_DQM<7>

MEM_DQM<6>

MEM_DQM<5>

MEM_DQM<4>

MEM_DQM<3>

MEM_DQM<1>

MEM_DQM<0>

MEM_DQM<2>

MEM_DQS<7>

MEM_DQS<6>

MEM_DQS<5>

MEM_DQS<4>

MEM_DQS<3>

MEM_DQS<1>

MEM_DQS<0>

MEM_CS_L<2>

MEM_CS_L<1>

MEM_CS_L<0>

MEM_CS_L<3>

MEM_BA<1>

MEM_BA<0>

MEM_DATA<54>

MEM_DATA<31>

MEM_DATA<29>

MEM_DATA<25>

MEM_DATA<24>

MEM_DATA<15>

MEM_DATA<63>

MEM_DATA<62>

MEM_DATA<61>

MEM_DATA<60>

MEM_DATA<59>

MEM_DATA<58>

MEM_DATA<57>

MEM_DATA<56>

MEM_DATA<55>

MEM_DATA<53>

MEM_DATA<52>

MEM_DATA<51>

MEM_DATA<50>

MEM_DATA<49>

MEM_DATA<48>

MEM_DATA<47>

MEM_DATA<46>

MEM_DATA<45>

MEM_DATA<44>

MEM_DATA<43>

MEM_DATA<42>

MEM_DATA<41>

MEM_DATA<40>

MEM_DATA<39>

MEM_DATA<38>

MEM_DATA<37>

MEM_DATA<36>

MEM_DATA<35>

MEM_DATA<34>

MEM_DATA<33>

MEM_DATA<32>

MEM_DATA<30>

MEM_DATA<28>

MEM_DATA<27>

MEM_DATA<26>

MEM_DATA<23>

MEM_DATA<22>

MEM_DATA<21>

MEM_DATA<20>

MEM_DATA<19>

MEM_DATA<18>

MEM_DATA<17>

MEM_DATA<16>

MEM_DATA<14>

MEM_DATA<13>

MEM_DATA<12>

MEM_DATA<11>

MEM_DATA<10>

MEM_DATA<9>

MEM_DATA<8>

MEM_DATA<7>

MEM_DATA<6>

MEM_DATA<5>

MEM_DATA<4>

MEM_DATA<3>

MEM_DATA<2>

MEM_DATA<1>

MEM_DATA<0>

MEM_MUXSEL_LSB_L_TP

MEM_MUXSEL_MSB

INT_MEM_VREF

SYSCLK_DDRCLK_A1_UF SYSCLK_DDRCLK_A1

SYSCLK_DDRCLK_A0_UF SYSCLK_DDRCLK_A0

SYSCLK_DDRCLK_A1_L_UF SYSCLK_DDRCLK_A1_L

SYSCLK_DDRCLK_B1_UF SYSCLK_DDRCLK_B1

SYSCLK_DDRCLK_B0_UF SYSCLK_DDRCLK_B0

MEM_CS_L<0> RAM_CS_L<0>

SYSCLK_DDRCLK_A0_L_UF SYSCLK_DDRCLK_A0_L

SYSCLK_DDRCLK_B1_L_UF SYSCLK_DDRCLK_B1_L

SYSCLK_DDRCLK_B0_L_UF SYSCLK_DDRCLK_B0_L

MEM_CS_L<1> RAM_CS_L<1>

MEM_CS_L<2> RAM_CS_L<2>

MEM_CKE<0> RAM_CKE<0>

MEM_CKE<2> RAM_CKE<2>

MEM_CS_L<3> RAM_CS_L<3>

MEM_CKE<1>

MEM_CKE<3> RAM_CKE<3>

MEM_ADDR<0> RAM_ADDR<0>

MEM_ADDR<2>

MEM_ADDR<4> RAM_ADDR<4>

MEM_ADDR<6> RAM_ADDR<6>

MEM_ADDR<1> RAM_ADDR<1>

MEM_ADDR<3>

MEM_ADDR<5> RAM_ADDR<5>

MEM_ADDR<7> RAM_ADDR<7>

MEM_ADDR<8> RAM_ADDR<8>

MEM_ADDR<10> RAM_ADDR<10>

MEM_ADDR<12> RAM_ADDR<12>

MEM_ADDR<9> RAM_ADDR<9>

MEM_ADDR<11> RAM_ADDR<11>

MEM_BA<0> RAM_BA<0>

MEM_BA<1>

RAM_CAS_LMEM_CAS_L

MEM_WE_L RAM_WE_L

RAM_RAS_LMEM_RAS_L

RAM_BA<1>

ROM_CS_L

MEM_DQS<2>

RAM_CKE<1>

RAM_CKE<2>

RAM_CKE<1>

RAM_CKE<0>

RAM_CKE<3>

+2_5V_INTREPID

RAM_ADDR<2>

RAM_ADDR<3>

PCI_AD<31>

PCI_AD<30>

PCI_AD<29>

PCI_AD<28>

PCI_AD<27>

PCI_AD<26>

PCI_AD<25>

PCI_AD<24>

PCI_AD<9>

PCI_AD<8>

PCI_AD<7>

PCI_AD<6>

PCI_AD<5>

PCI_AD<4>

PCI_AD<3>

PCI_AD<20>

PCI_AD<2>

PCI_AD<19>

PCI_AD<18>

PCI_AD<17>

PCI_AD<16>

PCI_AD<15>

PCI_AD<14>

PCI_AD<13>

PCI_AD<12>

PCI_AD<11>

PCI_AD<10>

PCI_AD<1>

PCI_AD<0>

ROM_ONBOARD_CS_L

ROM_OE_L

ROM_RW_L

ROM_WP_L

INT_RESET_L

39

39

39

39

39

39

39

39

39

39

39

39

39

39

39

39

39

39

39

39

39

39

39

39

39

39

39

39

39

37

37

37

37

37

37

37

37

37

37

37

37

37

37

37

37

37

37

37

37

37

37

37

37

37

37

37

37

37

38

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

35

35

35

39

35

35

35

35

35

16

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

39

39

38

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

38

35 35

35 35

35 35

35 35

35 35

35 35

35 35

35 35

35 35

35 35

35 35

35 11

35 11

35 35

35

35 11

35 35

35

35 35

35 35

35 35

35

35 35

35 35

35 35

35 35

35 35

35 35

35 35

35 35

35

35 35

35 35

35 35

35

24

35

11

11

11

11

11

15

35

35

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

39

24

24

29

9

9

9

9

9

9

9

9

9

9

9

9

9

9

10

38

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

9

9

9

9

9

9

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

9

9 11

9 11

9 11

9 11

9 11

9 11

9 11

9 11

9 11

9 11

9 11

9 9

9 9

9 11

9

9 9

9 11

9

9 11

9 11

9 11

9

9 11

9 11

9 11

9 11

9 11

9 11

9 11

9 11

9

11 9

9 11

11 9

11

12

10

9

9

9

9

9

10

11

11

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

24

12

12

13

Page 10

GND

DA10 SEL

DH19

DH18

DH17

DH16

DH15

DH14

DH13

DH12

DH11

DH10

DH9

DH8

DH7

DH6

DH5

DH4

DH3

DH2

DH1

DH0

DA19

DA18

DA17

DA16

DA15

DA14

DA13

DA12

DA11DB0*

DA9

DA8

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

DB19*

DB18*

DB17*

DB16*

DB15*

DB14*

DB13*

DB12*

DB11*

DB10*

DB9*

DB8*

DB7*

DB6*

DB5*

DB4*

DB3*

DB2*

DB1*

VDD

GND

DA10 SEL

DH19

DH18

DH17

DH16

DH15

DH14

DH13

DH12

DH11

DH10

DH9

DH8

DH7

DH6

DH5

DH4

DH3

DH2

DH1

DH0

DA19

DA18

DA17

DA16

DA15

DA14

DA13

DA12

DA11DB0*

DA9

DA8

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

DB19*

DB18*

DB17*

DB16*

DB15*

DB14*

DB13*

DB12*

DB11*

DB10*

DB9*

DB8*

DB7*

DB6*

DB5*

DB4*

DB3*

DB2*

DB1*

VDD

GND

DA10 SEL

DH19

DH18

DH17

DH16

DH15

DH14

DH13

DH12

DH11

DH10

DH9

DH8

DH7

DH6

DH5

DH4

DH3

DH2

DH1

DH0

DA19

DA18

DA17

DA16

DA15

DA14

DA13

DA12

DA11DB0*

DA9

DA8

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

DB19*

DB18*

DB17*

DB16*

DB15*

DB14*

DB13*

DB12*

DB11*

DB10*

DB9*

DB8*

DB7*

DB6*

DB5*

DB4*

DB3*

DB2*

DB1*

VDD

GND

DA10 SEL

DH19

DH18

DH17

DH16

DH15

DH14

DH13

DH12

DH11

DH10

DH9

DH8

DH7

DH6

DH5

DH4

DH3

DH2

DH1

DH0

DA19

DA18

DA17

DA16

DA15

DA14

DA13

DA12

DA11DB0*

DA9

DA8

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

DB19*

DB18*

DB17*

DB16*

DB15*

DB14*

DB13*

DB12*

DB11*

DB10*

DB9*

DB8*

DB7*

DB6*

DB5*

DB4*

DB3*

DB2*

DB1*

VDD

DSIZE

OFSHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

12345678

12345678

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.SCALE

NONE

16BIT 2:1 DDR MUXES

BIT 48..63BIT 32..47BIT 16..31BIT 0..15

SEL = LOW; HOST = B PORT; A PORT = 100OHM TO GNDSEL = HIGH; HOST = A PORT; B PORT = 100OHM TO GND

2

1 C72720%10VCERM402

0.1uF

2

1 C745

402CERM10V20%0.1uF

2

1 C74220%10VCERM402

0.1uF2

1 C73220%10VCERM402

0.1uF

2

1 C733

402CERM10V20%0.1uF

2

1 C74120%10VCERM402

0.1uF

2

1 C764

402CERM10V20%0.1uF

2

1 C73420%10VCERM402

0.1uF

2

1 C726

402CERM10V20%0.1uF

2

1 C73020%10VCERM402

0.1uF

2

1 C75820%10VCERM402

0.1uF

2

1 C75720%10VCERM402

0.1uF

F8

F3

E8

E3

H6

H5

G9

G2

D9

D2

C6

C5

E2

C2

B2

B3

B5

B6

B8

B9

C9

E9

F9

H9

J9

J8

J6

J5

J3

J2

H2

F2

E1

C1

A1

A3

A4

A6

B7

A9

B10

D10

F10

H10

K10

K8

K7

K5

J4

K2

J1

G1

D1

B1

A2

B4

A5

A7

A8

A10

C10

E10

G10

J10

K9

J7

K6

K4

K3

K1

H1

F1

U28

CRITICAL

BGACBTV4020

F8

F3

E8

E3

H6

H5

G9

G2

D9

D2

C6

C5

E2

C2

B2

B3

B5

B6

B8

B9

C9

E9

F9

H9

J9

J8

J6

J5

J3

J2

H2

F2

E1

C1

A1

A3

A4

A6

B7

A9

B10

D10

F10

H10

K10

K8

K7

K5

J4

K2

J1

G1

D1

B1

A2

B4

A5

A7

A8

A10

C10

E10

G10

J10

K9

J7

K6

K4

K3

K1

H1

F1

U27

CRITICAL

BGACBTV4020

F8

F3

E8

E3

H6

H5

G9

G2

D9

D2

C6

C5

E2

C2

B2

B3

B5

B6

B8

B9

C9

E9

F9

H9

J9

J8

J6

J5

J3

J2

H2

F2

E1

C1

A1

A3

A4

A6

B7

A9

B10

D10

F10

H10

K10

K8

K7

K5

J4

K2

J1

G1

D1

B1

A2

B4

A5

A7

A8

A10

C10

E10

G10

J10

K9

J7

K6

K4

K3

K1

H1

F1

U18CBTV4020

BGA

CRITICAL

F8

F3

E8

E3

H6

H5

G9

G2

D9

D2

C6

C5

E2

C2

B2

B3

B5

B6

B8

B9

C9

E9

F9

H9

J9

J8

J6

J5

J3

J2

H2

F2

E1

C1

A1

A3

A4

A6

B7

A9

B10

D10

F10

H10

K10

K8

K7

K5

J4

K2

J1

G1

D1

B1

A2

B4

A5

A7

A8

A10

C10

E10

G10

J10

K9

J7

K6

K4

K3

K1

H1

F1

U16CBTV4020

BGA

CRITICAL

C

4010051-6338

RAM_DATA_B<13>

MEM_DQS<3>

MEM_DATA<31>

RAM_DATA_B<25>

RAM_DATA_B<45>

RAM_DATA_B<47>MEM_DATA<5>

MEM_DATA<7>

+2_5V_INTREPID +2_5V_INTREPID+2_5V_INTREPID+2_5V_INTREPID

RAM_DATA_A<57>

MEM_DQM<7>

RAM_DATA_A<56>

RAM_DATA_A<48>

RAM_DATA_A<50>

RAM_DATA_A<51>

RAM_DATA_A<49>

RAM_DATA_A<53>

RAM_DATA_A<52>

RAM_DATA_A<54>

RAM_DATA_A<55>

RAM_DQS_A<6>

RAM_DQM_A<6>

MEM_MUXSEL_MSB

MEM_DATA<63>

MEM_DQS<7>

MEM_DATA<62>

MEM_DATA<60>

MEM_DATA<61>

MEM_DATA<57>

MEM_DATA<58>

MEM_DATA<59>

MEM_DATA<56>

MEM_DQM<6>

MEM_DATA<55>

MEM_DATA<54>

MEM_DQS<6>

MEM_DATA<52>

MEM_DATA<53>

MEM_DATA<50>

MEM_DATA<49>

MEM_DATA<51>

RAM_DQM_A<7>

MEM_DATA<48>

RAM_DQS_A<7>

RAM_DATA_A<62>

RAM_DATA_A<63>

RAM_DATA_A<60>

RAM_DATA_A<61>

RAM_DATA_A<59>

RAM_DATA_A<58>

RAM_DATA_B<59>

RAM_DATA_B<60>

RAM_DATA_B<61>

RAM_DATA_B<62>

RAM_DATA_B<63>

RAM_DQS_B<7>

RAM_DQM_B<7>

RAM_DATA_B<53>

RAM_DATA_B<54>

RAM_DATA_B<55>

RAM_DATA_B<51>

RAM_DATA_B<52>

RAM_DQS_B<6>

RAM_DQM_B<6>

RAM_DATA_B<56>

RAM_DATA_B<57>

RAM_DATA_B<58>

RAM_DATA_B<50>

RAM_DATA_B<49>

RAM_DATA_B<48>RAM_DATA_A<41>

MEM_DQM<5>

RAM_DATA_A<40>

RAM_DATA_A<32>

RAM_DATA_A<34>

RAM_DATA_A<35>

RAM_DATA_A<33>

RAM_DATA_A<37>

RAM_DATA_A<36>

RAM_DATA_A<38>

RAM_DATA_A<39>

RAM_DQS_A<4>

RAM_DQM_A<4>

MEM_MUXSEL_MSB

MEM_DATA<47>

MEM_DQS<5>

MEM_DATA<46>

MEM_DATA<44>

MEM_DATA<45>

MEM_DATA<41>

MEM_DATA<42>

MEM_DATA<43>

MEM_DATA<40>

MEM_DQM<4>

MEM_DATA<39>

MEM_DATA<38>

MEM_DQS<4>

MEM_DATA<36>

MEM_DATA<37>

MEM_DATA<34>

MEM_DATA<33>

MEM_DATA<35>

RAM_DQM_A<5>

MEM_DATA<32>

RAM_DQS_A<5>

RAM_DATA_A<46>

RAM_DATA_A<47>

RAM_DATA_A<44>

RAM_DATA_A<45>

RAM_DATA_A<43>

RAM_DATA_A<42>

RAM_DATA_B<43>

RAM_DATA_B<44>

RAM_DATA_B<46>

RAM_DQS_B<5>

RAM_DQM_B<5>

RAM_DATA_B<37>

RAM_DATA_B<38>

RAM_DATA_B<39>

RAM_DATA_B<35>

RAM_DATA_B<36>

RAM_DQS_B<4>

RAM_DQM_B<4>

RAM_DATA_B<40>

RAM_DATA_B<41>

RAM_DATA_B<42>

RAM_DATA_B<34>

RAM_DATA_B<33>

RAM_DATA_B<32>RAM_DATA_A<25>

MEM_DQM<3>

RAM_DATA_A<24>

RAM_DATA_A<16>

RAM_DATA_A<18>

RAM_DATA_A<19>

RAM_DATA_A<17>

RAM_DATA_A<21>

RAM_DATA_A<20>

RAM_DATA_A<22>

RAM_DATA_A<23>

RAM_DQS_A<2>

RAM_DQM_A<2>

MEM_MUXSEL_LSB

MEM_DATA<30>

MEM_DATA<28>

MEM_DATA<29>

MEM_DATA<25>

MEM_DATA<26>

MEM_DATA<27>

MEM_DATA<24>

MEM_DQM<2>

MEM_DATA<23>

MEM_DATA<22>

MEM_DQS<2>

MEM_DATA<20>

MEM_DATA<21>

MEM_DATA<18>

MEM_DATA<17>

MEM_DATA<19>

RAM_DQM_A<3>

MEM_DATA<16>

RAM_DQS_A<3>

RAM_DATA_A<30>

RAM_DATA_A<31>

RAM_DATA_A<28>

RAM_DATA_A<29>

RAM_DATA_A<27>

RAM_DATA_A<26>

RAM_DATA_B<27>

RAM_DATA_B<28>

RAM_DATA_B<29>

RAM_DATA_B<30>

RAM_DATA_B<31>

RAM_DQS_B<3>

RAM_DQM_B<3>

RAM_DATA_B<21>

RAM_DATA_B<22>

RAM_DATA_B<23>

RAM_DATA_B<19>

RAM_DATA_B<20>

RAM_DQS_B<2>

RAM_DQM_B<2>

RAM_DATA_B<24>

RAM_DATA_B<26>

RAM_DATA_B<18>

RAM_DATA_B<17>

RAM_DATA_B<16>RAM_DATA_A<9>

MEM_DQM<1>

RAM_DATA_A<8>

RAM_DATA_A<0>

RAM_DATA_A<2>

RAM_DATA_A<3>

RAM_DATA_A<1>

RAM_DATA_A<5>

RAM_DATA_A<4>

RAM_DATA_A<6>

RAM_DATA_A<7>

RAM_DQS_A<0>

RAM_DQM_A<0>

MEM_MUXSEL_LSB

MEM_DATA<15>

MEM_DQS<1>

MEM_DATA<14>

MEM_DATA<12>

MEM_DATA<13>

MEM_DATA<9>

MEM_DATA<10>

MEM_DATA<11>

MEM_DATA<8>

MEM_DQM<0>

MEM_DATA<6>

MEM_DQS<0>

MEM_DATA<4>

MEM_DATA<2>

MEM_DATA<1>

MEM_DATA<3>

RAM_DQM_A<1>

MEM_DATA<0>

RAM_DQS_A<1>

RAM_DATA_A<14>

RAM_DATA_A<15>

RAM_DATA_A<12>

RAM_DATA_A<13>

RAM_DATA_A<11>

RAM_DATA_A<10>

RAM_DATA_B<11>

RAM_DATA_B<12>

RAM_DATA_B<14>

RAM_DATA_B<15>

RAM_DQS_B<1>

RAM_DQM_B<1>

RAM_DATA_B<5>

RAM_DATA_B<6>

RAM_DATA_B<7>

RAM_DATA_B<3>

RAM_DATA_B<4>

RAM_DQS_B<0>

RAM_DQM_B<0>

RAM_DATA_B<8>

RAM_DATA_B<9>

RAM_DATA_B<10>

RAM_DATA_B<2>

RAM_DATA_B<1>

RAM_DATA_B<0>

38 38 38 38

16 16 16

16

15 15 15

15

35 35 35

35

35

35

35

35

35

35 35

35

10 10 10

10

35

35

35

35

35

35

35

35

35

35

35

35

35

10

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35 35

35

35

35

35

35

35

35

35

35

35

35

35

10

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35 35

35

35

35

35

35

35

35

35

35

35

35

35

10

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35 35

35

35

35

35

35

35

35

35

35

35

35

35

10

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

11

9

9

11

11

11 9

9

9 9 9

9

11

9

11

11

11

11

11

11

11

11

11

11

11

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

11

9

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11 11

9

11

11

11

11

11

11

11

11

11

11

11

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

11

9

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11 11

9

11

11

11

11

11

11

11

11

11

11

11

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

11

9

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11 11

9

11

11

11

11

11

11

11

11

11

11

11

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

11

9

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

Page 11

DQ58

RFU18

KEY

VDD6

VSS6

VSS8

VDD5

DQ15

DQ13

DQ14

VSS5

DM1

VDD3

VSS3

DQ7

DQ12

DQ6

DM0

DQ4

DQ5

VSS1

VREF1

VDD1

SA1

SA2

RFU19

SA0

VDD32

DQ63

DQ62

VSS32

DQ61

VDD30

DQ60

DQ55

DM7

VSS30

DQ54

DM6

VDD28

DQ53

DQ52

VDD25

CK1*

CK1

VSS28

DQ47

DQ46

VDD23

VSS25

DM5

DQ45

DQ44

DM4

DQ39

VSS23

DQ38

DQ37

RFU17

DQ36

VSS21

VDD21

VDD19

RAS*

BA1

CAS*

S1*

A6

A4

A2

A0

VSS19

A8

A11

VDD17

RFU15

CKE0

VDD15

VSS17

RFU11

VSS16

RFU9

VDD14

RFU3

VSS14

RFU5

RFU7

RFU1

VDD12

VSS12

DM3

DQ31

DQ30

DQ29

VSS10

VDD10

DQ28

DQ23

DM2

DQ20

VDD8

DQ21

DQ22

VDDSPD

SCL

SDA

VDD31

VSS31

DQ59

DQS7

DQ51

VDD29

DQ56

VSS29

DQ57

DQ48

DQS6

VDD27

DQ49

DQ50

DQ43

VSS26

VDD26

VDD24

VSS27

DQ41

DQS5

VSS24

VDD22

DQ42

DQ34

VSS22

DQ35

DQS4

DQ40

VDD20

RFU16

DQ32

VSS20

DQ33

S0*

VDD18

BA0

A10_AP

WE*

A1

A5

A3

A9

A7

VSS18

CKE1

RFU14

RFU13

VDD16

VDD13

VSS15

RFU10

RFU8

RFU12

RFU0

RFU4

VSS13

RFU2

RFU6

VSS11

DQ26

DQ27

DQS3

VDD11

DQ19

DQ24

VDD9

VSS9

DQ25

DQ18

DQ16

VDD7

DQ17

DQS2

DQ11

VDD4

VSS7

CK0*

CK0

DQS1

VSS4

DQ10

VDD2

DQ9

DQ2

DQS0

DQ8

DQ3

VSS2

VDD0

DQ0

DQ1

VSS0

VREF0

A12

(1 OF 2)(2 OF 2)

DQ58

RFU18

KEY

VDD6

VSS6

VSS8

VDD5

DQ15

DQ13

DQ14

VSS5

DM1

VDD3

VSS3

DQ7

DQ12

DQ6

DM0

DQ4

DQ5

VSS1

VREF1

VDD1

SA1

SA2

RFU19

SA0

VDD32

DQ63

DQ62

VSS32

DQ61

VDD30

DQ60

DQ55

DM7

VSS30

DQ54

DM6

VDD28

DQ53

DQ52

VDD25

CK1*

CK1

VSS28

DQ47

DQ46

VDD23

VSS25

DM5

DQ45

DQ44

DM4

DQ39

VSS23

DQ38

DQ37

RFU17

DQ36

VSS21

VDD21

VDD19

RAS*

BA1

CAS*

S1*

A6

A4

A2

A0

VSS19

A8

A11

VDD17

RFU15

CKE0

VDD15

VSS17

RFU11

VSS16

RFU9

VDD14

RFU3

VSS14

RFU5

RFU7

RFU1

VDD12

VSS12

DM3

DQ31

DQ30

DQ29

VSS10

VDD10

DQ28

DQ23

DM2

DQ20

VDD8

DQ21

DQ22

VDDSPD

SCL

SDA

VDD31

VSS31

DQ59

DQS7

DQ51

VDD29

DQ56

VSS29

DQ57

DQ48

DQS6

VDD27

DQ49

DQ50

DQ43

VSS26

VDD26

VDD24

VSS27

DQ41

DQS5

VSS24

VDD22

DQ42

DQ34

VSS22

DQ35

DQS4

DQ40

VDD20

RFU16

DQ32

VSS20

DQ33

S0*

VDD18

BA0

A10_AP

WE*

A1

A5

A3

A9

A7

VSS18

CKE1

RFU14

RFU13

VDD16

VDD13

VSS15

RFU10

RFU8

RFU12

RFU0

RFU4

VSS13

RFU2

RFU6

VSS11

DQ26

DQ27

DQS3

VDD11

DQ19

DQ24

VDD9

VSS9

DQ25

DQ18

DQ16

VDD7

DQ17

DQS2

DQ11

VDD4

VSS7

CK0*

CK0

DQS1

VSS4

DQ10

VDD2

DQ9

DQ2

DQS0

DQ8

DQ3

VSS2

VDD0

DQ0

DQ1

VSS0

VREF0

A12

DSIZE

OFSHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

12345678

12345678

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.SCALE

NONENCNC

NC NC

NCNC

on the PCB for additional mountingNOTE: The SODIMM connector footprint has a through-hole slot

NC

NC

NC

NC

NC

NC

NC

NC

ADDR=0XA0(WR)/0XA1(RD)

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

SLOT "A"LOWER SLOTFACTORY SLOT

NC

ADDR=0XA2(WR)/0XA3(RD)

SLOT "B"UPPER SLOTCUSTOMER SLOT

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC

NC

DDR SODIMM CONNS

SLOT "B"

SLOT "A"

DDR BYPASS

DDR VREFONE 0.1UF PER SLOT

2

1 C1400.1uF20%10V

402CERM2

1 C1560.1uF20%10V

402CERM 2

1 C1320.1uF10V

402CERM

20%

119B

51B

40B39B

38B

28B27B

16B

186B185B

174B

15B

173B

162B161B

159B

150B149B

138B137B

126B125B

4B

104B103B

90B

88B87B

76B75B

64B63B

52B

3B

2B1B

197B

57B

46B45B

36B

34B33B

22B

192B191B

180B

21B

179B

168B167B

157B

156B155B

144B143B

132B131B

10B

114B113B

94B93B

92B

82B81B

70B69B

58B

9B

193B

195B

198B

196B

194B

122B121B

84B83B

80B79B

78B77B

74B73B

72B

200B199B

124B123B

98B97B

91B

89B

86B85B

71B

118B

402

401

183B

169B

147B

133B

61B

47B

25B

11B

23B

19B

18B

14B

190B

188B

182B

178B

8B

189B

187B

181B

177B

176B

172B

166B

164B

175B

171B

6B

165B

163B

154B

152B

146B

142B

153B

151B

145B

141B

17B

140B

136B

130B

128B

139B

135B

129B

127B

68B

66B

13B

60B

56B

67B

65B

59B

55B

54B

50B

44B

42B

7B

53B

49B

43B

41B

32B

30B

24B

20B

31B

29B

5B

184B

170B

148B

134B

62B

48B

26B

12B

95B 96B

158B

160B

37B

35B

120B

116B

117B

101B 102B

105B 106B

107B 108B

109B 110B

111B

99B 100B

115B

112B

J25CRITICAL

F-RT-SM

DDR-SO-DIMM-DUAL

119A

51A

40A39A

38A

28A27A

16A

186A185A

174A

15A

173A

162A161A

159A

150A149A

138A137A

126A125A

4A

104A103A

90A

88A87A

76A75A

64A63A

52A

3A

2A1A

197A

57A

46A45A

36A

34A33A

22A

192A191A

180A

21A

179A

168A167A

157A

156A155A

144A143A

132A131A

10A

114A113A

94A93A

92A

82A81A

70A69A

58A

9A

193A

195A

198A

196A

194A

122A121A

84A83A

80A79A

78A77A

74A73A

72A

200A199A

124A123A

98A97A

91A

89A

86A85A

71A

118A

404

403

183A

169A

147A

133A

61A

47A

25A

11A

23A

19A

18A

14A

190A

188A

182A

178A

8A

189A

187A

181A

177A

176A

172A

166A

164A

175A

171A

6A

165A

163A

154A

152A

146A

142A

153A

151A

145A

141A

17A

140A

136A

130A

128A

139A

135A

129A

127A

68A

66A

13A

60A

56A

67A

65A

59A

55A

54A

50A

44A

42A

7A

53A

49A

43A

41A

32A

30A

24A

20A

31A

29A

5A

184A

170A

148A

134A

62A

48A

26A

12A

95A 96A

158A

160A

37A

35A

120A

116A

117A

101A 102A

105A 106A

107A 108A

109A 110A

111A

99A 100A

115A

112A

J25CRITICAL

F-RT-SM

DDR-SO-DIMM-DUAL

2

1 C40410uF20%6.3VCERM805

2

1 C12810uF20%6.3VCERM805

2

1R299

402MF1/16W1%1K

2

1R3031K1%1/16WMF402

2

1 C3970.1uF

402CERM10V20%

2

1 C4030.1uF20%10VCERM402

+2_5V_MAIN+2_5V_MAIN

+2_5V_MAIN

+2_5V_MAIN

+2_5V_MAIN+2_5V_MAIN

+3V_MAIN +3V_MAIN+3V_MAIN

2

1 C169

CERM402

10V20%0.1uF

2

1 C3910.1uF10V

402CERM

20%2

1 C35620%

CERM402

10V

0.1uF

2

1 C2110.1uF20%10V

402CERM 2

1 C1270.1uF20%10V

402CERM

+2_5V_MAIN

2

1 C17410uF

805CERM6.3V20%

2

1 C15020%

CERM402

10V

0.1uF

2

1 C15710uF

805CERM6.3V20%

2

1 C3830.1uF20%10V

402CERM

051-6338

11 40C

RAM_DATA_B<37>

RAM_DATA_B<63>

RAM_DATA_B<62>

RAM_DQM_B<7>

RAM_DATA_B<61>

RAM_DATA_B<60>

RAM_DATA_B<55>

RAM_DATA_B<54>

RAM_DQM_B<6>

RAM_DATA_B<53>

RAM_DATA_B<52>

SYSCLK_DDRCLK_B1

SYSCLK_DDRCLK_B1_L

RAM_DATA_B<47>

RAM_DATA_B<46>

RAM_DQM_B<5>

RAM_DATA_B<45>

RAM_DATA_B<44>

RAM_DATA_B<39>

RAM_DATA_B<38>

RAM_DQM_B<4>

RAM_DATA_B<36>

RAM_CS_L<3>

RAM_CAS_L

RAM_RAS_L

RAM_BA<1>

RAM_ADDR<0>

RAM_ADDR<2>

RAM_ADDR<4>

RAM_ADDR<6>

RAM_ADDR<8>

RAM_ADDR<11>

RAM_CKE<2>

RAM_DATA_B<31>

RAM_DATA_B<30>

RAM_DQM_B<3>

RAM_DATA_B<29>

RAM_DATA_B<28>

RAM_DATA_B<22>

RAM_DQM_B<2>

RAM_DATA_B<21>

RAM_DATA_B<20>

RAM_DATA_B<15>

RAM_DATA_B<14>

RAM_DQM_B<1>

RAM_DATA_B<13>

RAM_DATA_B<12>

RAM_DATA_B<7>

RAM_DATA_B<6>

RAM_DQM_B<0>

RAM_DATA_B<5>

RAM_DATA_B<4>

DDR_VREF

INT_I2C_CLK0

INT_I2C_DATA0

RAM_DATA_B<59>

RAM_DATA_B<58>

RAM_DQS_B<7>

RAM_DATA_B<57>

RAM_DATA_B<56>

RAM_DATA_B<51>

RAM_DATA_B<50>

RAM_DQS_B<6>

RAM_DATA_B<49>

RAM_DATA_B<48>

RAM_DATA_B<43>

RAM_DATA_B<42>

RAM_DQS_B<5>

RAM_DATA_B<41>

RAM_DATA_B<40>

RAM_DATA_B<35>

RAM_DATA_B<34>

RAM_DQS_B<4>

RAM_DATA_B<33>

RAM_DATA_B<32>

RAM_CS_L<2>

RAM_WE_L

RAM_BA<0>

RAM_ADDR<10>

RAM_ADDR<1>

RAM_ADDR<3>

RAM_ADDR<5>

RAM_ADDR<7>

RAM_ADDR<9>

RAM_ADDR<12>

RAM_CKE<3>

RAM_DATA_B<27>

RAM_DATA_B<26>

RAM_DQS_B<3>

RAM_DATA_B<25>

RAM_DATA_B<24>

RAM_DATA_B<19>

RAM_DATA_B<18>

RAM_DQS_B<2>

RAM_DATA_B<17>

RAM_DATA_B<16>

SYSCLK_DDRCLK_B0_L

SYSCLK_DDRCLK_B0

RAM_DATA_B<11>

RAM_DATA_B<10>

RAM_DQS_B<1>

RAM_DATA_B<9>

RAM_DATA_B<8>

RAM_DATA_B<3>

RAM_DATA_B<2>

RAM_DQS_B<0>

RAM_DATA_B<1>

RAM_DATA_B<0>

DDR_VREF

DDR_VREF

RAM_DATA_B<23>

RAM_DATA_A<38>

RAM_DQM_A<4>

RAM_BA<1>

RAM_DATA_A<28>

RAM_DATA_A<15>

RAM_DATA_A<63>

RAM_DATA_A<62>

RAM_DQM_A<7>

RAM_DATA_A<61>

RAM_DATA_A<60>

RAM_DATA_A<55>

RAM_DATA_A<54>

RAM_DQM_A<6>

RAM_DATA_A<53>

RAM_DATA_A<52>

SYSCLK_DDRCLK_A1

SYSCLK_DDRCLK_A1_L

RAM_DATA_A<47>

RAM_DATA_A<46>

RAM_DQM_A<5>

RAM_DATA_A<45>

RAM_DATA_A<44>

RAM_DATA_A<39>

RAM_DATA_A<37>

RAM_DATA_A<36>

RAM_CS_L<1>

RAM_CAS_L

RAM_ADDR<0>

RAM_ADDR<2>

RAM_ADDR<4>

RAM_ADDR<6>

RAM_ADDR<8>

RAM_ADDR<11>

RAM_CKE<0>

RAM_DATA_A<31>

RAM_DATA_A<30>

RAM_DQM_A<3>

RAM_DATA_A<29>

RAM_DATA_A<23>

RAM_DQM_A<2>

RAM_DATA_A<21>

RAM_DATA_A<20>

RAM_DATA_A<14>

RAM_DQM_A<1>

RAM_DATA_A<13>

RAM_DATA_A<12>

RAM_DATA_A<7>

RAM_DATA_A<6>

RAM_DQM_A<0>

RAM_DATA_A<5>

RAM_DATA_A<4>

DDR_VREF

RAM_DATA_A<56>

RAM_DATA_A<50>

INT_I2C_CLK0

INT_I2C_DATA0

RAM_DATA_A<59>

RAM_DATA_A<58>

RAM_DQS_A<7>

RAM_DATA_A<57>

RAM_DATA_A<51>

RAM_DQS_A<6>

RAM_DATA_A<49>

RAM_DATA_A<48>

RAM_DATA_A<43>

RAM_DATA_A<42>

RAM_DQS_A<5>

RAM_DATA_A<41>

RAM_DATA_A<40>

RAM_DATA_A<35>

RAM_DATA_A<34>

RAM_DQS_A<4>

RAM_DATA_A<33>

RAM_DATA_A<32>

RAM_CS_L<0>

RAM_WE_L

RAM_BA<0>

RAM_ADDR<10>

RAM_ADDR<1>

RAM_ADDR<3>

RAM_ADDR<5>

RAM_ADDR<7>

RAM_ADDR<9>

RAM_ADDR<12>

RAM_CKE<1>

RAM_DATA_A<27>

RAM_DATA_A<26>

RAM_DQS_A<3>

RAM_DATA_A<25>

RAM_DATA_A<24>

RAM_DATA_A<19>

RAM_DATA_A<18>

RAM_DQS_A<2>

RAM_DATA_A<17>

RAM_DATA_A<16>

SYSCLK_DDRCLK_A0_L

SYSCLK_DDRCLK_A0

RAM_DATA_A<11>

RAM_DATA_A<10>

RAM_DQS_A<1>

RAM_DATA_A<9>

RAM_DATA_A<8>

RAM_DATA_A<3>

RAM_DATA_A<2>

RAM_DQS_A<0>

RAM_DATA_A<1>

RAM_DATA_A<0>

RAM_RAS_L

RAM_DATA_A<22>

DDR_VREF

39

39

39

39

23

23

23

23

35

35

35

35

35

35

35

35

35

13

13

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

13

13

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

11

11

11

11

11

11

11

11

11

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

38

11

11

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

11

11

11

11

11

11

11

11

11

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

38

38

35

35

35

11

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

11

11

11

11

11

11

11

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

38

35

35

11

11

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

11

11

11

11

11

11

11

11

11

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

35

11

35

38

10

10

10

10

10

10

10

10

10

10

10

9

9

10

10

10

10

10

10

10

10

10

9

9

9

9

9

9

9

9

9

9

9

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

11

6

6

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

9

9

9

9

9

9

9

9

9

9

9

10

10

10

10

10

10

10

10

10

10

9

9

10

10

10

10

10

10

10

10

10

10

11

11

10

10

10

9

10

10

10

10

10

10

10

10

10

10

10

10

9

9

10

10

10

10

10

10

10

10

9

9

9

9

9

9

9

9

9

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

11

10

10

6

6

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

9

9

9

9

9

9

9

9

9

9

9

10

10

10

10

10

10

10

10

10

10

9

9

10

10

10

10

10

10

10

10

10

10

9

10

11