DSL Development Board Rev 2/01/01 1 Purdue Digital Systems Labs Development Board K. Otte and D. Meyer School of Electrical & Computer Engineering Purdue University West Lafayette, Indiana Objective The objective of this project was to develop a robust instructional tool for the Digital Systems Labs in the School of Electrical & Computer Engineering at Purdue University. For an introductory microprocessor course like EE 362, Microprocessor System Design and Interfacing, it provides a Motorola 68HC12 with built-in debugger. It also has a large FPGA, which can be used autonomously or in conjunction with the 68HC12. Up to 128 KB of RAM is available for prototyping and debugging software-intensive embedded applications, such as those students complete for EE 477, Digital Systems Senior Design Project. A Liquid Crystal Display (LCD) and expansion connectors are also available, which include full access to the address and data bus along with sixteen programmable pins to facilitate custom interfaces. For a computer architecture course like EE 437, Computer Design and Prototyping, a hardware platform based on an Altera FPGA is provided to prototype and exercise a microprocessor core. The on-board RAM can be loaded by the 68HC12 with instructions for the experimental core to execute, and then switched to the experimental core’s bus for execution. The 68HC12 can then reclaim the bus for a post-run analysis of the memory. The development board is designed to accommodate a simple microcontroller or multi-cycle microprocessor. It is theoretically possible to implement a pipelined microprocessor with a larger FPGA so an internal split cache could be created. The board was designed with upward compatibility for this option, but the current design is focused on implementation of a multi-cycle processor. Seven byte-wide logic analyzer ports are provided for monitoring critical signals. Several clocking methods are available to provide a wide range of clocking options: an external function generator, on-board 25MHz and 16 MHz oscillators, and the 68HC12 pulse width modulator. For a future “System on a Chip” course, an FPGA-based hardware platform is provided with several interfacing options. 128 KB of external RAM is available for lookup tables or other applications that have large memory requirements. Two PS/2 style connectors are provided for a keyboard and mouse interface. A standard VGA connector is available for a monitor interface. A serial charge pump is provided to create an RS232 style serial port. For example, all of these interfaces could be pulled together to make a terminal, which has a VGA interface, a keyboard interface, and a custom serial port. The platform is flexible and robust enough to handle many different interface combinations. A daughter board is available which contains buttons, switches, and lights for system debugging and control. For senior design project courses, a platform is provided that has a robust microcontroller-based core with many flexible interfacing options. The options available facilitate projects that focus on the development of feature boards and software. In a single- semester design course it often takes the better part of the time available to get the core running, thus delaying the development of software and feature boards. The development platform provided here makes it possible for these tasks to begin earlier in the design cycle by providing a core that has a microcontroller, RAM, programmable logic, and a plethora of interfaces.
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DSL Development Board Rev 2/01/011
Purdue Digital Systems Labs Development BoardK. Otte and D. Meyer
School of Electrical & Computer EngineeringPurdue University
West Lafayette, Indiana
ObjectiveThe objective of this project was to develop a robust instructional tool for the Digital
Systems Labs in the School of Electrical & Computer Engineering at Purdue University. For anintroductory microprocessor course like EE 362, Microprocessor System Design and Interfacing,it provides a Motorola 68HC12 with built-in debugger. It also has a large FPGA, which can beused autonomously or in conjunction with the 68HC12. Up to 128 KB of RAM is available forprototyping and debugging software-intensive embedded applications, such as those studentscomplete for EE 477, Digital Systems Senior Design Project. A Liquid Crystal Display (LCD)and expansion connectors are also available, which include full access to the address and databus along with sixteen programmable pins to facilitate custom interfaces.
For a computer architecture course like EE 437, Computer Design and Prototyping, ahardware platform based on an Altera FPGA is provided to prototype and exercise amicroprocessor core. The on-board RAM can be loaded by the 68HC12 with instructions for theexperimental core to execute, and then switched to the experimental core’s bus for execution.The 68HC12 can then reclaim the bus for a post-run analysis of the memory. The developmentboard is designed to accommodate a simple microcontroller or multi-cycle microprocessor. It istheoretically possible to implement a pipelined microprocessor with a larger FPGA so an internalsplit cache could be created. The board was designed with upward compatibility for this option,but the current design is focused on implementation of a multi-cycle processor. Seven byte-widelogic analyzer ports are provided for monitoring critical signals. Several clocking methods areavailable to provide a wide range of clocking options: an external function generator, on-board25MHz and 16 MHz oscillators, and the 68HC12 pulse width modulator.
For a future “System on a Chip” course, an FPGA-based hardware platform is providedwith several interfacing options. 128 KB of external RAM is available for lookup tables or otherapplications that have large memory requirements. Two PS/2 style connectors are provided for akeyboard and mouse interface. A standard VGA connector is available for a monitor interface.A serial charge pump is provided to create an RS232 style serial port. For example, all of theseinterfaces could be pulled together to make a terminal, which has a VGA interface, a keyboardinterface, and a custom serial port. The platform is flexible and robust enough to handle manydifferent interface combinations. A daughter board is available which contains buttons,switches, and lights for system debugging and control.
For senior design project courses, a platform is provided that has a robustmicrocontroller-based core with many flexible interfacing options. The options availablefacilitate projects that focus on the development of feature boards and software. In a single-semester design course it often takes the better part of the time available to get the core running,thus delaying the development of software and feature boards. The development platformprovided here makes it possible for these tasks to begin earlier in the design cycle by providing acore that has a microcontroller, RAM, programmable logic, and a plethora of interfaces.
DSL Development Board Rev 2/01/012
AbstractThe board is divided into four principal sections. The first section is the Motorola
68HC12 debugger. This section requires a minimal set of circuitry for the 68HC12 to run inbackground debug mode for the main 68HC12. The second section is the main 68HC12. Thismicrocontroller can be used in single chip mode or in expanded mode. It has the ability tocommunicate with the “glue logic” PLD, the FPGA, the RAM, the LCD, and several expansionconnectors. The third section is the glue logic. Its purpose is to provide all of the necessaryinterfaces with and meet the timing requirements of each device. It performs bus switching toallow for multiple bus masters, de-multiplexes the 68HC12 signals, and creates the necessarytiming for the LCD. The last section is the Altera FPGA (“FLEX” chip). This large FPGA canbe used as a peripheral to the main 68HC12, or loaded with a microprocessor core and run on itsown. It has access to a series of external interfaces: VGA, PS2 keyboard, PS2 mouse, serial port,and RAM. It also has seven byte-wide logic analyzer ports that can also serve as expansionconnectors.
Serial Port
Serial Port
Serial Port
KeyboardMouse
BNC
JTAGRAM LCD
Main HC12
Debugger HC12 BDM
BDM
Glue Logic
Altera Flex
VGA
Analyzer Ports
Expansion Port
i
Figure 1. Board Block Diagram.
DSL Development Board Rev 2/01/013
Hardware Design
Power Supply
D5
LED
MIC29300U10
123
InGndVcc
Ext_Pwr
R1015K
D4
1N4001
12
VCC
J2
DC Power
1
2
C3010uF
F1 2A
Figure 2. Power Supply Schematic.
The power supply is designed to provide regulated 5 VDC with a current draw around 2amps. The input power is expected to be an unregulated 6 VDC power supply. A low-drop-outregulator is used to minimize heat dissipation (in contrast, a conventional 7805 regulator requiresa minimum input of 7.5 VDC to produce a regulated 5 VDC output, and thus dissipatesconsiderably more heat than a low-drop-out regulator using a lower input voltage). An effortwas made to keep the power supply components as close to room temperature as possible toavoid safety hazards. The current draw of the board is dynamic: the minimum draw is around0.7A for a fully populated board, but increases as peripherals are attached. The daughter boardwith seven-segment displays and dual banks of LEDs increases the load significantly.
Additional features are also provided for protection. A fuse is placed in series with thesupply. In an overload condition the fuse will sacrifice itself to save the board. A diode isincluded to protect the board from becoming reverse-biased.
ClockingThe primary clock domain of the board is based on a 16 MHz oscillator. An oscillator
was used to avoid having several redundant crystal circuits on the board. In order for the gluelogic to be able to correctly create some of the needed bus timing, a free-running clock wasrequired, phase-locked to the clock used by the microcontrollers. Therefore, an oscillator wasused to provide a clocking signal to both 68HC12s as well as the glue logic.
An on-board 25.125 MHz oscillator provides the timing necessary for the VGA interface.This clock is directly connected to the Altera FPGA for low delay and clock skew, and also fedto the “glue logic” EPLD so it can be used in other clock chains.
68HC12 DebuggerThe 68HC12 has a background debug mode (BDM) that makes it possible to use one
68HC12 to debug another one. To avoid the need for additional hardware, a 68HC12 is providedon board to act as the debugger for the main 68HC12. Headers are provided so externaldebuggers can be used if necessary. By default, the processor is set to boot up in single chipmode, and the debugger software is set to background debug mode. The jumper configurationfor the debugging headers and processor interconnection is shown below.
The main 68HC12 is modeled after the M68HC12B32EVB Evaluation Board. It has allof its signals pulled out to headers for observation. The headers are in the exact sameconfiguration as the evaluation board so any test fixtures designed to connect with the evaluationboard will also mate with this board. By default, the processor is set to boot up in single chipmode; however, its external bus is connected to the glue logic FPGA and expected to be able to
DSL Development Board Rev 2/01/015
run in expanded wide mode. To enter this mode, the MODE register ($0B) is set to $71 and theMISC register ($13) is set to $74. Through the glue logic EPLD, the microcontroller has accessto many different peripherals, including 128K of external RAM. An LCD display may beoptionally mapped into the 68HC12’s memory space; the timing needed to operate the display ismanaged by the EPLD. The Altera Flex 10K FPGA may also be memory mapped in to the68HC12’s memory space. This FPGA could be used as a custom-designed peripheral such as aUART, SPI, USB, Ethernet controller, etc. A front-end interface (FI) would be requireddepending on the desired interface, but all of the headers are present to make the addition of sucha FI as painless as possible.
68HC12 Flash Programming
VFPD1
1N4148JH1
Flash Prog
11
VCC
D2
1N4001
1 2
Figure 4. Flash Programming Voltage Circuit.
The flash programming circuit is rather basic, but addresses some critical issues. First, asmall-signal diode (1N4148) is provided to ensure that the flash programming pin will always beat approximately 5VDC (or higher). If the flash programming voltage is absent, the diode isforward biased and holds the 68HC12’s VFP pin at about 4.5VDC. If the flash programmingvoltage is present, it isolates the main power plane (5 VDC) from the programming voltage. Theflash programming voltage required for optimal performance is critical: it must be between11.4VDC and 11.8VDC (12VDC is too much and will damage the flash). A 1N4001 diode isplaced in series with the flash programming header and the VFP pin of the 68HC12. Thisprovides one diode drop of about 0.5V, making it possible to use a standard 12VDC supply forflash programming power.
NOTE: Motorola claims the flash is good for about 100 programming cycles. Experimentally ithas been found to be much less than that. It is good practice not to program the flash any morethan necessary and do not leave the flash programming voltage applied any longer than strictlynecessary. It has been found the flash can usually be programmed reliably using backgrounddebug mode at 1200 baud.
Glue Logic
The glue logic chip is an Altera Max EPM7256SRC208 EPLD. Its primary function is toact as a bus arbiter and timing manager for the different interconnected peripherals. It has acomplete 16-bit independent address and data path to the 68HC12, RAM, and the Altera FPGA.It also manages the clocking for the Altera FPGA and creates the bus timing that is needed for
DSL Development Board Rev 2/01/016
the LCD interface. The details of its operation are covered in depth in a later section devoted tothe software.
JTAG Programmer
TMS_Port
TCK
R2621K
VCC
JTAG Port
TDI_Port
TDO
TDO
R2401K
TMS_Port
VCC
R2631K
HC12_JTAG
R2411K
R261 1K
PDLC2
JP204
HEADER 5X2
1 23 45 67 89 10
TCK_Port
PDLC3
TDI_Port
PDLC4
Port_JTAG
TDI
R260 1K
R2421K
R2651K
VCC
TMS
TMS
TDO_Port
TCK_PortTDI
VCC
R2431K
PDLC5
C2100.1uF
TDO_Port
R2641K
TCK
TDO
74ALS244
U5
3579
12141618
17151311
8642
20
191
2Y42Y32Y22Y1
1Y41Y31Y21Y1
2A42A32A22A1
1A41A31A21A1
VCC
2OE1OE
Figure 5. JTAG Programming Circuit.
The programming circuit for the two Altera devices (glue logic EPLD and applicationFPGA) is a JTAG chain. JTAG is a four-wire serial style interface. The Altera Byte Blaster isused to interface the board with a host computer through a ten-pin header that is provided. Thesignals are then conditioned and passed through a line driver. The line driver functions like a tri-state style multiplexer. In one configuration, this “multiplexer” passes the signals from theJTAG header to the Altera devices; in the other configuration, the JTAG signals are masteredfrom the 68HC12. This makes it possible to use the 68HC12 as the programmer rather than theByte Blaster, and for the 68HC12 (via its serial port) to program the Altera devices. This featureallows the Altera devices to be programmed in a UNIX environment (where PC style serial portsare not available, or not supported by Altera). In addition to being able to select theprogramming source, the JTAG chain can be configured as a two-device chain, or any of thedevices may be configured independently.
The memory consists of two 128Kx8 SRAM chips. All of the control signals are createdby the glue logic EPLD. The bus itself is isolated from the hosts by the EPLD to support theswitching of the driving hosts. To combat noise and signal integrity issues that were found inrepeated high-speed accesses, pull-up resistors are applied to all signals. All of the signals arepulled out to headers for debugging or expansion.
DSL Development Board Rev 2/01/018
LCD Interface
Data15
LCD_nCS
LCD_Contrast_Filtered
R2541K
LCD_Contrast_Filtered
R2191K
C22310uF
VCC
R2511K
R2211K
Data11
Data13
LCD_RSLCD_nWE
R2521K
LCD_Contrast
Data10
R2561K
R2531K
R2551K
VCC
Data8
R2571K
R223
1K
R2201K
Data9
JP202
HEADER 14
1234567891011121314
Data14
R2501K
Data12
Figure 7. LCD Schematic.
The LCD interface is a standard 14-pin interface. The timing for the LCD isautomatically generated in the EPLD so the display can be both read and written. The timing forthe LCD is different than the rest of the bus timing. Notching of several of the control signals isrequired on both the rising and falling edge. The contrast for the LCD is controlled by areference signal that varies from 0 to 5 VDC. This signal is created digitally with one of theHC12’s pulse width modulators and a large capacitor. This makes it possible to create thedesired analog reference voltage from the digital pulse width modulator.
Altera FlexThe Altera “Flex” FPGA serves as a large, programmable resource for prototyping digital
systems. It can be used to implement a microprocessor core and run as a master of its ownbuses, or it can serve as a peripheral of the HC12. Logic analyzer headers are provided as ameans of monitoring its status, which can also be used for expansion connectors. Severalperipherals are also directly connected to the Altera FPGA. A simple VGA interface is providedwith a couple of diodes and resistors. Two PS/2 connectors, a serial port, and a coax connectorare available. A 25MHz oscillator is provided to meet the strict timing requirements of the VGAinterface.
DSL Development Board Rev 2/01/019
Daughter BoardThe daughter board is a “button, switches, and lights” board for the Altera FPGA. It
provides four push buttons, 16 DIP switches, four 7-segment displays, and 16 LEDs. Its purposeis to provide a variety of human interfaces to the FPGA for VHDL design and development.
7Seg_DP
Dig111
7421
1053
12
9
8
6
ABCDEFGDp
Dig1
Dig2
Dig3
Dig4R7 100
7Seg_E7Seg_F
7Seg_A
R4 100
7Seg_B
R6 100
7Seg_C
7Seg_Dig4
R2 100
7Seg_Dig1
R8 100
R1 100
7Seg_Dig3
Q2
IRF7104
1
3
2
45
6
7
8
VCC
7Seg_Dig2
R3 100
Q1
IRF7104
1
3
2
45
6
7
8
U5
74ACT541
23456789
119
1817161514131211
A1A2A3A4A5A6A7A8
G1G2
Y1Y2Y3Y4Y5Y6Y7Y8
7Seg_DR5 100
7Seg_G
Figure 8. 7 Segment Display Schematic.
To save on the number of signals necessary to run a quad 7-segment display, amultiplexed version is used. A transistor controlled by the EPLD supplies the voltage source foreach segment. Only one of the transistors should be on at a time, and it should be pulsed at a ratearound 10KHz to avoid overdriving the segments. A driver in the EPLD should be created thatscans the display pulsing the necessary segments for each one of the digits in a repeated fashion.
Button Button Button ButtonDip Switch BankDip Switch Bank
Quad Seven Segment Display
LEDs LEDs
Con
nect
orC
onne
ctor
Con
nect
orC
onne
ctor
ConnectorConnectorConnector Connector
Figure 9. Daughter Board Assembly Drawing.
DSL Development Board Rev 2/01/0110
Programmable Logic
Altera Max 7KThe Altera Max 7K is the glue logic EPLD that provides the necessary interfaces and
flexibility to make the board design extendible. Since the chip is in the middle (crossroads) ofthe board, the original developer of the code (Mike Faulhaber) code-named the project Indiana.Indiana has many different independent functions, which in most cases are controlled by aregister file presented to the main HC12. From this register file, the HC12 can manage theinternal interfaces of the chip. Due to size constraints some of the functionality of the design isconstrained. It is possible to recompile the code to provide other options, but the mostcommonly used options are run-time controllable through the register file. By default theregister file entries are four bits based at address at $0200 in the main HC12's address space.
Table 4. Indiana's Register File
Offset Register0 Upper Address1 MIPS Clock2 Bus Control3 LCD Contrast
The board architecture is based around a 16-bit bus. This makes it possible to address 216
or 64K byte locations. There are two 128K byte memories available on the board. To access theremaining locations in memory outside of the bus width, a windowing technique is used. A fixed4K window at $C000 in the main HC12's address space can be moved through the upper addressranges by concatenating the value of this register with the existing address bus.
From Indiana's point, the FPGA contains a MIPS-like microprocessor core. The clockpin for this core is configurable from Indiana. It can be clocked from the HC12 with either theHC12 or a custom clock frequency generated by the HC12's pulse width modulator. Otheroptions are to pass it a 25 MHz clock signal from an on-board oscillator, which it can usedirectly or divide down. The last choice is a custom signal from an external function generator.
Table 5. MIPS Clock Register Values.
Value Clock Source0 HC12 ECLK1 Hc12 PWM2 External Connector3 25MHz
A memory-space LCD interface is provided that can be dynamically mapped to any ofthe system buses. One issue with making an LCD a memory-mapped device is managing thetiming. The LCD expects its signals to be setup prior to receipt of an enable signal pulse. Theenable signal pulse must be asserted for at least the specified minimum duration, and must be“notched in” from both the beginning and end of the cycle. Indiana has an internal state machine
DSL Development Board Rev 2/01/0111
that handles this timing. Indiana takes the value off of the system bus, freeing the micro from theburden of the timing differences and then moves the data to the LCD with the necessary timing.The main microprocessor must wait until the LCD transaction is finished before anothertransaction may be requested. There is no built in queuing. Also the LCD has adjustablecontrast which is an analog signal ranging between zero and five volts. A counter in Indiana isprocessed through a filter to create a ranging analog signal. By varying the duty cycle of thedigital signal, an analog reference voltage can be created across the full range. This duty cycle iscontrolled by the contrast register making it possible for the HC12 to digitally manage thecontrast of the LCD.
The Bus register is used to select the master of the peripheral bus. When the value is azero, the HC12 is the master of the peripheral bus and the RAM. When the value is a one, theMIPS core has control of the peripheral bus. Through this register the HC12 can load imagesinto RAM for the MIPS core to be able to access.
Another feature that facilitates implementation of a MIPS core is a forced jumpinstruction, placed at address zero in the MIPS address space. This allows code to be loaded at ahigher address (such as $C000). When the MIPS core executes, it will automatically jump to theinsertion point.
In addition to these interfaces, there are several interfaces provided for expansion. Thecomplete peripheral address and data bus is available on headers for expansion purposes. Also,sixteen bits of user customizable signals are provided on an expansion header. This makes itpossible for development board to easily interface with other boards.
Altera Flex 10KThe Altera Flex FPGA can be programmed to act as an independent system. In this
mode, with the daughter board attached, it can be used for a variety of stand-alone applications.It can also implement a microprocessor core and access the RAM through the glue logic. Asidefrom running in stand-alone mode, it can be a member of the HC12's bus and provide anopportunity to develop a large single-chip peripheral. Seven test ports are provided which aredesigned to interface directly to a logic analyzer. These ports also serve as expansion connectorsto the daughter board.
Table 8. Altera Flex Pin Assignments for Daughter Board.
Table 9. Altera Flex Pin Assignments for On-Board Connectors.
Signal Pin Signal PinMouse Data 174 VGA Horizontal Sync 191Mouse Clock 175 VGA Vertical Sync 192Keyboard Data 184 VGA Blue 193Keyboard Clock 187 VGA Green 194Serial Port TX 119 VGA Red 195Serial Port RX 120 25 MHz Clock 211Clock (Indiana Selectable) 91
Signal Pin Signal Pin25MHz 211 Switch One 1 219Display One Enable 136 Switch One 2 218Display Two Enable 137 Switch One 3 217Display Three Enable 138 Switch One 4 215Display Four Enable 139 Switch One 5 214Segment A 94 Switch One 6 208Segment B 95 Switch One 7 207Segment C 97 Switch One 8 206Segment D 98 Switch Two 1 204Segment E 99 Switch Two 2 203Segment F 100 Switch Two 3 202Segment G 101 Switch Two 4 201Segment DP 102 Switch Two 5 200Button 1 83 Switch Two 6 199Button 2 82 Switch Two 7 198Button 3 81 Switch Two 8 196Button 4 80 Led 8 154Led 0 164 Led 9 153Led 1 163 Led 10 152Led 2 162 Led 11 151Led 3 161 Led 12 149Led 4 159 Led 13 148Led 5 158 Led 14 147Led 6 157 Led 15 146Led 7 156
DSL Development Board Rev 2/01/0115
Main Board - Bill of MaterialsItem Quantity Reference Part Supplier1 35 C8, C18, C19, C20, C21, C200,
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - C r e a t e d o n : 4 - 4 - 0 0- - C r e a t e d b y : M i k e F a u l h a b e r , K u r t O t t e- - V e r s i o n 1 . 1- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -l i b r a r y i e e e ;u s e i e e e . s t d _ l o g i c _ 1 1 6 4 . A L L ;u s e i e e e . s t d _ l o g i c _ a r i t h . A L L ;u s e i e e e . s t d _ l o g i c _ u n s i g n e d . A L L ;
e n t i t y I n d i a n a i s
p o r t ( n R e s e t : i n s t d _ l o g i c ; E x t _ C l k : i n s t d _ l o g i c ; E x t _ O s c : i n s t d _ l o g i c ;
- - L o o p B a c k G C L R N : i n s t d _ l o g i c ; O E 1 : i n s t d _ l o g i c ; G C L K 2 : i n s t d _ l o g i c ; G C L K : i n s t d _ l o g i c ;
G C L R N _ o u t : o u t s t d _ l o g i c ; O E 1 _ o u t : o u t s t d _ l o g i c ; O E 2 _ o u t : o u t s t d _ l o g i c ; G C L K _ o u t : o u t s t d _ l o g i c ;
- - H C 1 2 P o r t s H C 1 2 D a t a : i n o u t s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; H C 1 2 _ P E : i n s t d _ l o g i c _ v e c t o r ( 7 d o w n t o 0 ) ; H C 1 2 _ P P : i n s t d _ l o g i c _ v e c t o r ( 7 d o w n t o 0 ) ;
- - M i p s M i p s D a t a : i n o u t s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; M i p s A d d r : i n s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ;
M i p s _ n C S : i n s t d _ l o g i c ; - - C t r l 0 M i p s _ R n W : i n s t d _ l o g i c ; - - C t r l 1 M i p s _ n O E : i n s t d _ l o g i c ; - - C t r l 2 M i p s _ C t r l : i n s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 3 ) ;
M i p s _ C l k : o u t s t d _ l o g i c ; M i p s _ I n p u t 3 : o u t s t d _ l o g i c ; M i p s _ I n p u t 4 : o u t s t d _ l o g i c ;
- - P e r f . R a m _ n W E _ L : o u t s t d _ l o g i c ; R a m _ n W E _ H : o u t s t d _ l o g i c ; R A M _ n C S _ O u t : o u t s t d _ l o g i c ; R A M _ n O E : o u t s t d _ l o g i c ; R A M A d d r : o u t s t d _ l o g i c _ v e c t o r ( 1 6 d o w n t o 0 ) ; R A M D a t a : i n o u t s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ;
A l t _ n C S 1 : o u t s t d _ l o g i c ; A l t _ n C S 2 : o u t s t d _ l o g i c ;
E x p a n s i o n : o u t s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ;
L C D _ C o n t r a s t : o u t s t d _ l o g i c ; L C D _ C S _ O u t : o u t s t d _ l o g i c ; L C D _ n W E : o u t s t d _ l o g i c ; L C D _ R S : o u t s t d _ l o g i c ) ;e n d I n d i a n a ;
DSL Development Board Rev 2/01/0119
a r c h i t e c t u r e s t r u c t u r e o f I n d i a n a i s
- - S i g a l s u s e d i n n a m e t r a n s l a t i o n
s i g n a l E C l k : s t d _ l o g i c ; s i g n a l n L S T R B : s t d _ l o g i c ; s i g n a l H C 1 2 R n W : s t d _ l o g i c ;
s i g n a l P W M : s t d _ l o g i c ; s i g n a l B N C : s t d _ l o g i c ; s i g n a l O S C : s t d _ l o g i c ;
- - P L D A d d r e s s s e l e c t
s i g n a l I n t _ n C S : s t d _ l o g i c ;
- - P L D A d d r e s s R e g i s t e r s
s i g n a l U p p e r _ A d d r e s s _ R e g : s t d _ l o g i c _ v e c t o r ( 3 d o w n t o 0 ) ; s i g n a l C L K _ R e g : s t d _ l o g i c _ v e c t o r ( 3 d o w n t o 0 ) ; s i g n a l B u s _ R e g : s t d _ l o g i c _ v e c t o r ( 3 d o w n t o 0 ) ; s i g n a l C o n t r a s t _ R e g : s t d _ l o g i c _ v e c t o r ( 3 d o w n t o 0 ) ;
- - F o r A d d r e s s / D a t a R o u t i n g
s i g n a l H C 1 2 A d d r _ I n t : s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; s i g n a l H C 1 2 A d d r _ I n t _ E x t e n d e d : s t d _ l o g i c _ v e c t o r ( 1 6 d o w n t o 0 ) ; s i g n a l H C 1 2 D a t a _ I n t : s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; s i g n a l P l d _ D a t a : s t d _ l o g i c _ v e c t o r ( 3 d o w n t o 0 ) ; s i g n a l E x t D e v i c e _ D a t a : s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; s i g n a l R A M D a t a _ I n t : s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; s i g n a l R A M D a t a _ F i l t e r e d : s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; s i g n a l R A M A d d r _ I n t : s t d _ l o g i c _ v e c t o r ( 1 6 d o w n t o 0 ) ; s i g n a l M i p s D a t a _ I n t : s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; s i g n a l M i p s A d d r _ I n t : s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; s i g n a l M i p s A d d r _ I n t _ E x t e n d e d : s t d _ l o g i c _ v e c t o r ( 1 6 d o w n t o 0 ) ; s i g n a l C r o p p e d _ M i p s _ A d d r : s t d _ l o g i c _ v e c t o r ( 5 d o w n t o 0 ) ; - - M i p s C l o c k S o u r c e
s i g n a l M i p s _ C l k _ I n t : s t d _ l o g i c ;
- - C o n t r o l S i g n a l s
s i g n a l H c 1 2 _ R a m _ n C S : s t d _ l o g i c ; s i g n a l M i p s _ R a m _ n C S : s t d _ l o g i c ;
s i g n a l R A M _ n C S : s t d _ l o g i c ; s i g n a l L C D _ C S : s t d _ l o g i c ; s i g n a l L C D _ S e l e c t : s t d _ l o g i c ;
s i g n a l H C 1 2 _ n O E : s t d _ l o g i c ;
s i g n a l H C 1 2 _ D a t a b u s _ E n : s t d _ l o g i c ; s i g n a l M i p s _ D a t a b u s _ E n : s t d _ l o g i c ;
s i g n a l H C 1 2 _ n W E : s t d _ l o g i c ; s i g n a l H C 1 2 _ n W E _ L : s t d _ l o g i c ; s i g n a l H C 1 2 _ n W E _ H : s t d _ l o g i c ;
t y p e s t a t e _ t y p e i s ( W a i t i n g , P u l s e , H o l d ) ; s i g n a l S t a t e : s t a t e _ t y p e ; s i g n a l c o u n t : i n t e g e r r a n g e 0 t o 7 ; s i g n a l c o n t r a s t _ c o u n t e r : s t d _ l o g i c _ v e c t o r ( 7 d o w n t o 0 ) ;
b e g i n
- - - - - - - - - - - - - - - - - - S i g n a l R e m a p i n g - - - - - - - - - - - - - - - - - - - - - - - - - - - - I n o r d e r t o r e s e r v e s o m e s i g n a l s f o r l a t e r u s e a n d t o m a k e t h e - - p i n o u t o f t h e c h i p m a t c h t h e s c h e m a t i c s i g n a l s h a v e b e e n - - r e m a p p e d . T h e m a j o r i t y o f t h e f o l l o w i n g e q u a t i o n s w i l l n o t
DSL Development Board Rev 2/01/0120
- - - r e s u l t i n a n y l o g i c s y n t h e s i s j u s t n a m e t r a n s l a t i o n .
E C l k < = H C 1 2 _ P E ( 4 ) ; n L S T R B < = H C 1 2 _ P E ( 3 ) ; H C 1 2 R n W < = H C 1 2 _ P E ( 2 ) ;
P W M < = H C 1 2 _ P P ( 0 ) ; B N C < = E x t _ C l k ; O S C < = E x t _ O s c ;
- - - - - - - - - - - - - - - - - - - G l o b a l S i g n a l s L o o p b a c k - - - - - - - - - - - - - - - - - - - - G C L R N _ o u t < = n R e s e t ; O E 1 _ o u t < = ' 1 ' ; O E 2 _ o u t < = E C l k ; G C L K _ o u t < = ' Z ' ;
- - - - - - - - - - - - R e s e r v e d S i g n a l - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T h i s s i g n a l s a r e r e s e r v e d f o r f u t u r e e x p a n s i o n s M i p s _ I n p u t 3 < = ' 0 ' ; M i p s _ I n p u t 4 < = ' 0 ' ; A l t _ n C S 1 < = G C L K ; A l t _ n C S 2 < = G C L K 2 ;
E x p a n s i o n < = " 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 " ;
- - - - - - - - - - M I P S C l o c k S o u r c e - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - D e p e n d i n g o n t h e v a l u e s s e t i n C l k _ R e g , t h e C l o c k s e n t t o t h e M I P S- - C h i p g e t s t h e c o o r e s p o n d i n g c l o c k
M i p s _ C l k < = M i p s _ C l k _ I n t ;
w i t h C l k _ R e g ( 1 d o w n t o 0 ) s e l e c t M i p s _ C l k _ I n t < = ( E C l k ) w h e n " 0 0 " , - - ( t o M I P S ) H C 1 2 e c l k ( P W M ) w h e n " 0 1 " , - - M i p s _ C l k _ I n t ( t o M I P S ) g e t s H C 1 2 P W M ( B N C ) w h e n " 1 0 " , - - M i p s _ C l k _ I n t ( t o M I P S ) g e t s B N C ( O S C ) w h e n " 1 1 " , - - M i p s _ C l k _ I n t ( t o M I P S ) g e t s O S C ' 0 ' w h e n o t h e r s ;
- - - - - - - - - - * e n d * - M I P S C l o c k S o u r c e - * e n d * - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - T r a n s p a r e n t L a t c h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H C 1 2 A d d r _ I n t < = H C 1 2 D a t a w h e n ( E C l k = ' 0 ' ) e l s e H C 1 2 A d d r _ I n t ;
- - - - - - - - - - - - - - - - - - - - - P L D I n t e r n a l A d d r e s s S p a c e - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - T h i s p r o c e s s e f f e c t s t h e C o n t r o l R e g i s t e r s - - W h e n t h e A d d r e s s b e i n g w r i t t e n f r o m t h e H C 1 2 i s 0 x 2 0 0 [ 0 - 3 ] - - T h e D a t a i s m a p p e d t o a C o n t r o l R e g i s t e r P L D _ R e g i s t e r _ W r i t t i n g : p r o c e s s ( G C L K 2 , G C L R N ) b e g i n i f G C L R N = ' 0 ' t h e n U p p e r _ A d d r e s s _ R e g ( 3 d o w n t o 0 ) < = " 0 1 1 0 " ; C l k _ R e g ( 3 d o w n t o 0 ) < = " 0 0 0 0 " ; B u s _ R e g ( 3 d o w n t o 0 ) < = " 0 0 0 0 " ; C o n t r a s t _ R e g ( 3 d o w n t o 0 ) < = " 1 1 0 0 " ;
e l s i f ( G C L K 2 ' e v e n t a n d G C L K 2 = ' 0 ' ) t h e n i f ( H C 1 2 R n W = ' 0 ' a n d I n t _ n C S = ' 0 ' ) t h e n - - P L D w r i t e m o d e c a s e H C 1 2 A d d r _ I n t ( 1 d o w n t o 0 ) i s w h e n " 0 0 " = > - - A d d r e s s S p a c e M a p p i n g R e g U p p e r _ A d d r e s s _ R e g < = H C 1 2 D a t a ( 1 1 d o w n t o 8 ) ; w h e n " 0 1 " = > - - M i p s C l o c k S o u r c e R e g C l k _ R e g < = H C 1 2 D a t a ( 1 1 d o w n t o 8 ) ; w h e n " 1 0 " = > - - B u s F l o w D i r e c t i o n R e g B u s _ R e g < = H C 1 2 D a t a ( 1 1 d o w n t o 8 ) ; w h e n " 1 1 " = > - - L C D C o n t r a s t C o n t r a s t _ R e g < = H C 1 2 D a t a ( 1 1 d o w n t o 8 ) ; w h e n o t h e r s = > e n d c a s e ;
DSL Development Board Rev 2/01/0121
e n d i f ; - - c h i p s e l e c t e n d i f ; - - r e s e t / c l k e n d p r o c e s s P L D _ R e g i s t e r _ W r i t t i n g ;
L C D _ C o n t r o l : p r o c e s s ( G C L K ) b e g i n i f ( G C L K ' e v e n t a n d G C L K = ' 0 ' ) t h e n c a s e S t a t e i s w h e n W a i t i n g = > - - W a i t i n g f o r c h i p s e l e c t L C D _ C S < = ' 0 ' ; i f ( L C D _ S e l e c t = ' 1 ' ) t h e n S t a t e < = P u l s e ; c o u n t < = 0 ; e n d i f ;
w h e n P u l s e = > - - p u l s e e n a b l e s i g n a l L C D _ C S < = ' 1 ' ; i f ( c o u n t = 3 ) t h e n s t a t e < = H o l d ; e l s e c o u n t < = c o u n t + 1 ; e n d i f ;
w h e n H o l d = > L C D _ C S < = ' 0 ' ; i f ( L C D _ S e l e c t = ' 0 ' ) t h e n s t a t e < = W a i t i n g ; e n d i f ;
e n d c a s e ; e n d i f ; e n d p r o c e s s L C D _ C o n t r o l ;
- - L C D _ C o n t r a s t < = P W M ; C o n t r a s t : p r o c e s s ( G C L K ) b e g i n i f ( G C L K ' e v e n t a n d G C L K = ' 0 ' ) t h e n c o n t r a s t _ c o u n t e r < = c o n t r a s t _ c o u n t e r + 1 ; i f ( c o n t r a s t _ c o u n t e r = C o n t r a s t _ R e g & " 1 1 1 0 " ) t h e n L C D _ C o n t r a s t < = ' 1 ' ; e l s i f ( c o n t r a s t _ c o u n t e r = " 1 1 1 1 1 1 1 1 " ) t h e n L C D _ C o n t r a s t < = ' 0 ' ; e n d i f ; e n d i f ; e n d p r o c e s s C o n t r a s t ;
- - T h e L C D R e g i s t e r S p a c e i s a t A d d r 0 x 0 2 1 0 t o 0 x 0 2 1 F ( R e g i s t e r - - F o l l o w i n g A r e a o f H C 1 2 ) t h e f o l l o w i n g l i n e c o n t r o l s r e a d i n g - - a n d w r i t t i n g t o t h e p l d r e g i s t e r s p a c e .
L C D _ S e l e c t < = ' 1 ' w h e n ( H C 1 2 A d d r _ I n t ( 1 5 d o w n t o 4 ) = " 0 0 0 0 0 0 1 0 0 0 0 1 " a n dG C L K 2 = ' 1 ' ) e l s e ' 0 ' ; L C D _ C S _ O u t < = L C D _ C S a n d L C D _ S e l e c t ;
- - * * * * D a t a B u s M a n a g e m e n t * * * * - - ( P L D R e g i s t e r R e a d i n g ) w i t h H C 1 2 A d d r _ I n t ( 1 d o w n t o 0 ) s e l e c t P l d _ D a t a < = ( U p p e r _ A d d r e s s _ R e g ) w h e n " 0 0 " , - - A d d r S p a c e M a p p i n g R e g ( C l k _ R e g ) w h e n " 0 1 " , - - M i p s C l o c k S o u r c e R e g ( B u s _ R e g ) w h e n " 1 0 " , - - B u s F l o w D i r e c t i o n R e g ( C o n t r a s t _ R e g ) w h e n " 1 1 " , - - C o n t r a s t R e g ( " 1 0 1 0 " ) w h e n o t h e r s ;
- - t h e a b o v e o n l y d r i v e s t h e H C 1 2 D a t a b u s w h e n a r e a d o c c u r s o n - - t h e P L D A d d r e s s S p a c e H C 1 2 D a t a _ I n t < = ( " 0 0 0 0 " & P l d _ D a t a & " 0 0 0 0 " & P l d _ D a t a ) w h e n ( I n t _ n C S =' 0 ' ) e l s e E x t D e v i c e _ D a t a ;
DSL Development Board Rev 2/01/0122
- - - - - - - - * e n d * - P L D I n t e r n a l A d d r e s s S p a c e - * e n d * - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - B u s F l o w D i r e c t i o n - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - D e p e n d i n g o n t h e v a l u e s s e t i n B u s _ R e g , t h e D i r e c t i o n o f t h e - - B u s F l o w o f t h e m a y c h a n g e .
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t E x t D e v i c e _ D a t a < = ( R A M D a t a ) w h e n " 0 0 " , - - H C 1 2 I s C o n n e c t e d t o R A M / L C D - - w h e n " 0 1 " , - - H C 1 2 I s N o t C o n n e c t e d ( M i p s D a t a ) w h e n " 1 0 " , - - H C 1 2 I s C o n n e c t e d t o M i p s ( " 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 " ) w h e n o t h e r s ;
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t R a m D a t a _ I n t < = H C 1 2 D a t a w h e n " 0 0 " , - - H C 1 2 I s C o n n e c t e d t o R A M M i p s D a t a w h e n " 0 1 " , - - M i p s I s C o n n e c t e d t o R A M - - w h e n " 1 0 " , - - R A M I s N o t C o n n e c t e d " 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 " w h e n o t h e r s ;
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t R a m A d d r _ I n t < = ( H C 1 2 A d d r _ I n t _ E x t e n d e d ) w h e n " 0 0 " , - - H C 1 2 t o R A M ( M i p s A d d r _ I n t _ E x t e n d e d ) w h e n " 0 1 " , - - M i p s t o R A M - - w h e n " 1 0 " , - - R A M N o t C o n n e c t e d ( " 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 " ) w h e n o t h e r s ;
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t M i p s D a t a _ I n t < = - - w h e n " 0 0 " , - - M i p s N o t C o n n e c t e d ( R a m D a t a _ F i l t e r e d ) w h e n " 0 1 " , - - M i p s t o R A M ( H C 1 2 D a t a ) w h e n " 1 0 " , - - M i p s t o H C 1 2 ( " 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 " ) w h e n o t h e r s ;
- - W e r o u t e t h e a d d r e s s b u s t o t h e t w o p a r t s t h a t a r e w r i t t e n t o( w r i t e e s ) w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t M i p s A d d r _ I n t < = - - w h e n " 0 0 " , - - M i p s I s N o t C o n n e c t e d ( M i p s A d d r ) w h e n " 0 1 " , - - M i p s I s C o n n e c t e d t o R A M ( H C 1 2 A d d r _ I n t ) w h e n " 1 0 " , - - M i p s I s C o n n e c t e d t o H C 1 2 ( " 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 " ) w h e n o t h e r s ;
C r o p p e d _ M i p s _ A d d r < = M i p s A d d r ( 1 5 d o w n t o 1 3 ) & M i p s A d d r ( 3 d o w n t o 1 ) ;- - T h i s w a s d o n e t o c u t d o w n o n n u m o f l i n e s n e e d i n g t o b e m a t c h e d- - w i t h ( C r o p p e d _ M i p s _ A d d r ) s e l e c t s o t h e d e s i g n w o u l d f i t
R a m D a t a _ F i l t e r e d < = - - 0 x D 7 C 0 L U I r 7 0 x c 0 0 0 m a t c h e s 0 0 0 x x x x x x x x x 0 0 0 x " 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 " w h e n " 0 0 0 0 0 0 " , " 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 " w h e n " 0 0 0 0 0 1 " , - - 0 x 9 F 0 0 J R r 7 R a m D a t a w h e n o t h e r s ;
R a m A d d r < = R a m A d d r _ I n t ;
R a m D a t a < = R a m D a t a _ I n t w h e n ( ( B u s _ R e g ( 1 d o w n t o 0 ) = " 0 0 " a n d H C 1 2 _ n W E = ' 0 ' ) o r ( B u s _ R e g ( 1 d o w n t o 0 ) = " 0 1 " a n d M i p s _ R n W = ' 0 ' ) ) e l s e " Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z " ;
H C 1 2 D a t a < = H C 1 2 D a t a _ I n t w h e n ( H C 1 2 _ D a t a b u s _ E n = ' 1 ' ) e l s e " Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z " ; M i p s D a t a < = M i p s D a t a _ I n t w h e n ( M i p s _ D a t a b u s _ E n = ' 1 ' )
DSL Development Board Rev 2/01/0123
e l s e " Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z " ;
- - - - - - - * e n d * - B u s F l o w D i r e c t i o n - * e n d * - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - A d d r e s s S p a c e M a p p i n g - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - W i n d o w 0 x C 0 0 0 t h r o u g h m e m o r y d e p e n d i n g o n t h e v a l u e o f - - U p p e r A d d r e s s R e g
w i t h ( H C 1 2 A d d r _ I n t ( 1 5 d o w n t o 1 2 ) ) s e l e c t H C 1 2 A d d r _ I n t _ E x t e n d e d < = U p p e r _ A d d r e s s _ R e g ( 3 d o w n t o 0 ) & H C 1 2 A d d r _ I n t ( 1 3 d o w n t o 1 ) w h e n " 1 1 0 0 " , " 0 0 " & H C 1 2 A d d r _ I n t ( 1 5 d o w n t o 1 ) w h e n o t h e r s ;
w i t h ( M i p s A d d r _ I n t ( 1 5 d o w n t o 1 2 ) ) s e l e c t M i p s A d d r _ I n t _ E x t e n d e d < = U p p e r _ A d d r e s s _ R e g ( 3 d o w n t o 0 ) & M i p s A d d r _ I n t ( 1 3 d o w n t o 1 ) w h e n " 1 1 0 0 " " 0 0 " & M i p s A d d r _ I n t ( 1 5 d o w n t o 1 ) w h e n o t h e r s ;
- - - - - - - - * e n d * - A d d r e s s S p a c e M a p p i n g - * e n d * - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - C o n t r o l S i g n a l s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - T h e P L D R e g i s t e r S p a c e i s a t A d d r 0 x 0 2 0 0 t o 0 x 0 2 0 F - - ( R e g i s t e r F o l l o w i n g A r e a o f H C 1 2 ) - - t h e f o l l o w i n g l i n e c o n t r o l s r e a d i n g a n d w r i t t i n g t o - - t h e p l d r e g i s t e r s p a c e .
I n t _ n C S < = ' 0 ' w h e n ( H C 1 2 A d d r _ I n t ( 1 5 d o w n t o 4 ) = " 0 0 0 0 0 0 1 0 0 0 0 0 " a n d G C L K 2 = ' 1 ' ) e l s e ' 1 ' ;
H c 1 2 _ R a m _ n C S < = ' 0 ' w h e n ( H C 1 2 A d d r _ I n t ( 1 5 ) = ' 1 ' a n d G C L K 2 = ' 1 ' ) e l s e ' 1 ' ;
M i p s _ R a m _ n C S < = M i p s _ n C S ;
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t R a m _ n C S < = H C 1 2 _ R a m _ n C S w h e n " 0 0 " , - - H C 1 2 M i p s _ R a m _ n C S w h e n " 0 1 " , - - M i p s ' 1 ' w h e n o t h e r s ;
R A M _ n C S _ O u t < = R A M _ n C S w h e n ( ( L C D _ C S = ' 0 ' ) a n d ( I n t _ n C S = ' 1 ' ) ) e l s e ' 1 ' ;
- - O u t p u t E n a b l e s H C 1 2 _ n O E < = N O T ( G C L K 2 A N D H C 1 2 R n W ) ;
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t R A M _ n O E < = H C 1 2 _ n O E w h e n " 0 0 " , - - H C 1 2 M i p s _ n O E w h e n " 0 1 " , - - M i p s ' 1 ' w h e n o t h e r s ;
H C 1 2 _ D a t a b u s _ E n < = H C 1 2 R n W a n d G C L K 2 ; M i p s _ D a t a b u s _ E n < = M i p s _ R n W a n d N o t M i p s _ n C S ;
- - W r i t e E n a b l e s - - D o n ' t a l l o w R n W t o g o l o w w h e n A d d r i n f o i s o n t h e b u s H C 1 2 _ n W E < = H C 1 2 R n W O R ( N o t G C L K 2 ) ;
- - S e l e c t t h e l o w b y t e R A M f o r a w r i t e H C 1 2 _ n W E _ L < = H C 1 2 _ n W E O R n L S T R B ;
- - S e l e c t t h e h i g h b y t e R A M f o r a w r i t e H C 1 2 _ n W E _ H < = H C 1 2 _ n W E O R H C 1 2 A d d r _ I n t ( 0 ) ;
DSL Development Board Rev 2/01/0124
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t R A M _ n W E _ L < = H c 1 2 _ n W E _ L w h e n " 0 0 " , - - H C 1 2 M i p s _ R n W w h e n " 0 1 " , - - M i p s ' 1 ' w h e n o t h e r s ;
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t R a m _ n W E _ H < = H c 1 2 _ n W E _ H w h e n " 0 0 " , - - H C 1 2 M i p s _ R n W w h e n " 0 1 " , - - M i p s ' 1 ' w h e n o t h e r s ;
L C D _ n W E < = H C 1 2 _ n W E ; L C D _ R S < = H C 1 2 A d d r _ I n t ( 1 ) ;