Synopsys Insight Imagination’s approach to graphics processor unit (GPU) development is to provide scalable IP that can support the demands of a broad range of applications, from wearables and mobile devices to high-end gaming and computing. Satisfying the requirements of all of these markets is only possible by creating architectures that can deliver the highest levels of performance while minimizing both area and power. Prototyping Imagination’s PowerVR Series6XT Dual-Cluster 64-Core GPU Want more articles like this? Synopsys Insight can be delivered to your inbox quarterly. Visit www.synopsys.com/Insight to read recent articles and subscribe to the quarterly newsletter Power to Perform The PowerVR ® Rogue architecture has helped Imagination take a market-leading position — measured in terms of GFLOPS/ mm2 and GFLOPS/mW — over several generations of GPUs. In order to achieve the highest levels of performance, GPU architectures harness significant parallel processing power to perform the most demanding graphics and GPU compute tasks. Consequently, configuring GPU IP to deliver advanced processing features and high performance can result in complex, high gate-count devices — often substantially larger than an SoC’s application processor IP. Across the PowerVR Series6 GPU cores, the largest GPU configuration is eight times that of the smallest GPU (Figure 1). A key challenge faced by Imagination’s design team is how to test GPUs as they become larger and more complex. Historically, use of FPGA-based prototyping has been limited as top-end GPUs exceed the capacity of the largest available FPGA devices and the manual partitioning of the data-path intensive GPU structures to multiple FPGAs has proven to be a time-consuming and difficult process. As a result, the only feasible approach has been to fabricate test chips — an increasingly expensive and time-consuming process, which delays final product lead times. Figure 1: Imagination’s PowerVR architecture (image provided at the courtesy of Imagination Technologies) Excerpt: Issue 4 | 2014 A quarterly publication providing insights on accelerating innovation for designers Unified shading cluster array Control and register bus System memory bus Host CPU interface Vertex data master USC0 USCn-1 USCn Texture unit Texture unit . . . USC1 Coarse grain scheduler Pixel data master Compute data master Core management unit Multi-level memory cache unit (MCU) Tiling co-processor Pixel co-processor 2D core (TLA) Host CPU bus System memory run System memory interface ASTC* PVRTC Extra low power GFLOPS * Supports both LDR and HDR ASTC formats *PowerVR ® is a registered trademark of Imagination Technologies About the Author Andy Jolley is Senior Staff Application Consultant – Worldwide Product Line Lead, FPGA-Based Prototyping at Synopsys. Andy has been working with FPGA technologies for over 25 years, originally in a design capacity in the telecommunications, radar and video industries before supporting FPGA synthesis and prototyping technologies at Synplicity and then Synopsys. Most recently, Andy has been supporting UK customers with their complex CPU SoC and GPU IP prototyping needs on the Synopsys HAPS platforms while also providing support for worldwide engagements to deploy the same SoC and GPU IPs embedded into user applications. Andy holds a Bachelor’s Degree in Electronic Engineering from the University of Brighton, England.
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Prototyping Imagination’s PowerVR Series6XT Dual … · Imagination’s approach to ... of performance while minimizing both area and power. Prototyping Imagination’s PowerVR
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Synopsys InsightImagination’s approach to graphics processor unit (GPU) development is to provide scalable IP that can support the demands of a broad range of applications, from wearables and mobile devices to high-end gaming and computing. Satisfying the requirements of all of these markets is only possible by creating architectures that can deliver the highest levels of performance while minimizing both area and power.
Want more articles like this? Synopsys Insight can be delivered to your inbox quarterly.
Visit www.synopsys.com/Insight to read recent articles and subscribe to the quarterly newsletter
Power to PerformThe PowerVR® Rogue architecture has
helped Imagination take a market-leading
position — measured in terms of GFLOPS/
mm2 and GFLOPS/mW — over several
generations of GPUs. In order to achieve
the highest levels of performance, GPU
architectures harness significant parallel
processing power to perform the most
demanding graphics and GPU compute
tasks. Consequently, configuring GPU IP
to deliver advanced processing features
and high performance can result in
complex, high gate-count devices —
often substantially larger than an SoC’s
application processor IP. Across the
PowerVR Series6 GPU cores, the largest
GPU configuration is eight times that of
the smallest GPU (Figure 1).
A key challenge faced by Imagination’s
design team is how to test GPUs as
they become larger and more complex.
Historically, use of FPGA-based
prototyping has been limited as top-end
GPUs exceed the capacity of the largest
available FPGA devices and the manual
partitioning of the data-path intensive
GPU structures to multiple FPGAs has
proven to be a time-consuming and
difficult process. As a result, the only
feasible approach has been to fabricate
test chips — an increasingly expensive and
time-consuming process, which delays
final product lead times.
Figure 1: Imagination’s PowerVR architecture (image provided at the courtesy of Imagination Technologies)
Excerpt: Issue 4 | 2014A quarterly publication providing insights on accelerating innovation for designers
Unified shading cluster array
Control and register bus
System memory bus
Host CPUinterface
Vertexdata master USC0
USCn-1 USCn
Textureunit
Textureunit
...
USC1Coarsegrain
schedulerPixel
data master
Computedata master
Coremanagement
unitMulti-level memory cache unit (MCU)
Tilingco-processor
Pixelco-processor
2D core(TLA)
HostCPUbus
Systemmemory
run Systemmemoryinterface
ASTC*
PVRTC
Extra low power GFLOPS
* Supports both LDR and HDR ASTC formats
*PowerVR® is a registered trademark of
Imagination Technologies
About the AuthorAndy Jolley is Senior Staff Application Consultant – Worldwide Product Line Lead, FPGA-Based Prototyping at Synopsys. Andy has been working with FPGA technologies for over 25 years, originally in a design capacity in the telecommunications, radar and video industries before supporting FPGA synthesis and prototyping technologies at Synplicity and then Synopsys. Most recently, Andy has been supporting UK customers with their complex CPU SoC and GPU IP prototyping needs on the Synopsys HAPS platforms while also providing support for worldwide engagements to deploy the same SoC and GPU IPs embedded into user applications. Andy holds a Bachelor’s Degree in Electronic Engineering from the University of Brighton, England.