Proposal Proposal : : Design of a 2.5 Design of a 2.5 Gbps Radiation Tolerant Gbps Radiation Tolerant SerDes for the CBM–DAQ in SerDes for the CBM–DAQ in 180 nm CMOS process 180 nm CMOS process Pradeep Banerjee, Pradeep Banerjee, Dr. T. K. Bhattacharyya, E & ECE Dept., Dr. T. K. Bhattacharyya, E & ECE Dept., Indian Institute of Technology, Indian Institute of Technology, Kharagpur Kharagpur CBM Collaboration Meeting, VECC, CBM Collaboration Meeting, VECC, Kolkata Kolkata 31 31 st st July, 2010 July, 2010
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Proposal : Design of a 2.5 Gbps Radiation Tolerant SerDes for the CBM–DAQ in 180 nm CMOS process
Proposal : Design of a 2.5 Gbps Radiation Tolerant SerDes for the CBM–DAQ in 180 nm CMOS process. Pradeep Banerjee, Dr. T. K. Bhattacharyya, E & ECE Dept., Indian Institute of Technology, Kharagpur CBM Collaboration Meeting, VECC, Kolkata 31 st July, 2010. Outline. - PowerPoint PPT Presentation
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ProposalProposal:: Design of a 2.5 Design of a 2.5 Gbps Radiation Tolerant Gbps Radiation Tolerant SerDes for the CBM–DAQ in SerDes for the CBM–DAQ in 180 nm CMOS process180 nm CMOS process
Pradeep Banerjee,Pradeep Banerjee,
Dr. T. K. Bhattacharyya, E & ECE Dept.,Dr. T. K. Bhattacharyya, E & ECE Dept.,
Indian Institute of Technology, KharagpurIndian Institute of Technology, Kharagpur
STS Data Rates – Aggregation STS Data Rates – Aggregation
Hit rate [MHz]
Sta0
Sta 1
Sta 2
Sta 3
Sta 4
Sta 5
Sta 6
Sta 7
Total
32-64 21 14 9 1 0 0 0 0 45
16-32 67 72 157 116 73 60 1 1 547
8-16 208 357 477 555 325 430 157 189 2698
4-8 494 521 250 440 964 785 1048
753 5255
2-4 441 376 51 24 219 294 693 1079
3177
1-2 104 51 0 0 3 5 21 90 274
0.5-1 1 1 0 0 0 4 0 0 6
Total 1336 1392 944 1136 1584 1578
1920
2112
12002
Very few chip in inner region have hit rate > 32 MHz > 90% of chips have hit rates in 2...16 MHz range AMPLE SCOPE FOR DATA AGGREGATION AMPLE SCOPE FOR DATA AGGREGATION
Hit rate per chip StatisticsHit rate per chip StatisticsAu+Au @ 25 AGevAu+Au @ 25 AGev
101077 evt/sec evt/sec
Slide Data from: Slide Data from: Walter F.J. Müller, GSI
31.25 MHz hit rate (80 bits/hit) 31.25 MHz hit rate (80 bits/hit) 2.5 2.5 Gbps Gbps
STS FEB Type and Link DistributionSTS FEB Type and Link Distribution
38 chips exceed 2.0 Gbps: 29 with 2.0 … 2.4; 9 with 2.4 … 3.2; # of FEBs and type distributions varies for stations All 8 chips combined give less than 2.5 Gbps (Aggregation Possible) --> FEBa8 A single chip gives data worth 2.5 Gbps (No Aggregation possible) --> FEBa1
Slide Data from: Slide Data from: Walter F.J. Müller, GSI
A peep into some feasible ‘Hub’ ASIC A peep into some feasible ‘Hub’ ASIC Requirements – Requirements – Initial Proposal from Dr. MullerInitial Proposal from Dr. Muller
Capacity for data aggregation from several Readout-ASICs into a single output link 1 ‘hub’ ASIC may contain 6 high speed Serializers : 6 Tx for data 15 Gbps
serviceable data bandwidth 1 Rx – 1 Tx channel for clock, sync, control 250 MHz sys clock as Transmit clk 500 Mbps (DDR LVDS) input interface 5-8 LVDS o/p links (each 500 Mbps) per chip (8 chips per FEB)
FEBa8 case : 1 LVDS link per chip: combine data upto 6 FEBs (48 LVDS links) per Hub FEBa1 case : All 6 LVDS links (single chip) per Serializer
Multiple Serializer Core: Design Multiple Serializer Core: Design ChallengesChallenges Jitter-free Clock signal Minimize noise contribution of VCO (Total serial
o/p jitter < 120 ps for BER ~ 10-12)
Switching noise generated by digital logic in ASIC
Constant phase relationship b/w VCO and Sys clock (400 ps bit time)
Multiple Serializer cores per chip: Power efficiency, ASIC footprint Sharing a single frequency multiplier among several Serializer cores in the same ASIC :
Distributing multi-gigahertz clocks over an extended distance consumes lot of power Signal integrity issues percentage of area saved as a function of the number of cores for a PLL that is half the size of a Serializer core saturates beyond 4 Careful planning on circuit layout buffering high speed clock in cascade actually worsens jitter performance
Total Ionizing Dose (TIID) Effects Issues : threshold-voltage shifts, mobility degradation, and isolation related
leakage Remedy : “Radiation tolerant Layout techniques” – Systematic use of
Annular Symmetric Enclosed Layout Transistors (ELT) and p+ guard rings between the n+ diffusions
Single Event Effects (SEE) Variants:
Non-Destructive : Single Event Upset (SEU), Single Event Transient (DSET) Destructive : Single Event Latch-Up (SEL)
Issues: SEU : Depending on the LET, if parasitic charge > node critical charge, a
logical switch may occur (bit flip) DSET : Error rate depends linearly on Clock frequency (glitch) SEL : Parasitic thyristor structure leading to latch-up
Observations/Experience in CBM Radiation Environment:
TID : MUCH plane 1 (at 130 cm) : deposited energy (rad/CBM-yr) at perimeter: ~30krad/yr, in center: ~500krad/yr Not necessary to have all transistors with ELT layout
SEL : Not seen as an issue in tests so far in deep submicron CMOS
Approach: Work Plan Freeze System level/Interface Specs
Design an appropriate architecture for the High speed Serializer core
Design and Implementation of the Peripheral cores in UMC 180μm process: CMU CDR Serializer and 50 ohm output Impedance driver
Characterization of UMC 0.18μm CMOS process concerning the vulnerability against SEU / SETs SEU cross section for different High speed Flip-Flop, Multiplexer designs and
layouts Characterization of the critical charge Qcrit /Linear Energy Transfer (LETcrit) SET sensitivity of the UMC 0.18μm process
Testing : Functionality/Performance : Design of different Testing/Digital blocks:
Pseudo Random Sequence generator (PRSG) 8B/10B encoder, FIFOs FPGA devices to program the Serializer Test Configuration generation of Test data patterns monitor PLL’s locking state, etc.
Approach: Work Plan – Year 1I. Complete literature review and definition of a suitable architecture
for the SerDes for operation up to 2.5 Gbps.
II. Top level modeling of the RF Front end blocks (CMU, CDR) with System level software.
III. Set up complete process flow for UMC 180 nm CMOS.
IV. Assess the SEU sensitivity of important sub-blocks, including the VCO, PLL loop filter, etc. and identify design criteria, simulation method and means of alleviating the same.
V. Design/Tape-out (Phase I) of transistor test structures as well as primitives like high speed multiplexers, latches, flip flops with standard and enclosed layouts for technology evaluation and for precise modeling of radiation hard devices.
VI. Complete design, layout and simulation of the CDR and CMU
CONTINGENCY & OVERHEAD FOR IIT KHARAGPUR = Rs 6,00,000
Contingent items including Software license fees for CAD tools for VLSI design, publications, report writing, etc.
Rs 3,00,000 Rs 3,00,000
MOBILITY COST OF RESEARCHERS (Travel Cost only) = Rs 12,00,000
From India to GSI: Short Term Visit: 2 visits of Project Coordinator/year + 3 visits of Project based staff: 1 PhD scholar, 2 Project Staff/yearFrom GSI to India: Short Term Visits: 6 visits for 18 man months over three years (Short term visits: either of 10 days or up to 3 months duration/year) + Local Hospitality